CHAPTER 9
REGISTERS
Q-1 Draw the diagram for a MOD-10 Johnson counter using J-K flip-flops and
determine its counting sequence. Draw the decoding circuit needed to decode
each of the 10 states.
A-1 The diagram for the MOD-10 Johnson counter using J-K flip-flops is as shown in
the following figure.
J4 Q4 J3 Q3 J2 Q2 J1 Q1 J0 Q0
K4 Q4 K3 Q3 K2 Q2 K1 Q1 K0 Q0
Q4 Q3 Q2 Q1 Q0
CLK
The counting sequence of the circuit is as shown in the following figure.
Q4 Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 0
1 1 0 0 0
1 1 1 0 0
1 1 1 1 0
1 1 1 1 1
0 1 1 1 1
0 0 1 1 1
0 0 0 1 1
0 0 0 0 1
0 0 0 0 0
The decoding circuit of all the states is as shown in the following figure.
1
D J4 Q4 J3 Q3 J2 Q2 J1 Q1 J0 Q0
K4 Q4 K3 Q3 K2 Q2 K1 Q1 K0 Q0
CLK
CLR
Q-2 Determine the frequency of the pulses at points w, x, y and z in the circuit of the
following figure.
A-2 The frequency of pulses at various points as shown in the above figure is as
follows:
10 Hz
Q-3 Design a shift register with parallel load that operates according to the following
function table:
A-3 The circuit for the above shift register can be drawn as shown in the following
figure.
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CLK
Q-4 The content of a 4-bit register is initially 1101. The register is shifted 6 times to
the right with the serial input being 101101. What is the content of the register
after each shift?
A-4 The content of the register after each shift is as shown in the following figure.
Q-5 What is the state of the register in the following figure after each clock pulse if it
starts in the 101001111000 state?
3
Data in
A-5 The state of the register on each clock pulse is as follows:
000011110000
Q-6 For the serial-in-serial-out shift register, determine the output waveform for the
data input and clock waveforms in the following figure.
CLK
Data in
A-6 The output waveform of the above data input is as shown in the following figure:
4
CLK
Data in
Data out
Q-7 Design a MOD-7 Johnson counter using J-K flip-flop.
Note: Problem 7 can be solved in the similar manner that is followed in problem 1.
Q-8 Design a self-correcting MOD-9 shift counter using D flip-flop.
A-8 Step 1 State diagram: The design of the 4-bit ring counter is as shown in the
following figure.
0000
1000
0001 0100
0010
Step 2 State table: PS-NS table of the ring counter can be drawn from the above
state diagram, as shown in the following figure.
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PS NS
qA qB qC qD QA QB QC QD
0 0 0 0 1 0 0 0
0 0 0 1 1 0 0 0
0 0 1 0 0 0 0 1
0 0 1 1 d d d d
0 1 0 0 0 0 1 0
0 1 0 1 d d d d
0 1 1 0 d d d d
0 1 1 1 d d d d
1 0 0 0 0 1 0 0
1 0 0 1 d d d d
1 0 1 0 d d d d
1 0 1 1 d d d d
1 1 0 0 d d d d
1 1 0 1 d d d d
1 1 1 0 d d d d
1 1 1 1 d d d d
Step 3 Excitation table: The excitation table of the ring counter can be drawn
from the PS-NS table and application of D flip-flop as shown in the following
table.
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PS NS Excitation inputs
qA qB qC qD QA QB QC QD DA DB DC DD
0 0 0 0 1 0 0 0 1 0 0 0
0 0 0 1 1 0 0 0 1 0 0 0
0 0 1 0 0 0 0 1 0 0 0 1
0 0 1 1 d d d d d d d d
0 1 0 0 0 0 1 0 0 0 1 0
0 1 0 1 d d d d d d d d
0 1 1 0 d d d d d d d d
0 1 1 1 d d d d d d d d
1 0 0 0 0 1 0 0 0 1 0 0
1 0 0 1 d d d d d d d d
1 0 1 0 d d d d d d d d
1 0 1 1 d d d d d d d d
1 1 0 0 d d d d d d d d
1 1 0 1 d d d d d d d d
1 1 1 0 d d d d d d d d
1 1 1 1 d d d d d d d d
Step 4 Excitation maps: The excitation maps of the ring counter can be created
as shown in the following figure.
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qAqB qAqB
qCqD 00 01 11 10 qCqD 00 01 11 10
00 1 0 d 0 00 0 0 d 1
01 1 d d d 01 0 d d d
11 d d d d 11 d d d d
10 0 d d d 10 0 d d d
(a) for DA (b) for DB
DA = qA qB qC DB = qA
qAqB qAqB
qCqD 00 01 11 10 qCqD 00 01 11 10
00 0 1 d 0 00 0 0 d 0
01 0 d d d 01 0 d d d
11 d d d d 11 d d d d
10 0 d d d 10 1 d d d
(c) for DC (d) for DD
DC = qB DD = qC
Step 5 Schematic diagram: The circuit diagram for the ring counter can be
drawn by using the above equations as shown in the following figure.
QA QB QC QD
D Q D Q D Q D Q
A B C D
Q Q Q Q
CLR CLR CLR CLR
CLK
CLK
Q-9 Design a 4-bit self correcting ring counter which is capable of rotating 1 in left
direction.
8
A-9 Step 1 State diagram: The design of the 4-bit self correcting ring counter is as
shown in the following figure.
0000
0001
1000 0010
0100
Step 2 State table: PS-NS table of the self correcting ring counter can be drawn
from the above state diagram, as shown in the following figure.
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PS NS
qA qB qC qD QA QB QC QD
0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 0
0 0 1 0 0 1 0 0
0 0 1 1 d d d d
0 1 0 0 1 0 0 0
0 1 0 1 d d d d
0 1 1 0 d d d d
0 1 1 1 d d d d
1 0 0 0 0 0 0 1
1 0 0 1 d d d d
1 0 1 0 d d d d
1 0 1 1 d d d d
1 1 0 0 d d d d
1 1 0 1 d d d d
1 1 1 0 d d d d
1 1 1 1 d d d d
Step 3 Excitation table: The excitation table of the self correcting ring counter
can be drawn from the PS-NS table and application of D flip-flop as shown in the
following table.
10
PS NS Excitation inputs
qA qB qC qD QA QB QC QD DA DB DC DD
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 1 0 0 0 1 0
0 0 1 0 0 1 0 0 0 1 0 0
0 0 1 1 d d d d d d d d
0 1 0 0 1 0 0 0 1 0 0 0
0 1 0 1 d d d d d d d d
0 1 1 0 d d d d d d d d
0 1 1 1 d d d d d d d d
1 0 0 0 0 0 0 1 0 0 0 1
1 0 0 1 d d d d d d d d
1 0 1 0 d d d d d d d d
1 0 1 1 d d d d d d d d
1 1 0 0 d d d d d d d d
1 1 0 1 d d d d d d d d
1 1 1 0 d d d d d d d d
1 1 1 1 d d d d d d d d
Step 4 Excitation maps: The excitation maps of the ring counter can be created
as shown in the following figure.
11
qCqD
qCqD
qAqB 00 01 11 10 00 01 11 10
qAqB
00 0 0 d 0 00 0 0 d 1
01 1 d d d 01 0 d d d
11 d d d d 11 d d d d
10 0 d d d 10 0 d d d
(a) for DA (b) for DB
DA = qB DB = q C
qCqD qCqD
qAqB 00 01 11 10 qAqB 00 01 11 10
00 0 1 d 0 00 1 0 d 0
01 0 d d d 01 0 d d d
11 d d d d 11 d d d d
10 0 d d d 10 1 d d d
(c) for DC (d) for DD
DC = qD DD = qB qCqD
Step 5 Schematic diagram: The circuit diagram for the self correcting ring
counter can be drawn by using the above equations as shown in the following
figure.
QA QB QC QD
D Q D Q D Q D Q
A B C D
Q Q Q Q
CLR CLR CLR CLR
CLR
CLK
Q-10 Design a 5-bit self-correcting ring counter.
Note: Problem 10 can be solved in the similar manner that is followed in problem 8.
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