Functional Units of a Computer b) When the data arrives 2.

The instruction -> Add LOCA,

regardless of the SIN flag R0 does _______
1. The ______ format is usually c) Neither of the cases a) Adds the value of LOCA to R0
used to store data. d) Either of the cases and stores in the temp register
a) BCD b) Adds the value of R0 to the
b) Decimal address of LOCA
c) Hexadecimal 10. ______ bus structure is c) Adds the values of both
d) Octal usually used to connect I/O LOCA and R0 and stores it in
devices. R0
2. The 8-bit encoding format a) Single bus d) Adds the value of LOCA with
used to store data in a computer b) Multiple bus a value in accumulator and
is ______ c) Star bus stores it in R0
a) ASCII d) Rambus
b) EBCDIC 3. Which registers can interact
c) ANCI 11. The I/O interface required to with the secondary storage?
d) USCII connect the I/O device to the bus a) MAR
consists of ______ b) PC
3. A source program is usually in a) Address decoder and c) IR
_______ registers d) R0
a) Assembly language b) Control circuits
b) Machine level language c) Address decoder, registers 4. During the execution of a
c) High-level language and Control circuits program which gets initialized
d) Natural language d) Only Control circuits first?
a) MDR
4. Which memory device is 12. To reduce the memory b) IR
generally made of access time we generally make c) PC
semiconductors? use of ______ d) MAR
a) RAM a) Heaps
b) Hard-disk b) Higher capacity RAM’s 5. Which of the register/s of the
c) Floppy disk c) SDRAM’s processor is/are connected to
d) Cd disk d) Cache’s Memory Bus?
a) PC
5. The small extremely fast, 13. ______ is generally used to b) MAR
RAM’s are called as _______ increase the apparent size of c) IR
a) Cache physical memory. d) Both PC and MAR
b) Heaps a) Secondary memory
c) Accumulators b) Virtual memory 6. ISP stands for _________
d) Stacks c) Hard-disk a) Instruction Set Processor
d) Disks b) Information Standard
6. The ALU makes use of Processing
_______ to store the 14. MFC stands for c) Interchange Standard
intermediate results. ___________ Protocol
a) Accumulators a) Memory Format Caches d) Interrupt Service Procedure
b) Registers b) Memory Function Complete
c) Heap c) Memory Find Command 7. The internal components of
d) Stack d) Mass Format Command the processor are connected by
_______
7. The control unit controls other 15. The time delay between two a) Processor intra-connectivity
units by generating successive initiations of memory circuitry
___________ operation _______ b) Processor bus
a) Control signals a) Memory access time c) Memory bus
b) Timing signals b) Memory search time d) Rambus
c) Transfer signals c) Memory cycle time
d) Command Signals d) Instruction delay 8. ______ is used to choose
between incrementing the PC or
performing ALU operations.
8. ______ are numbers and Basic Operational Concept
encoded characters, generally a) Conditional codes
used as operands. b) Multiplexer
1. The decoded instruction is c) Control unit
a) Input
stored in ______ d) None of the mentioned
b) Data
a) IR
c) Information
b) PC 9. The registers, ALU and the
d) Stored Values
c) Registers interconnection between them
d) MDR are collectively called as _____
9. The Input devices can send
information to the processor. a) process route
a) When the SIN status flag is b) information trail
set c) information path
d) data path b) Takes advantage of the type Basic performance equation)?
of processor and reduces its a) 3
10. _______ is used to store process time b) ~2
data in registers. c) Does better memory c) ~1
a) D flip flop management d) 6
b) JK flip flop d) None of the mentioned 14. CISC stands for _______
c) RS flip flop a) Complete Instruction
d) None of the mentioned 7. The ultimate goal of a Sequential Compilation
compiler is to ________ b) Computer Integrated
1. During the execution of the a) Reduce the clock cycles for Sequential Compiler
instructions, a copy of the a programming task c) Complex Instruction Set
instructions is placed in the b) Reduce the size of the object Computer
______ code d) Complex Instruction
a) Register c) Be versatile Sequential Compilation
b) RAM d) Be able to detect even the
c) System heap smallest of errors 15. As of 2000, the reference
d) Cache system to find the SPEC rating
8. SPEC stands for _______ are built with _____ Processor.
2. Two processors A and B have a) Standard Performance a) Intel Atom SParc 300Mhz
clock frequencies of 700 Mhz Evaluation Code b) Ultra SPARC -IIi 300MHZ
and 900 Mhz respectively. b) System Processing c) Amd Neutrino series
Suppose A can execute an Enhancing Code d) ASUS A series 450 Mhz
instruction with an average of 3 c) System Performance
steps and B can execute with an Evaluation Corporation This set of Computer
average of 5 steps. For the d) Standard Processing Organization and Architecture
execution of the same instruction Enhancement Corporation Multiple Choice Questions &
which processor is faster? Answers (MCQs) focuses on
a) A 9. As of 2000, the reference “Addressing Modes”.
b) B system to find the performance
c) Both take the same time of a system is _____
d) Insufficient information a) Ultra SPARC 10 1. The instruction, Add #45,R1
b) SUN SPARC does _______
3. A processor performing fetch c) SUN II a) Adds the value of 45 to the
or decoding of different d) None of the mentioned address of R1 and stores 45 in
instruction during the execution that address
of another instruction is called 10. When Performing a looping b) Adds 45 to the value of R1
______ operation, the instruction gets and stores it in R1
a) Super-scaling stored in the ______ c) Finds the memory location 45
b) Pipe-lining a) Registers and adds that content to that of
c) Parallel Computation b) Cache R1
d) None of the mentioned c) System Heap d) None of the mentioned
d) System stack
4. For a given FINITE number of 2. In the case of, Zero-address
instructions to be executed, 11. The average number of instruction method the operands
which architecture of the steps taken to execute the set of are stored in _____
processor provides for a faster instructions can be made to be a) Registers
execution? less than one by following b) Accumulators
a) ISA _______ c) Push down stack
b) ANSA a) ISA d) Cache
c) Super-scalar b) Pipe-lining
d) All of the mentioned c) Super-scaling 3. Add #45, when this instruction
d) Sequential is executed the following
5. The clock rate of the happen/s _______
processor can be improved by 12. If a processor clock is rated a) The processor raises an error
_________ as 1250 million cycles per and requests for one more
a) Improving the IC technology second, then its clock period is operand
of the logic circuits ________ b) The value stored in memory
b) Reducing the amount of
-10
a) 1.9 * 10 sec location 45 is retrieved and
processing done in one step
-9
b) 1.6 * 10 sec one more operand is
c) By using the overclocking
-10
c) 1.25 * 10 sec requested
method
-10
d) 8 * 10 sec c) The value 45 gets added to
d) All of the mentioned the value on the stack and is
pushed onto the stack
6. An optimizing Compiler does 13. If the instruction, Add R1, d) None of the mentioned
_________ R2, R3 is executed in a system
a) Better compilation of the given that is pipe-lined, then the value
piece of code of S is (Where S is a term of the
4. The addressing mode which b) Indirect 8. In a normal adder circuit, the
makes use of in-direction c) Index with Offset delay obtained in a generation of
pointers is ______ d) Immediate the output is _______
a) Indirect addressing mode Fast Adders a) 2n + 2
b) Index addressing mode This set of Computer b) 2n
c) Relative addressing mode Organization and Architecture c) n + 2
d) Offset addressing mode Multiple Choice Questions & d) None of the mentioned
Answers (MCQs) focuses on
“Fast Adders”. 9. The final addition sum of the
5. In the following indexed numbers, 0110 & 0110 is
addressing mode instruction, ____________
MOV 5(R1), LOC the effective 1. The logic operations are a) 1101
address is ______ simpler to implement using logic b) 1111
a) EA = 5+R1 circuits. c) 1001
b) EA = R1 a) True d) 1010
c) EA = [R1] b) False
d) EA = 5+[R1] 10. The delay reduced to in the
2. The logic operations are carry look ahead adder is
6. The addressing mode/s, implemented using _______ __________
which uses the PC instead of a circuits. a) 5
general purpose register is a) Bridge b) 8
______ b) Logical c) 10
a) Indexed with offset c) Combinatorial d) 2n
b) Relative d) Gate
Multiplication
c) Direct
d) Both Indexed with offset and 3. The carry generation function:
direct ci + 1 = yici + xici + xiyi, is 1. The product of 1101 & 1011 is
implemented in ____________ ______
7. When we use auto increment a) Half adders a) 10001111
or auto decrements, which of the b) Full adders b) 10101010
following is/are true? c) Ripple adders c) 11110000
1) In both, the address is used to d) Fast adders d) 11001100
retrieve the operand and then
the address gets altered 4. Which option is true regarding 2. We make use of ______
2) In auto increment, the the carry in the ripple adders? circuits to implement
operand is retrieved first and a) Are generated at the multiplication.
then the address altered beginning only a) Flip flops
3) Both of them can be used on b) Must travel through the b) Combinatorial
general purpose registers as configuration c) Fast adders
well as memory locations c) Is generated at the end of d) None of the mentioned
a) 1, 2, 3 each operation
b) 2 d) None of the mentioned 3. The multiplier is stored in
c) 1, 3 ______
d) 2, 3 5. In full adders the sum circuit is a) PC Register
implemented using ________ b) Shift register
8. The addressing mode, where a) And & or gates c) Cache
you directly specify the operand b) NAND gate d) None of the mentioned
value is _______ c) XOR
a) Immediate d) XNOR 4. The ______ is used to
b) Direct coordinate the operation of the
c) Definite 6. The usual implementation of multiplier.
d) Relative the carry circuit involves a) Controller
_________ b) Coordinator
a) And & or gates c) Control sequencer
9. The effective address of the b) XOR d) None of the mentioned
following instruction is MUL c) NAND
5(R1,R2). d) XNOR 5. The multiplicand and the
a) 5+R1+R2 control signals are passed
b) 5+(R1*R2) 7. A _______ gate is used to through to the n-bit adder via
c) 5+[R1]+[R2] detect the occurrence of an _____
d) 5*([R1]+[R2]) overflow. a) MUX
a) NAND b) DEMUX
10. _____ addressing mode is b) XOR c) Encoder
most suitable to change the c) XNOR d) Decoder
normal sequence of execution of d) AND
instructions. 6. The product of -13 & 11 is
a) Relative ______________
a) 1100110011 number. c) Optimizing compilers
b) 1101110001 a) Sign d) None of the mentioned
c) 1010101010 b) Significant digits
d) 1111111000 c) Scale factor 2. The pipelining process is also
d) All of the mentioned called as ______
7. The method used to reduce a) Superscalar operation
the maximum number of 5. The sign followed by the string b) Assembly line operation
summands by half is _______ of digits is called as ______ c) Von Neumann cycle
a) Fast multiplication a) Significant d) None of the mentioned
b) Bit-pair recording b) Determinant
c) Quick multiplication c) Mantissa 3. The fetch and execution
d) None of the mentioned d) Exponent cycles are interleaved with the
help of ________
8. The bits 1 & 1 are recorded as 6. In IEEE 32-bit a) Modification in processor
_______ in bit-pair recording. representations, the mantissa of architecture
a) -1 the fraction is said to occupy b) Clock
b) 0 ______ bits. c) Special unit
c) +1 a) 24 d) Control unit
d) both -1 and 0 b) 23
c) 20 4. Each stage in pipelining
9. The multiplier -6(11010) is d) 16 should be completed within
recorded as _______ ___________ cycle.
a) 0-1-2 7. The normalized a) 1
b) 0-1+1-10 representation of 0.0010110 * b) 2
c) -2-10 2 9 is _______ c) 3
d) None of the mentioned a) 0 10001000 0010110 d) 4
b) 0 10000101 0110
10. CSA stands for? c) 0 10101010 1110 5. In pipelining the task which
a) Computer Speed Addition d) 0 11110100 11100 requires the least time is
b) Carry Save Addition performed first.
c) Computer Service 8. The 32 bit representation of a) True
Architecture the decimal number is called as b) False
d) None of the mentioned ___________
a) Double-precision 6. If a unit completes its task
Representation of Floating b) Single-precision before the allotted time period,
Number c) Extended format then _______
d) None of the mentioned a) It’ll perform some other task in
the remaining time
1. The decimal numbers
9. In 32 bit representation the b) Its time gets reallocated to a
represented in the computer are
scale factor as a range of different task
called as floating point numbers,
________ c) It’ll remain idle for the
as the decimal point floats
a) -128 to 127 remaining time
through the number.
a) True b) -256 to 255 d) None of the mentioned
c) 0 to 255
b) False
d) None of the mentioned 7. To increase the speed of
memory access in pipelining, we
10. In double precision format, make use of _______
2. The numbers written to the the size of the mantissa is a) Special memory locations
power of 10 in the representation ______ b) Special purpose registers
of decimal numbers are called a) 32 bit c) Cache
as _____ b) 52 bit d) Buffers
a) Height factors c) 64 bit
b) Size factors d) 72 bit 8. The periods of time when the
c) Scale factors unit is idle is called as _____
d) None of the mentioned Pipe-lining a) Stalls
This set of Computer b) Bubbles
3. If the decimal point is placed Organization and Architecture c) Hazards
to the right of the first significant Multiple Choice Questions & d) Both Stalls and Bubbles
digit, then the number is called Answers (MCQs) focuses on
________ “Pipe-lining”. 9. The contention for the usage
a) Orthogonal of a hardware device is called
b) Normalized ______
c) Determinate 1. ______ have been developed a) Structural hazard
d) None of the mentioned specifically for pipelined b) Stalk
systems. c) Deadlock
4. ________ constitute the a) Utility software d) None of the mentioned
representation of the floating b) Speed up utilities
10. The situation wherein the d) TLB CISC.
data of operands are not a) True
available is called ______ 8. The step where in the results b) False
a) Data hazard stored in the temporary register
b) Stock is transferred into the permanent 5. The iconic feature of the RISC
c) Deadlock register is called as ______ machine among the following is
d) Structural hazard a) Final step _______
b) Commitment step a) Reduced number of
Superscalar Processors c) Last step addressing modes
d) Inception step b) Increased memory size
c) Having a branch delay slot
9. A special unit used to govern d) All of the mentioned
1. The throughput of a super the out of order execution of the
scalar processor is _______ instructions is called as ______
a) less than 1 a) Commitment unit
b) 1 b) Temporal unit 6. Both the CISC and RISC
c) More than 1 c) Monitor architectures have been
d) Not Known d) Supervisory unit developed to reduce the ______
a) Cost
10. The commitment unit uses a b) Time delay
queue called ______ c) Semantic gap
2. When the processor executes a) Record buffer d) All of the mentioned
multiple instructions at a time it b) Commitment buffer
is said to use _______ c) Storage buffer 7. Out of the following which is
a) single issue d) None of the mentioned not a CISC machine.
b) Multiplicity a) IBM 370/168
c) Visualization b) VAX 11/780
CISC and RISC Processors
d) Multiple issues c) Intel 80486
d) Motorola A567
3. The ______ plays a very vital This set of Computer
role in case of super scalar Organization and Architecture 8. Pipe-lining is a unique feature
processors. Multiple Choice Questions & of _______
a) Compilers Answers (MCQs) focuses on a) RISC
b) Motherboard “CISC and RISC Processors”. b) CISC
c) Memory c) ISA
d) Peripherals d) IANA
1. The CISC stands for
4. If an exception is raised and ___________
9. In CISC architecture most of
the succeeding instructions are a) Computer Instruction Set
the complex instructions are
executed completely, then the Compliment
stored in _____
processor is said to have b) Complete Instruction Set
a) Register
______ Compliment
b) Diodes
a) Exception handling c) Computer Indexed Set
c) CMOS
b) Imprecise exceptions Components
d) Transistors
c) Error correction d) Complex Instruction set
d) None of the mentioned computer
10. Which of the architecture is
power efficient?
5. In super-scalar mode, all the 2. The computer architecture
a) CISC
similar instructions are grouped aimed at reducing the time of
b) RISC
and executed together. execution of instructions is
c) ISA
a) True ________
d) IANA
b) False a) CISC
b) RISC
6. In super-scalar processors, c) ISA
DONE BY PREZO MERLIN
________ mode of execution is d) ANNA
used. COMPILLED BY PROF: HASSAN
a) In-order 3. The Sun micro systems
processors usually follow _____ JALLOH
b) Post order
c) Out of order architecture.
d) None of the mentioned a) CISC
b) ISA
7. Since it uses the out of order c) ULTRA SPARC
mode of execution, the results d) RISC
are stored in ______
a) Buffers
b) Special memory locations 4. The RISC processor has a
c) Temporary registers more complicated design than