UNIT-2(part-1)

24CSEN2021:COMPUTER ORGANIZATION AND

ARCHITECTURE

Prof Srinivas Prasad, FIE, FIETE

BE (SGBAU), MS (BITS), MTECH (IIT-ISM), PhD (UU)

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 Text/Reference Books
TextBooks:
1. C. Hamacher, Z. Vranesic and S. Zaky,
"Computer Organization", 5th edition,
McGrawHill, 2017
2. W. Stallings, "Computer Organization and
Architecture -Designing for Performance",
11th edition, Prentice Hall of India,2022
References:
1. D. A. Patterson and J. L. Hennessy, "Computer
Organization and Design The Hardware/Software
Interface", 1998
2. J .P. Hayes, "Computer Architecture and
Organization", 1998
3.,https://onlinecourses.nptel.ac.in/noc21_cs61/
preview

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CONTROL UNIT DESIGN

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 Overview
● Instruction Set Processor (ISP)
● Central Processing Unit (CPU)
● A typical computing task consists of a
series of steps specified by a sequence of
machine instructions that constitute a
program.
● An instruction is executed by carrying out
a sequence of more rudimentary
operations.
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Some Fundamental Concepts

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 Fundamental Concepts
● Processor fetches one instruction at a time and
perform the operation specified.
● Instructions are fetched from successive
memory locations until a branch or a jump
instruction is encountered.
● Processor keeps track of the address of the
memory location containing the next instruction
to be fetched using Program Counter (PC).
● Instruction Register (IR)

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 Executing an Instruction
● Fetch the contents of the memory location
pointed to by the PC. The contents of this
location are loaded into the IR (fetch phase).
IR ← [[PC]]
● Assuming that the memory is byte addressable,
increment the contents of the PC by 4 (fetch
phase).
PC ← [PC] + 4
● Carry out the actions specified by the
instruction in the IR (execution phase).
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 Processor Organization
Internal processor
bus
Control signals

PC

Instruction
Address
decoder and
lines
MDR HAS MAR control logic
TWO Memory
INPUTS AND bus
TWO MDR
OUTPUTS Data
lines IR

Y
Datapath
Constant 4 R0

Select MUX

Add
A B
ALU Sub R n - 1 
control ALU
lines
Carry-in
XOR TEMP

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Figure 7.1. Single-bus organization of the datapath inside a processor.
 Executing an Instruction
● Transfer a word of data from one
processor register to another or to the
ALU.
● Perform an arithmetic or a logic operation
and store the result in a processor
register.
● Fetch the contents of a given memory
location and load them into a processor
register.
● Store a word of data from a processor
register into a given memory location. 9
Register Transfers Internal processor
bus
Riin

Ri

Riout

Y in

Constant 4

Select MUX

A B
ALU

Z in

Z out

FInput and output gating for the registers . 10

 Register Transfers
● All operations and data transfers are controlled by the processor
clock.
Bus

D Q
1
Q
Riout

Ri in
Clock

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Figure 7.3.
InputInput and output
and output gating ating
g onefor
for one re
register gbit.
ister bit.
 Performing an Arithmetic or
Logic Operation
● The ALU is a combinational circuit that has no
internal storage.
● ALU gets the two operands from MUX and bus.
The result is temporarily stored in register Z.
● What is the sequence of operations to add the
contents of register R1 to those of R2 and
store the result in R3?
1. R1out, Yin
2. R2out, SelectY, Add, Zin
3. Zout, R3in
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 Fetching a Word from Memory
● Address into MAR; issue Read operation; data into MDR.
Memory-bus Internal processor
data lines MDRoutE MDRout bus

MDR

MDR inE MDRin

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Figure 7.4. Connection
Connection and signals
and control controlfor
signals
registerfor
gister
re MDR.
MDR.
Fetching a Word from Memory
● The response time of each memory access
varies (cache miss, memory-mapped I/O,…).
● To accommodate this, the processor waits until
it receives an indication that the requested
operation has been completed (Memory-
Function-Completed, MFC).
● Move (R1), R2
 MAR ← [R1]
 Start a Read operation on the memory bus
 Wait for the MFC response from the memory
 Load MDR from the memory bus
 R2 ← [MDR]
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 Execution of a Complete
Instruction
● Add (R3), R1
● Fetch the instruction
● Fetch the first operand (the contents of
the memory location pointed to by R3)
● Perform the addition
● Load the result into R1

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 Architecture
Internal processor
bus
Riin

Ri

Riout

Y in

Constant 4

Select MUX

A B
ALU

Z in

Z out

Input and output gating for the registers in Figure . 16

 Execution of a Complete
Instruction Internal processor
bus

Add (R3), R1 PC
Control signals

Instruction
Step Action Address
decoder and
lines
MAR control logic

1 PCout , MAR in , Read, Select4,Add, Zin Memory

bus

2 Zout , PCin , Yin , WMF C MDR

Data
lines IR
3 MDR out , IR in
4 R3out , MAR in , Read Y
Constant 4 R0
5 R1out , Y in , WMF C
6 MDR out , SelectY, Add, Zin Select MUX

7 Zout , R1in , End Add

A B
ALU Sub R n - 1
control ALU
lines
Carry-in
XOR TEMP
Figure 7.6. Control sequencefor execution of the instruction Add (R3),R1.
Z

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Figure 7.1. Single-bus organization of the datapath inside a processor.
 Execution of Branch
Instructions
● A branch instruction replaces the contents
of PC with the branch target address,
which is usually obtained by adding an
offset X given in the branch instruction.
● The offset X is usually the difference
between the branch target address and
the address immediately following the
branch instruction.
● Conditional branch
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 Execution of Branch
Instructions
Step Action

1 PC out , MAR in , Read, Select4, Add, Z in

2 Z out , PC in , Y in , WMF C
3 MDR out , IR in
4 Offset-field-of-IR out, Add, Z in
5 Z out, PC in , End

Control sequence for an unconditional branch instruction.

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Multiple-Bus Organization
Bus A Bus B Bus C

Incrementer

PC

Re gister
file

Constant 4

MUX
A

ALU R

Instruction
decoder

IR

MDR

MAR

Memory b us Address
data lines lines
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Figure 7.8. Three-b us or g anization of the datapath.
 Multiple-Bus Organization
● Add R4, R5, R6

StepAction

1 PCout, R=B, MARin , Read,IncPC

2 WMFC
3 MDRoutB , R=B, IR in
4 R4outA , R5outB , SelectA,Add,R6in , End

Control sequence for the instruction. Add R4,R5,R6,

for the three-bus organization 21
 Quiz
Internal processor
bus
Control signals

● What is the control PC

sequence for Address

lines
Instruction
decoder and

execution of the
MAR control logic

Memory
bus

instruction Data
lines
MDR
IR

Add R1, R2 Constant 4

Y
R0

including the Select MUX

instruction fetch ALU

Add
Sub
A B
R n - 1

phase? (Assume
control ALU
lines
Carry-in

single bus
XOR TEMP

architecture)
Figure 7.1. Single-bus organization of the datapath inside a processor. 22
23
Hardwired Control

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 Overview
● To execute instructions, the processor
must have some means of generating the
control signals needed in the proper
sequence.
● Two categories: hardwired control and
microprogrammed control
● Hardwired system can operate at high
speed; but with little flexibility.

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Control Unit Organization
CLK Control step
Clock counter

External
inputs
Decoder/
IR
encoder
Condition
codes

Control signals

Control unit organization.

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 Detailed Block Description
CLK
Clock Control step Reset
counter

Step decoder

T 1 T2 Tn

INS1
External
INS2 inputs
Instruction
IR Encoder
decoder
Condition
codes
INSm

Run End

Control signals

Figure 7.11. Separation of the decoding and encoding functions. 27

 Generating Zin
● Zin = T1 + T6 • ADD + T4 • BR + …
Branch Add

T4 T6

T1

Generation of the Zin control signal for the processor in Figure 7.1.
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 Generating End
● End = T7 • ADD + T5 • BR + (T5 • N + T4 • N) • BRN +…
Branch<0
Add Branch
N N

T7 T5 T4 T5

End

Figure 7.13. Generation of the End control signal.

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A Complete Processor

Instruction Integer Floating-point

unit unit unit

Instruction Data
cache cache

Bus interface
Processor

System bus

Main Input/
memory Output

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Figure 7.14. Block diagram of a complete processor
.
Microprogrammed Control

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 Overview
● Control signals are generated by a program similar to machine
language programs.
● Control Word (CW); microroutine; microinstruction

MDRout

WMFC
MAR in

Select
Read
PCout

R1out

R3out
Micro -

End
PCin

R1in
Add

Z out
IRin

Yin
instruction

Zin
1 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0
2 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0
3 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
4 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0
5 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0
6 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1

Figure 7.15 An e xample of microinstructions for Figure 7.6.

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 Overview

Step Action

1 PCout , MAR in , Read, Select4,Add, Zin

2 Zout , PCin , Yin , WMF C
3 MDR out , IR in
4 R3out , MAR in , Read
5 R1out , Y in , WMF C
6 MDR out , SelectY, Add, Zin
7 Zout , R1in , End

Figure 7.6. Control sequencefor execution of the instruction Add (R3),R1.

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 Overview
● Control store
Starting
IR address
One function
generator cannot be carried
out by this simple
organization.

Clock PC

Control
store CW

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Figure 7.16. Basic organization of a microprogrammed control unit.
 Overview
● The previous organization cannot handle the situation when the
control unit is required to check the status of the condition codes or
external inputs to choose between alternative courses of action.
● Use conditional branch microinstruction.
Address Microinstruction

0 PC out , MAR in , Read, Select4, Add, Z in

1 Z out , PC in , Y in , WMF C
2 MDR out , IR in
3 Branch to starting address of appropriate microroutine
. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ... ..
25 If N=0, then branch to microinstruction 0
26 Offset-field-of-IR out , SelectY, Add, Z in
27 Z out , PC in , End

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Figure 7.17. Microroutine for the instruction Branch<0.
 Overview
External
inputs
Starting and
branch address Condition
IR codes
generator

Clock PC

Control
store CW

Figure 7.18. Organization of the control unit to allow 36

conditional branching in the microprogram.

 Microinstructions
● A straightforward way to structure
microinstructions is to assign one bit
position to each control signal.
● However, this is very inefficient.
● The length can be reduced: most signals
are not needed simultaneously, and many
signals are mutually exclusive.
● All mutually exclusive signals are placed in
the same group in binary coding.
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 Further Improvement
● Enumerate the patterns of required
signals in all possible microinstructions.
Each meaningful combination of active
control signals can then be assigned a
distinct code.
● Vertical organization
● Horizontal organization

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 Microprogram Sequencing
● If all microprograms require only straightforward sequential execution of
microinstructions except for branches, letting a μPC governs the sequencing
would be efficient.
● However, two disadvantages:
 Having a separate microroutine for each machine instruction results in a
large total number of microinstructions and a large control store.
 Longer execution time because it takes more time to carry out the required
branches.
● Example: Add src, Rdst
● Four addressing modes: register, autoincrement, autodecrement, and
indexed (with indirect forms).

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 Hardwired vs
Micro-programmed Control
● Hardwired implementation of the CU
– synthesizing a sequential circuit to obtain the desidered
input-output relations for control signals
● Micro-programmed implementation of the CU
– use sequences of micro-instructions to implement the
execution of CPU micro-operations
● Called micro-programming or firmware production, since
each sequence is made up by a small number of very simple
operations

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 Hardwired vs Micro-programmed

● Micro-programmed control simplifies the design of

control unit
– Cheaper
– Less error-prone
– Much more easier to revise and modify
● But the control unit is faster with hardwired CU
● Micro-programmed CU is used mainly for CISC
architectures since flexibility of CU is more important
for a complex instruction set
● On the other side, RISC architectures use hardwired
CU since with a Rev.
simpler
(2008-09) by instruction
Luciano Gualà set flexibility
41 is a

less important requirement than speed of execution

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 References
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Computer
Organization,5/e, McGraw Hill,2001
References:
!. M. Morris Mano, Computer System Architecture, 3/e,
Pearson education, 2008
2. John P. Hayes, Computer Architecture and Organization,
3/e, McGraw Hill, 1998.
3. William Stallings, Computer Organization and
Architecture, 6/e, Pearson PHI, 2012.

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