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MAX32655 Low-Power, Arm Cortex-M4 Processor with

FPU-Based Microcontroller and Bluetooth 5.2

General Description Benefits and Features

The MAX32655 microcontroller (MCU) is an advanced ● Ultra-Low-Power Wireless Microcontroller
system-on-chip (SoC) featuring an Arm® Cortex®-M4F • Internal 100MHz Oscillator
CPU for efficient computation of complex functions and • Flexible Low-Power Modes with 7.3728MHz
algorithms that is qualified to operate at a temperature System Clock Option
range of -40°C to +105°C. The SoC integrates power reg- • 512KB Flash and 128KB SRAM
ulation and management with a single inductor multiple- • Optional ECC on One 32KB SRAM Bank
output (SIMO) buck regulator system. The latest genera- • 16KB Instruction Cache
tion Bluetooth® 5.2 Low Energy (LE) radio is on board, ● Bluetooth 5.2 LE Radio
supporting long-range (coded) and high-throughput • Dedicated, Ultra-Low-Power, 32-Bit RISC-V
modes and medical body area network (MBAN). Coprocessor to Offload Timing-Critical Bluetooth
The device offers large onboard memory with 512KB flash Processing
and 128KB SRAM, with optional error correction coding • Fully Open-Source Bluetooth 5.2 Stack Available
(ECC) on one 32KB SRAM bank. This 32KB bank can be • Supports Medical Body Area Network (MBAN)
optionally retained in BACKUP mode. An 8KB user OTP • High-Throughput (2Mbps) Mode
area is available. • Long-Range (125kbps and 500kbps) Modes
The MAX32655 supports multiple high-speed peripherals, • Rx Sensitivity: -97dBm; Tx Power: +5.5dBm
such as I2C, 50MHz SPI, and UART, plus one I2S port • Single-Ended Antenna Connection (50Ω)
for connecting to an audio codec. An eight-input, 10-bit ● Power Management Maximizes Battery Life
ADC is available to monitor analog input from external • 2.0V to 3.6V Supply Voltage Range
analog sources. In addition, a low-power UART (LPUART) • Integrated SIMO Power Regulator
is available for operation in the lowest power sleep modes • 12.9μA/MHz Active Current at 3.0V
to facilitate wake-up activity without any data loss. A total • 1.53μA at 3.0V Retention Current for 32KB
of six timers with I/O capability are provided, including two • Selectable SRAM Retention + RTC in Low-Power
low-power timers to enable pulse counting, capture/com- Modes
pare, and pulse-width modulation (PWM) generation, even ● Multiple Peripherals for System Control
in the lowest power sleep modes. • Up to Two High-Speed SPI Controller/Target
The MAX32655 is available in two different packages: • Up to Three I2C Controller/Target
● 81 CTBGA (8mm x 8mm, 0.8mm pitch) • Up to Four UARTs
● 51 WLP (3.09mm x 3.09mm, 0.35mm pitch) • Up to One I2S Controller/Target
• Up to 8-Input, 10-Bit Sigma-Delta ADC 7.8ksps
• Up to Four Micro-Power Comparators
Applications • Timers: Four 32-Bit, Two Low Power, One
● Asset Tracking Watchdog, One Low-Power Watchdog
● Fitness/Health and Medical Wearables • 1-Wire® Controller
● Hearables • Up to Four Pulse Train (PWM) Engines
● Industrial Sensors • RTC with Wake-Up Timer
● Wireless Computer Peripherals and I/O Devices • Up to 52 GPIOs
● Security and Integrity
• Optional Secure Boot
• TRNG Seed Generator
• AES 128/192/256 Hardware Acceleration Engine

1-Wire is a registered trademark of Maxim Integrated Products, Inc.

Arm, Cordio, and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
Bluetooth is a trademark of Bluetooth SIG, Inc.

Ordering Information appears at end of data sheet. 19-100883; Rev 4; 1/24

© 2024 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

One Analog Way, Wilmington, MA 01887 U.S.A. | Tel: 781.329.4700 | © 2024 Analog Devices, Inc. All rights reserved.
MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

Simplified Block Diagram

100MHz (IPO)
MAX32655

EXTERNAL CLOCK
HFXOUT Bluetooth 5.2
32MHz (ERFO) 32-BIT RISC-V (RV32) ANT
HFXIN RADIO TRANSCEIVER
Arm Cortex-M4
8kHz (INRO) WITH FPU
100MHz (CM4)
32.768kHz (ERTCO)
7.3728MHz (IBRO) NVIC SERIAL WIRE DEBUG

60MHz (ISO)
*I2S

TX/RX
FIFO
32KIN CONTROLLER/TARGET
RTC WITH WAKE-UP SHARED PAD
32KOUT TIMER FUNCTIONS
*3 x I2C

TX/RX
FIFO
CONTROLLER/TARGET TIMERS/PWM
POWER-ON RESET, MEMORY
BROWNOUT MONITOR, CAPTURE/
RSTN COMPARE

TX/RX
SUPPLY VOLTAGE

FIFO
*3 × 4-WIRE UART
MONITORS FLASH 512KB
LOW-POWER
TIMERS
TX/RX
VREGI SRAM0 32KB + ECC
FIFO
*2-WIRE LPUART
MULTILAYER BUS MATRIX – AHB/APB

VSSPWR GPIO/
SERIAL WIRE
BLE_LDO_IN ALTERNATE
SRAM1 32KB *2 x QUAD SPI DEBUG
FUNCTION
TX/RX
FIFO

VSS CONTROLLER/TARGET UP TO 52
LXA (3 CS EACH) SPI
SRAM2 48KB
I 2C
LXB UART
VBST SRAM3 16KB 1-Wire CONTROLLER (OWM)
VREGO_A LOW-POWER
SIMO VOLTAGE
VREGO_B CACHE 16KB *4 × PULSE TRAIN ENGINES UART
REGULATION,
VREGO_C AND
1-Wire
POWER CONTROL BOOT ROM *4 × 32-BIT TIMERS
VREGO_D
WAKE-UP TIMER
VDDA 8-CH, Σ-Δ ADC
VSSA *2 × 32-BIT LOW-POWER MICROPOWER
4-CH DMA TIMERS COMPARATORS
VSS_TX
VSS_RX VREGI
2 × WATCHDOG VTXOUT BLUETOOTH
VSS TIMER ANTENNA
OPTIONAL 8 VRXOUT
VTXOUT VCOREA CONTROL
EXTERNAL
VRXOUT UNIQUE ID VCOREB
CHANNEL
VDDIO VDDIOH EXTERNAL
10-BIT VDDIO
VDDIOH INTERRUPTS
SECURITY Σ-Δ ADC VDDA
VCOREA
VCOREB AES-128/192/256
8
RADIO I/O I/O DIGITAL/ OPTIONAL 4 MICROPOWER 8
32-BIT CRC
MEMORIES COMPARATORS
ACCELERATOR
ANALOG SECURE NV KEY *NOT ALL PACKAGES
4 PROVIDE THE FULL
SECURE BOOT
COMPLEMENT OF THIS
TRUE RANDOM NUMBER 4 PERIPHERAL. SEE
GENERATOR (TRNG)
ORDERING INFORMATION
TABLE FOR DETAILS.

www.analog.com Analog Devices | 2

MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
81 CTBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
51 WLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical Characteristics—SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Electrical Characteristics—I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Electrical Characteristics—I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Electrical Characteristics—1-Wire Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
81 CTBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Pin Descriptions – 81 CTBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
51 WLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Pin Descriptions – 51 WLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Arm Cortex-M4 (CM4) with FPU Processor and RISC-V (RV32) Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Internal Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Internal SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Bluetooth 5.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Bluetooth 5.2 Low Energy Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Bluetooth 5.2 Software Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
General-Purpose I/O (GPIO) and Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Single-Inductor Multiple-Output (SIMO) Switch-Mode Power Supply (SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
ACTIVE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
SLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
LOW POWER Mode (LPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
MICRO POWER Mode (UPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
STANDBY Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

www.analog.com Analog Devices | 3

MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

TABLE OF CONTENTS (CONTINUED)

BACKUP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
POWER DOWN Mode (PDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Wake-up Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Real-Time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Programmable Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
32-Bit Timer/Counter/PWM (TMR, LPTMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Pulse Train Engine (PT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Serial Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
I2C Interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
I2S Interface (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
UART (UART, LPUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
1-Wire Controller (OWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Standard DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
AES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
True Random Number Generator (TRNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
CRC Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Secure Communications Protocol Bootloader (SCPBL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Secure Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Debug and Development Interface (SWD, JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Bypass Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
RTC Crystal Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Device PCB Power Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
VREGI Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Transmitted Spurious Emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Typical Fixed Current Consumption Temperature Variance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
ACTIVE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
SLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
STANDBY Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
BACKUP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

LIST OF FIGURES
Figure 1. Example 81 CTBGA Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. Example 51 WLP Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. SPI Controller Mode Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 4. SPI Target Mode Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 5. I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 6. I2S Target Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 7. 1-Wire Controller Data Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 8. 81 CTBGA Clocking Scheme Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 9. 51 WLP Clocking Scheme Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
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LIST OF TABLES
Table 1. MAX32655 Comparator Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 2. MAX32655 ADC External Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 3. BACKUP Mode SRAM Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 4. MAX32655 Wake-up Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 5. MAX32655 Timer Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 6. MAX32655 Watchdog Timer Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 7. MAX32655 Pulse Train Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 8. MAX32655 I2C Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 9. MAX32655 SPI Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 10. MAX32655 UART Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 11. Common CRC Polynomials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 12. Device PCB Power Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 13. MAX32655 VREGI Capacitor Placement Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 14. Fixed VREGI Current Consumption ACTIVE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 15. Fixed VREGI Current Consumption SLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 16. Fixed VREGI Current Consumption STANDBY Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 17. Fixed VREGI Current Consumption BACKUP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
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Absolute Maximum Ratings

VCOREA, VCOREB ............................................... -0.3V to +1.21V VSSA ..................................................................................100mA
VDDIO .................................................................. -0.3V to +1.89V VSS, VSS_TX, VSS_RX .......................................................100mA
VDDIOH .................................................................. -0.3V to +3.6V VSSPWR .............................................................................100mA
VREGI .................................................................... -0.3V to +3.6V Continuous Package Power Dissipation CTBGA (multilayer
VDDA ................................................................... -0.3V to +1.89V board) TA = +70°C (derate 24.10mW/°C above
BLE_LDO_IN ......................................................... -0.3V to +1.5V +70°C) ........................................................................1928.18mW
RSTN, GPIO (VDDIOH) (Note 1) ..............-0.3V to VDDIOH + 0.5V Continuous Package Power Dissipation 51 WLP (multilayer
GPIO (VDDIO) (Note 2) .............................. -0.3V to VDDIO + 0.5V board) TA = +70°C (derate 20.75mW/°C above
32KIN, 32KOUT (Note 2) ........................... -0.3V to VDDA + 0.2V +70°C) ..........................................................................1660.1mW
Output Current (sink) by Any GPIO Pin ............................... 25mA Operating Temperature Range ...........................-40°C to +105°C
Output Current (source) by Any GPIO Pin ......................... -25mA Storage Temperature Range ..............................-65°C to +125°C
VDDIO Combined Pins (sink) (Note 3) ................................. 50mA Soldering Temperature ..................................................... +260°C
VDDIOH Combined Pins (sink) ........................................... 100mA
Note 1: These device pins cannot exceed 3.63V. All voltages with respect to VSS, unless otherwise noted.
Note 2: These device pins cannot exceed 1.89V. All voltages with respect to VSS, unless otherwise noted.
Note 3: This maximum current is limited by the VREGO_A regulator output. See Device PCB Power Connectivity.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

Package Information
81 CTBGA
Package Code X8188+4C
Outline Number 21-0735
Land Pattern Number 90-0460
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA) 41.49°C/W
Junction to Case (θJC) 10.81°C/W

TOP VIEW

LOGO [X]

ROOT PART NUMBER MAX32655

DATE CODE AND DIE REVISION YYWW[[

ASSEMBLY LOT NUMBER ###&&

PIN A1 DESIGNATOR +

Figure 1. Example 81 CTBGA Top Marking

For the latest package outline information and land patterns (footprints), go to the Package Index on the Analog Devices
website. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a
different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a
four-layer board. For detailed information on package thermal considerations, refer to Thermal Characterization of IC
Packages.

51 WLP
Package Code W513A3+1
Outline Number 21-100711
Land Pattern Number Refer to Application Note 1891
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA) 20.75°C/W
Junction to Case (θJC) N/A

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

TOP VIEW

PIN A1 DESIGNATOR +

ROOT PART NUMBER MAX32655J

DATE CODE AND DIE REVISION YYWW[[

ASSEMBLY LOT NUMBER ###&&

Figure 2. Example 51 WLP Top Marking

For the latest package outline information and land patterns (footprints), go to the Package Index on the Analog Devices
website. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a
different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a
four-layer board. For detailed information on package thermal considerations, refer to Thermal Characterization of IC
Packages.

Electrical Characteristics
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLIES
Core Input Supply
VCOREA 0.99 1.1 1.21 V
Voltage A
Core Input Supply
VCOREB 0.81 1.1 1.21 V
Voltage B
If power to the device is cycled, VREGI
must exceed VREGI_POR(MIN) within
Input Supply Voltage, VREGI 2.0 3.0 3.6
20ms after VDDA > 1.24V. After that, V
Battery VREGI can settle to its final value.
VREGI_POR 2.45
Input Supply Voltage,
VDDA 1.71 1.8 1.89 V
Analog
Input Supply Voltage,
VDDIO 1.71 1.8 1.89 V
GPIO
Input Supply Voltage,
VDDIOH 2.0 3.0 3.6 V
GPIO (High)

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

Electrical Characteristics (continued)

(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Monitors VCOREA 0.84
Monitors VCOREB 0.69 0.73
Monitors VDDA 1.58 1.64 1.69
Power-Fail Reset Monitors VDDIO 1.58 1.64 1.69
VRST V
Voltage Monitors VDDIOH 1.58 1.64 1.69
Monitors VREGI 1.91 1.98 2.08
Monitors VRXOUT 0.773
Monitors VTXOUT 0.773
Monitors VCOREA 0.57
Power-on Reset Voltage VPOR V
Monitors VDDA 1.25

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
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Electrical Characteristics (continued)

(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Dynamic, IPO enabled, ISO disabled,
fSYS_CLK(MAX) = 100MHz, total current
into VREGI pin, VREGI = 3.0V, VCOREA =
1.0V, VCOREB = 0.81V, CM4 in ACTIVE
18.9
mode executing Coremark®, RV32 in
SLEEP mode, ECC disabled; inputs tied
to VSS, VDDIO, or VDDIOH; outputs
source/sink 0mA
Dynamic, IPO enabled, ISO disabled,
fSYS_CLK(MAX) = 100MHz, total current
into VREGI pin, VREGI = 3.0V, VCOREA =
1.0V, VCOREB = 0.81V, CM4 and RV32
in ACTIVE mode executing While(1), 19.0
ECC disabled; inputs tied to VSS, VDDIO,
or VDDIOH; outputs source/sink 0mA.
IREGI_DACT This specification is a function of the IPO μA/MHz
frequency.
Dynamic, IPO enabled, ISO disabled,
fSYS_CLK(MAX) = 100MHz, total current
into VREGI pin, VREGI = 3.0V, VCOREA =
1.0V, VCOREB = 0.81V, CM4 in ACTIVE
12.9
mode executing While(1), RV32 in
VREGI Current, ACTIVE SLEEP mode, ECC disabled; inputs tied
Mode to VSS, VDDIO, or VDDIOH; outputs
source/sink 0mA
Dynamic, total current into VREGI pin,
VREGI = 3.0V, VCOREA = 1.0V, VCOREB
= 0.81V, CM4 in SLEEP mode, RV32 in
18.3
ACTIVE mode running from ISO, ECC
disabled; inputs tied to VSS, VDDIO, or
VDDIOH; outputs source/sink 0mA
Fixed, IPO enabled, ISO disabled, total
current into VREGI, VREGI = 3.0V,
VCOREA = 1.0V, VCOREB = 0.81V, CM4
in ACTIVE mode 0MHz, RV32 in ACTIVE 582.1
mode 0MHz; inputs tied to VSS, VDDIO,
or VDDIOH; outputs source/sink 0mA. See
Temperature Variance.
IREGI_FACT μA
Fixed, IPO disabled, ISO enabled, total
current into VREGI, VREGI = 3.0V,
VCOREA = 1.0V, VCOREB = 0.81V, CM4
in ACTIVE mode 0MHz, RV32 in ACTIVE 446
mode 0MHz; inputs tied to VSS, VDDIO,
or VDDIOH; outputs source/sink 0mA. See
Temperature Variance.

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
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Electrical Characteristics (continued)

(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Dynamic, IPO enabled, ISO disabled,
fSYS_CLK(MAX) = 100MHz, ISO enabled,
total current into VREGI pins, VREGI =
3.0V, VCOREA = 1.0V, VCOREB = 0.81V,
IREGI_DSLP CM4 in SLEEP mode, RV32 in SLEEP 8.76 μA/MHz
mode, ECC disabled, standard DMA with
two channels active; inputs tied to VSS,
VREGI Current, SLEEP VDDIO, or VDDIOH; outputs source/sink
Mode 0mA
Fixed, IPO enabled, ISO disabled, total
current into VREGI pins, VREGI = 3.0V,
VCOREA = 1.0V, VCOREB = 0.81V, CM4
IREGI_FSLP in SLEEP mode, RV32 in SLEEP mode, 582.1 μA
ECC disabled; inputs tied to VSS, VDDIO,
or VDDIOH; outputs source/sink 0mA. See
Temperature Variance.
Dynamic, IPO disabled, ISO enabled,
total current into VREGI pins, VREGI =
3.0V, VCOREA = 1.0V, VCOREB = 0.81V,
IREGI_DLP CM4 powered off, RV32 in ACTIVE mode 18.30 μA/MHz
running While(1), fSYS_CLK(MAX) =
60MHz; inputs tied to VSS, VDDIO, or
VREGI Current, LOW VDDIOH; outputs source/sink 0mA
POWER Mode
Fixed, IPO disabled, ISO enabled, total
current into VREGI pins, VREGI = 3.0V,
VCOREA = 1.0V, VCOREB = 0.81V, CM4
IREGI_FLP 446 μA
powered off, RV32 in ACTIVE mode
0MHz; inputs tied to VSS, VDDIO, or
VDDIOH; outputs source/sink 0mA
Dynamic, ERTCO enabled, IBRO
enabled, total current into VREGI pins,
VREGI Current, MICRO VREGI = 3.0V, VCOREA = 1.0V, VCOREB
IREGI_DMP 230 μA
POWER Mode = 0.81V, LPUART active, fLPUART =
32.768kHz; inputs tied to VSS, VDDIO, or
VDDIOH; outputs source/sink 0mA
Fixed, total current into VREGI pins,
VREGI = 3.0V, VCOREA = 1.0V, VCOREB
VREGI Current,
IREGI_STBY = 0.81V; inputs tied to VSS, VDDIO, or 2.1 μA
STANDBY Mode
VDDIOH; outputs source/sink 0mA. See
Temperature Variance.

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
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Electrical Characteristics (continued)

(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Total current into
VREGI pins, VREGI
= 3.0V, VCOREA =
1.0V, VCOREB =
0.81V, RTC
All SRAM retained,
disabled; inputs 1.6
25°C
tied to VSS, VDDIO,
or VDDIOH; outputs
source/sink 0mA.
See Temperature
Variance.
Total current into
VREGI pins, VREGI
= 3.0V, VCOREA =
1.0V, VCOREB =
0.81V, RTC
VREGI Current, No SRAM
IREGI_BK disabled; inputs 0.98 μA
BACKUP Mode retention, 25°C
tied to VSS, VDDIO,
or VDDIOH, outputs
source/sink 0mA.
See Temperature
Variance.
Total current into SRAM0 retained,
1.14
VREGI pins, VREGI 25°C
= 3.0V, VCOREA = SRAM0 and
1.0V, VCOREB = SRAM1 retained, 1.29
0.81V, RTC 25°C
disabled; inputs
tied to VSS, VDDIO,
or VDDIOH; outputs SRAM0, SRAM1,
source/sink 0mA. and SRAM2 1.53
See Temperature retained
Variance.
Total current into VREGI pins, VREGI =
VREGI Current, POWER 3.0V, VCOREA = 1.0V, VCOREB = 0.81V;
IREGI_PDM 0.09 μA
DOWN Mode inputs tied to VSS, VDDIO, or VDDIOH;
outputs source/sink 0mA
VREGO_X Output VREGO_X_IOU Output current for each of the VREGO_X
5 50 mA
Current T outputs
VREGO_X Output VREGO_X_IOU
All four VREGO_X outputs combined 15 100 mA
Current Combined T_TOT
VREGI ≥ VREGO_X + 200mV; output
VREGO_X Output VREGO_X_RA voltage range must be configured to meet
VRST 1.0 VMAX V
Voltage Range NGE the input voltage range of the load device
pin (VRST to VMAX)
VREGI = 2.7V, VREGO_X = 1.1V,
VREGO_X Efficiency VREGO_X_EFF 90 %
load = 30mA
SLEEP Mode Resume Time from power mode exit to execution
tSLP_ON 0.847 μs
Time of first user instruction
LOW POWER Mode Time from power mode exit to execution
tLP_ON 6.08 μs
Resume Time of first user instruction

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
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Electrical Characteristics (continued)

(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MICRO POWER Mode Time from power mode exit to execution
tMP_ON 12.4 μs
Resume Time of first user instruction
STANDBY Mode Time from power mode exit to execution
tSTBY_ON 14.7 μs
Resume Time of first user instruction
BACKUP Mode Resume Time from power mode exit to execution
tBKU_ON 1.15 ms
Time of first user instruction
POWER DOWN Mode Time from power mode exit to execution
tPDM_ON 5 ms
Resume Time of first user instruction
CLOCKS
System Clock
fSYS_CLK 100,000 kHz
Frequency
Internal Primary
fIPO 100 MHz
Oscillator (IPO)
Internal Secondary
fISO 60 MHz
Oscillator (ISO)
Internal Baud Rate
fIBRO 7.3728 MHz
Oscillator (IBRO)
8kHz selected 8
Internal Nano-Ring
fINRO 16kHz selected 16 kHz
Oscillator (INRO)
30kHz selected 30
32kHz watch crystal. Required crystal
characteristics: CL_XTAL = 6pF, ESR <
90kΩ, C0 ≤ 2pF, crystal power dissipation
External RTC Oscillator
fERTCO rating minimum 0.5μW, no external load 32.768 kHz
(ERTCO)
capacitors, see RTC Crystal Guidelines.
The accuracy is determined by the crystal
and PCB layout.
The oscillator accepts a crystal between
16MHz and 32MHz. Required crystal
characteristics: CL_XTAL = 12pF, ESR ≤
50Ω, C0 ≤ 7pF, crystal power dissipation
rating of 100μW (min). Refer to the
device user guide for calculating the load
External RF Oscillator
fERFO capacitors. The accuracy is determined 16–32 MHz
Frequency (ERFO)
by the crystal and PCB layout.

If the ERFO is used for Bluetooth LE

operation, the frequency must be 32MHz,
the temperature stability must be ±20ppm
and the initial tolerance must be ±20ppm.
RTC Operating Current IRTC All power modes, RTC enabled 0.3 μA
RTC Power-Up Time tRTC_ ON 250 ms
Input Low Voltage 0.3 ×
VIL_32K V
32KIN VDDA
Input High Voltage 0.7 ×
VIH_32K V
32KIN VDDA

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
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Electrical Characteristics (continued)

(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
EXT_CLK selected. Drive this input with a
square wave from 0V to VDDIOH with 80
External System Clock VDDIOH selected as the I/O supply.
fEXT_CLK MHz
Input Frequency EXT_CLK selected. Drive this input with a
square wave from 0V to VDDIO with 80
VDDIO selected as the I/O supply.
External Low-Power
fEXT_LPTMR1_
Timer 1 Clock Input LPTMR1_CLK selected 8 MHz
Frequency CLK

External Low-Power
fEXT_LPTMR2_
Timer 2 Clock Input LPTMR2_CLK selected 8 MHz
Frequency CLK

GENERAL-PURPOSE I/O
P3.0 and P3.1 can
Input Low Voltage for All only use VDDIOH
VDDIO selected as 0.3 ×
GPIO Except P3.0 and VIL_VDDIO as I/O supply and V
I/O supply VDDIO
P3.1 cannot use VDDIO
as I/O supply
Input Low Voltage for All 0.3 ×
VIL_VDDIOH VDDIOH selected as I/O supply V
GPIO VDDIOH
Input Low Voltage for 0.5 x
VIL_RSTN V
RSTN VDDIOH
P3.0 and P3.1 can
Input High Voltage for only use VDDIOH
VDDIO selected as 0.7 ×
All GPIO Except P3.0 VIH_VDDIO as I/O supply and V
I/O supply VDDIO
and P3.1 cannot use VDDIO
as I/O supply
Input High Voltage for 0.7 ×
VIH_VDDIOH VDDIOH selected as I/O supply V
All GPIO VDDIOH
Input High Voltage for 0.5 x
VIH_RSTN V
RSTN VDDIOH

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
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Electrical Characteristics (continued)

(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VDDIO selected as
I/O supply, VDDIO
= 1.71V, 0.2 0.4
GPIOn_DS_SEL[1:
0] = 00, IOL = 1mA
VDDIO selected as
I/O supply, VDDIO
= 1.71V, 0.2 0.4
P3.0 and P3.1 can GPIOn_DS_SEL[1:
Output Low Voltage for only use VDDIOH 0] = 01, IOL = 2mA
All GPIO Except P3.0 VOL_VDDIO as I/O supply and V
and P3.1 cannot use VDDIO VDDIO selected as
as I/O supply I/O supply, VDDIO
= 1.71V, 0.2 0.4
GPIOn_DS_SEL[1:
0] = 10, IOL = 4mA
VDDIO selected as
I/O supply, VDDIO
= 1.71V, 0.2 0.4
GPIOn_DS_SEL[1:
0] = 11, IOL = 8mA
VDDIOH selected as I/O supply, VDDIOH
= 1.71V, GPIOn_DS_SEL[1:0] = 00, IOL 0.2 0.4
= 1mA
VDDIOH selected as I/O supply, VDDIOH
= 1.71V, GPIOn_DS_SEL[1:0] = 01, IOL 0.2 0.4
Output Low Voltage for = 2mA
VOL_VDDIOH V
All GPIO VDDIOH selected as I/O supply, VDDIOH
= 1.71V, GPIOn_DS_SEL[1:0] = 10, IOL 0.2 0.4
= 4mA
VDDIOH selected as I/O supply, VDDIOH
= 1.71V, GPIOn_DS_SEL[1:0] = 11, IOL 0.2 0.4
= 8mA
Combined IOL, All GPIO IOL_TOTAL 48 mA

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

Electrical Characteristics (continued)

(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VDDIO selected as
I/O supply, VDDIO
VDDIO -
= 1.71V,
0.4
GPIOn_DS_SEL[1:
0] = 00, IOL = -1mA
VDDIO selected as
I/O supply, VDDIO
VDDIO -
= 1.71V,
P3.0 and P3.1 can 0.4
GPIOn_DS_SEL[1:
Output High Voltage for only use VDDIOH 0] = 01, IOL = -2mA
All GPIO Except P3.0 VOH_VDDIO as I/O supply and V
and P3.1 cannot use VDDIO VDDIO selected as
as I/O supply I/O supply, VDDIO
VDDIO -
= 1.71V,
0.4
GPIOn_DS_SEL[1:
0] = 10, IOL = -4mA
VDDIO selected as
I/O supply, VDDIO
VDDIO -
= 1.71V,
0.4
GPIOn_DS_SEL[1:
0] = 11, IOL = -8mA
VDDIOH selected as I/O supply, VDDIOH
VDDIOH
= 1.71V, GPIOn_DS_SEL[1:0] = 00, IOL
- 0.4
= -1mA
VDDIOH selected as I/O supply, VDDIOH
VDDIOH
= 1.71V, GPIOn_DS_SEL[1:0] = 01, IOL
Output High Voltage for - 0.4
= -2mA
All GPIO Except P3.0 VOH_VDDIOH V
and P3.1 VDDIOH selected as I/O supply, VDDIOH
VDDIOH
= 1.71V, GPIOn_DS_SEL[1:0] = 10, IOL
- 0.4
= -8mA
VDDIOH selected as I/O supply, VDDIOH
VDDIOH
= 1.71V, GPIOn_DS_SEL[1:0] = 11, IOL
- 0.4
= -8mA
Output High Voltage for VDDIOH = 1.71V, GPIOn_DS_SEL[1:0] VDDIOH
VOH_VDDIOH V
P3.0 and P3.1 fixed at 00, IOL = -1mA - 0.4
Combined IOH, All GPIO IOH_TOTAL -48 mA
Input Hysteresis
VIHYS 300 mV
(Schmitt)
VDDIO = 1.89V, VDDIOH = 3.6V, VDDIOH
Input Leakage Current
IIL selected as I/O supply, VIN = 0V, internal -100 +100 nA
Low
pull-up disabled
VDDIO = 1.89V, VDDIOH = 3.6V, VDDIOH
IIH selected as I/O supply, VIN = 3.6V, -800 +800 nA
internal pull-down disabled
Input Leakage Current
VDDIO = 0V, VDDIOH = 0V, VDDIO
High IOFF -1 +1
selected as I/O supply, VIN < 1.89V
μA
VDDIO = VDDIOH = 1.71V, VDDIO
IIH3V -2 +2
selected as I/O supply, VIN = 3.6V
Input Pull-up Resistor
RPU_R Pull-up to VDDIOH 25 kΩ
RSTN

www.analog.com Analog Devices | 17

MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

Electrical Characteristics (continued)

(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Pull-up/Pull-down RPU1 Strong Pull-up 25 kΩ
Resistor for All GPIO RPU2 Weak Pull-up 1 MΩ
Device in ACTIVE mode, RSTN device
RSTN Assertion Time tRSTN pin assertion duration to entry into device 6 μs
reset state
BLUETOOTH RADIO / POWER
Bluetooth LDO Input
VBLE_LDO_IN 0.9 1.1 1.5 V
Voltage
BLUETOOTH RADIO / FREQUENCY
Operating Frequency 1MHz channel spacing 2360 2500 MHz
PLL Programming
PLLRES 1 MHz
Resolution
Frequency Deviation at
Δf1MHz ±170 kHz
1Mbps
Frequency Deviation at
ΔfBLE1MHz ±250 kHz
Bluetooth LE 1Mbps
Frequency Deviation at
Δf2MHz ±320 kHz
2Mbps
Frequency Deviation at
ΔfBLE2MHz ±500 kHz
Bluetooth LE 2Mbps
BLUETOOTH RADIO / CURRENT CONSUMPTION (SIMO enabled, VREGI = 3.3V. ISO enabled, fSYS_CLK = 60MHz, Bluetooth
LE stack running on RV32. Measured at the VREGI device pin, VREGO_B = 0.9V, VREGO_C = 1.0V, CM4 in SLEEP mode.)
ITX_+5.5DBM PRF = +5.5dBm 7.42
Tx Run Current ITX_0DBM PRF = 0dBm 4.78 mA
ITX_-10DBM PRF = -10dBm 3.80
Tx Startup Current ISTART_TX 2.25 mA
BLUETOOTH RADIO / CURRENT CONSUMPTION (SIMO enabled, VREGI = 3.3V. ISO Enabled, fSYS_CLK = 60MHz, BLE stack
running on RV32. Measured at the VREGI device pin, VREGO_B = 0.9V, VREGO_C = 1.0V, CM4 in SLEEP mode)
IRX_1M fRX = 1Mbps 4.41
Rx Run Current mA
IRX_2M fRX = 2Mbps 4.45
Rx Startup Current ISTART_RX 2.05 mA
BLUETOOTH RADIO / TRANSMITTER
Maximum Output Power PRF +5.5 dBm
RF Power Accuracy PRF_ACC ±1 dB
First Adjacent Channel
PRF1_1 1Mbps Bluetooth LE -30.5 dBc
Transmit Power ±2MHz
First Adjacent Channel
PRF2_1 1Mbps Bluetooth LE -40 dBc
Transmit Power ±4MHz
BLUETOOTH RADIO / RECEIVER
Maximum Received
Signal Strength at < PRX_MAX 0 dBm
0.1% PER

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

Electrical Characteristics (continued)

(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
1Mbps Bluetooth
-97
Receiver Sensitivity, Measured with LE
PSENS_IT dBm
Ideal Transmitter 37-byte payload 2Mbps Bluetooth
-94
LE
1Mbps Bluetooth
-95.5
Receiver Sensitivity, Measured with LE
PSENS_DT dBm
Dirty Transmitter 37-byte payload 2Mbps Bluetooth
-93
LE
125kbps Bluetooth
-105
Receiver Sensitivity, Measured with LE
PSENS_LR dBm
Long-Range Coded 37-byte payload 500kbps Bluetooth
-101
LE
C/I1MHz 1Mbps Bluetooth LE 6.7
C/I Cochannel dB
C/I2Mhz 2Mbps Bluetooth LE 7
C/I+1_1 +1MHz offset, 1Mbps Bluetooth LE -2.5
C/I-1_1 -1MHz offset, 1Mbps Bluetooth LE -2.6
C/I+2_1 +2MHz offset, 1Mbps Bluetooth LE -22
C/I-2_1 -2MHz offset, 1Mbps Bluetooth LE -24
Adjacent Interference dB
C/I+2_2 +2MHz offset, 2Mbps Bluetooth LE -2
C/I-2_2 -2MHz offset, 2Mbps Bluetooth LE -3
C/I+4_2 +4MHz offset, 2Mbps Bluetooth LE -32
C/I-4_2 -4MHz offset, 2Mbps Bluetooth LE -34
Adjacent Interference,
(3+n) MHz Offset [n = 0, C/I3+MHZ 1Mbps Bluetooth LE -34.5 dB
1, 2, . . .]
Adjacent Interference,
(6+2n) MHz Offset [n = C/I6+MHZ 2Mbps Bluetooth LE -34 dB
0, 1, 2, . . .]
Intermodulation
Performance, 1Mbps
PIMD_1MBPS 1Mbps Bluetooth LE -38 dBm
Bluetooth LE with 3MHz,
4MHz, 5MHz Offset
Intermodulation
Performance, 2Mbps
PIMD_2MBPS 2Mbps Bluetooth LE -38 dBm
Bluetooth LE with 6MHz,
8MHz, 10MHz Offset
Received Signal
Strength Indicator RSSIACC ±1.5 dB
Accuracy
Received Signal
-100 to
Strength Indicator RSSIRANGE dBm
-15
Range
ADC (SIGMA-DELTA)
Resolution 10 Bits
ADC Clock Rate fACLK 0.1 8 MHz

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

Electrical Characteristics (continued)

(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ADC Clock Period tACLK 1/fACLK μs
AIN[7:0],
ADC_DIVSEL = REF_SEL = 0,
VSSA +
[00], REF_SCALE = 0, VBG
0.05
ADC_CH_SEL = SCALE = 0
[7:0]
AIN[7:0],
ADC_DIVSEL = REF_SEL = 0,
VSSA +
[01], REF_SCALE = 0, 2 x VBG
0.05
ADC_CH_SEL = SCALE = 1
[7:0]
Input Voltage Range VAIN V
AIN[7:0], REF_SEL = 1,
ADC_DIVSEL = REF_SCALE = 0,
VSSA +
[10], SCALE = 1, VDDIOH
0.05
ADC_CH_SEL = VDDIOH selected
[7:0] as the I/O supply
AIN[7:0], REF_SEL = 1,
ADC_DIVSEL = REF_SCALE = 0,
VSSA +
[11], SCALE = 1, VDDIO VDDIO
0.05
ADC_CH_SEL = selected as the I/O
[7:0] supply
Input Impedance RAIN 30 kΩ
Analog Input Fixed capacitance to VSSA 1 pF
CAIN
Capacitance Dynamically switched capacitance 250 fF
Integral Nonlinearity INL Measured at +25°C ±2.5 LSb
Differential Nonlinearity DNL Measured at +25°C ±1 LSb
Offset Error VOS ±1 LSb
Measured at VREGI = 3.0V, ADC active,
ADC Active Current IADC reference buffer enabled, input buffer 156 µA
disabled
Any power-up of ADC clock or ADC bias
ADC Setup Time tADC_SU 10 µs
to CpuAdcStart
ADC Output Latency tADC 1067 tACLK
ADC Sample Rate fADC 7.8 ksps
ADC Input Leakage IADC_LEAK ADC inactive or channel not selected 10 nA
Full-Scale Voltage VFS ADC code = 0x3FF 1.2 V
Bandgap Temperature
VTEMPCO Box method 30 ppm
Coefficient
COMPARATORS
Input Offset Voltage VOFFSET ±1 mV
AINCOMPHYST[1:0] = 00 ±23
AINCOMPHYST[1:0] = 01 ±50
Input Hysteresis VHYST mV
AINCOMPHYST[1:0] = 10 ±0
AINCOMPHYST[1:0] = 11 ±10

www.analog.com Analog Devices | 20

MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

Electrical Characteristics (continued)

(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Common-mode range. VDDIOH selected VDDIOH
0.2
as the I/O supply. - 0.2V
Input Voltage Range VIN_CMP V
Common-mode range. VDDIO selected as VDDIO -
0.2
the I/O supply. 0.2V
FLASH MEMORY
tM_ERASE Mass erase 20
Flash Erase Time ms
tP_ERASE Page erase 20
Flash Programming
tPROG 42 μs
Time per Word
Flash Endurance 10 kcycles
Data Retention tRET TA = +105°C 10 years
Current Consumption
VREGI = 3.0V. Current required for flash
During Flash IPROG 4.6 mA
write/erase
Programming

Electrical Characteristics—SPI
(Timing specifications are guaranteed by design and not production tested. All specifications and characteristics apply across the entire
operating conditions range unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CONTROLLER MODE
fSYS_CLK = 100MHz, fMCK0(MAX) =
fSYS_CLK/2, Mode 0 and Mode 2 50
SPI Controller Operating operation, SPI0_CTRL.sclk_fb_inv = 1
fMCK0 MHz
Frequency for SPI0 fSYS_CLK = 100MHz, fMCK0(MAX) =
fSYS_CLK/4, Mode 1 and Mode 3 25
operation
SPI Controller Operating fSYS_CLK = 100MHz, fMCK1(MAX) =
fMCK1 25 MHz
Frequency for SPI1 fSYS_CLK/4, all SPI modes of operation
SPI Controller SCK
tMCKX 1/fMCKX ns
Period
SCK Output Pulse-
tMCH, tMCL tMCKX/2 ns
Width High/Low
MOSI Output Hold Time
tMOH tMCX/2 ns
After SCK Sample Edge
MOSI Output Valid to
tMOV tMCKX/2 ns
Sample Edge
MOSI Output Hold Time
tMLH tMCKX/2 ns
After SCK Low Idle
MISO Input Valid to
SCK Sample Edge tMIS 5 ns
Setup
MISO Input to SCK
tMIH tMCKX/2 ns
Sample Edge Hold

www.analog.com Analog Devices | 21

MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

Electrical Characteristics—SPI (continued)

(Timing specifications are guaranteed by design and not production tested. All specifications and characteristics apply across the entire
operating conditions range unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TARGET MODE
SPI Target Operating
fSCK 50 MHz
Frequency
SPI Target SCK Period tSCK 1/fSCK ns
SCK Input Pulse-Width
tSCH, tSCL tSCK/2
High/Low
SSx Active to First Shift
tSSE 10 ns
Edge
MOSI Input to SCK
Sample Edge Rise/Fall tSIS 5 ns
Setup
MOSI Input from SCK
Sample Edge Transition tSIH 1 ns
Hold
MISO Output Valid After
SCLK Shift Edge tSOV 15 ns
Transition
SCK Inactive to SSx
tSSD 10 ns
Inactive
SSx Inactive Time tSSH 1/fSCK μs
MISO Hold Time After
tSLH 10 ns
SSx Deassertion

Electrical Characteristics—I2C
(Timing specifications are guaranteed by design and not production tested. All specifications and characteristics apply across the entire
operating conditions range unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STANDARD-MODE
Standard-mode, from VIH(MIN) to
Output Fall Time tOF 150 ns
VIL(MAX)
SCL Clock Frequency fSCL 0 100 kHz
Low Period SCL Clock tLOW 4.7 μs
High Time SCL Clock tHIGH 4.0 μs
Setup Time for
Repeated Start tSU;STA 4.7 μs
Condition
Hold Time for Repeated
tHD;STA 4.0 μs
Start Condition
Data Setup Time tSU;DAT 300 ns
Data Hold Time tHD;DAT 10 ns
Rise Time for SDA and
tR 800 ns
SCL

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

Electrical Characteristics—I2C (continued)

(Timing specifications are guaranteed by design and not production tested. All specifications and characteristics apply across the entire
operating conditions range unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Fall Time for SDA and
tF 200 ns
SCL
Setup Time for a Stop
tSU;STO 4.0 μs
Condition
Bus Free Time Between
a Stop and Start tBUS 4.7 μs
Condition
Data Valid Time tVD;DAT 3.45 μs
Data Valid Acknowledge
tVD;ACK 3.45 μs
Time
FAST-MODE
Output Fall Time tOF From VIH(MIN) to VIL(MAX) 150 ns
Pulse Width Suppressed
tSP 75 ns
by Input Filter
SCL Clock Frequency fSCL 0 400 kHz
Low Period SCL Clock tLOW 1.3 μs
High Time SCL Clock tHIGH 0.6 μs
Setup Time for
Repeated Start tSU;STA 0.6 μs
Condition
Hold Time for Repeated
tHD;STA 0.6 μs
Start Condition
Data Setup Time tSU;DAT 125 ns
Data Hold Time tHD;DAT 10 ns
Rise Time for SDA and
tR 30 ns
SCL
Fall Time for SDA and
tF 30 ns
SCL
Setup Time for a Stop
tSU;STO 0.6 μs
Condition
Bus Free Time Between
a Stop and Start tBUS 1.3 μs
Condition
Data Valid Time tVD;DAT 0.9 μs
Data Valid Acknowledge
tVD;ACK 0.9 μs
Time
FAST-MODE PLUS
Output Fall Time tOF From VIH(MIN) to VIL(MAX) 80 ns
Pulse Width Suppressed
tSP 75 ns
by Input Filter
SCL Clock Frequency fSCL 0 1000 kHz
Low Period SCL Clock tLOW 0.5 μs
High Time SCL Clock tHIGH 0.26 μs

www.analog.com Analog Devices | 23

MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

Electrical Characteristics—I2C (continued)

(Timing specifications are guaranteed by design and not production tested. All specifications and characteristics apply across the entire
operating conditions range unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Setup Time for
Repeated Start tSU;STA 0.26 μs
Condition
Hold Time for Repeated
tHD;STA 0.26 μs
Start Condition
Data Setup Time tSU;DAT 50 ns
Data Hold Time tHD;DAT 10 ns
Rise Time for SDA and
tR 50 ns
SCL
Fall Time for SDA and
tF 30 ns
SCL
Setup Time for a Stop
tSU;STO 0.26 μs
Condition
Bus Free Time Between
0.5
a Stop and Start tBUS μs
Condition
Data Valid Time tVD;DAT 0.45 μs
Data Valid Acknowledge
tVD;ACK 0.45 μs
Time

Electrical Characteristics—I2S
(Timing specifications are guaranteed by design and not production tested. All specifications and characteristics apply across the entire
operating conditions range unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Bit Clock Frequency fBCLK 25 MHz
0.5 x
BCLK High Time tWBCLKH ns
1/fBCLK
0.5 x
BCLK Low Time tWBCLKL ns
1/fBCLK
LRCLK Setup Time tLRCLK_BLCKS 25 ns
Delay Time, BCLK to
tBCLK_SDO 12 ns
SD (Output) Valid
Setup Time for SD
tSU_SDI 6 ns
(Input)
Hold Time SD (Input) tHD_SDI 3 ns

Electrical Characteristics—1-Wire Controller

(Timing specifications are guaranteed by design and not production tested. All specifications and characteristics apply across the entire
operating conditions range unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Standard 60
Write 0 Low Time tW0L μs
Overdrive 8

www.analog.com Analog Devices | 24

MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

Electrical Characteristics—1-Wire Controller (continued)

(Timing specifications are guaranteed by design and not production tested. All specifications and characteristics apply across the entire
operating conditions range unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Standard 6
Write 1 Low Time tW1L Standard, Long Line mode 8 μs
Overdrive 1
Standard 70
Presence Detect
tMSP Standard, Long Line mode 85 μs
Sample
Overdrive 9
Standard 15
Read Data Value tMSR Standard, Long Line mode 24 μs
Overdrive 3
Standard 10
Recovery Time tREC0 Standard, Long Line mode 20 μs
Overdrive 4
Standard 480
Reset Time High tRSTH μs
Overdrive 58
Standard 600
Reset Time Low tRSTL μs
Overdrive 70
Standard 70
Time Slot tSLOT μs
Overdrive 12

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

SHIFT SAMPLE SHIFT SAMPLE

SSx
(SHOWN ACTIVE LOW)
tMCK
SCK
CKPOL/CKPHA
0/1 OR 1/0
SCK tMCH tMCL
CKPOL/CKPHA
0/0 OR 1/1
tMOH
tMOV tMLH
MOSI/SDIOx
(OUTPUT) MSB MSB-1 LSB

tMIS tMIH
MISO/SDIOx
(INPUT) MSB MSB-1 LSB

Figure 3. SPI Controller Mode Timing Diagram

SHIFT SAMPLE SHIFT SAMPLE

SSx tSSE
tSSH
(SHOWN ACTIVE LOW)
tSSD
SCK tSCK
CKPOL/CKPHA
0/1 OR 1/0
tSCH tSCL
SCK
CKPOL/CKPHA
0/0 OR 1/1

tSIS tSIH
MOSI/SDIOx
(INPUT) MSB MSB-1 LSB

tSOV tSLH
MISO/SDIOx MSB MSB-1 LSB
(OUTPUT)

Figure 4. SPI Target Mode Timing Diagram

www.analog.com Analog Devices | 26

MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

START STOP START

START
REPEAT tBUS

SDA
tOF tR
tSU;STO
tSP
tSU;DAT tSU;STA tHIGH

SCL
tHD;STA
tHD;DAT
tLOW
tVD;ACK
tVD;DAT

Figure 5. I2C Timing Diagram

tBCLKS
tWBCLKHS tWBCLKLS

BCLK
(INPUT)

tLRCLK_BCLKS
LRCLK
(INPUT)

tBCLK_SDOS

SDO LSB MSB LSB MSB

(OUTPUT)
tHD_SDIS
tSU_SDIS
SDI
(INPUT) LSB MSB LSB MSB

WORD N-1 RIGHT CHANNEL WORD N LEFT CHANNEL WORD N RIGHT CHANNEL

CONDITIONS: I2S_CTRL0CH0.ws_pol = 0; I2S_CTRL0CH0.ch_mode = 3; I2S_CTRL0CH0.lsb_first = 0; I2S_CTRL0CH0.stereo = 0; I2S_CTRL1CH0.en = 1

Figure 6. I2S Target Timing Diagram

www.analog.com Analog Devices | 27

MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

INITALIZATION RESET AND PRESENCE PULSE

tRSTH

OWM_IO

tRSTL tPDH tPDL

WRITE TIME SLOTS

WRITE 0 SLOT WRITE 1 SLOT
tSLOT tSLOT

tLOW0 tREC tLOW1

OWM_IO

READ TIME SLOTS

READ 0 SLOT READ 1 SLOT
tSLOT tSLOT

tLOW1 tREC tLOW1

OWM_IO

tRDV tRDV

LEGEND
1-Wire BOTH CONTROLLER
CONTROLLER AND TARGET TARGET DEVICE RESISTOR
ACTIVE LOW DEVICE ACTIVE LOW ACTIVE LOW PULL-UP

Figure 7. 1-Wire Controller Data Timing Diagram

www.analog.com Analog Devices | 28

MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

Pin Configuration
81 CTBGA

TOP VIEW MAX32655

1 2 3 4 5 6 7 8 9

A ANT VSS_TX 32KOUT 32KIN VSSA VREGO_C VREGO_D LXB VSSPWR A

B VRXOUT VTXOUT BLE_LDO_IN VREGI VDDA VREGO_B VREGO_A VBST LXA B

C HFXIN HFXOUT VSS_RX P2.0 P2.1 P2.6 P2.4 VCOREB VREGI C

D VSS P1.8 P1.9 P1.7 P1.2 P2.7 P2.5 P2.2 VCOREA D

E P1.4 P1.6 P1.5 P1.3 P3.0 P3.1 P0.1 P2.3 VSS E

F P0.30 P1.1 P1.0 P0.31 P0.17 RSTN P0.0 P0.2 P0.3 F

G P0.28 P0.29 P0.23 P0.19 P0.16 P0.12 P0.6 P0.5 P0.4 G

H P0.26 P0.27 P0.22 P0.20 P0.18 P0.13 P0.10 P0.8 P0.7 H

J P0.25 P0.24 P0.21 VDDIOH VDDIO P0.15 P0.14 P0.11 P0.9 J

1 2 3 4 5 6 7 8 9

81 CTBGA
8mm x 8mm

www.analog.com Analog Devices | 29

MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

Pin Descriptions – 81 CTBGA

FUNCTION MODE
PIN NAME Primary Signal Alternate Alternate FUNCTION
(Default) Function 1 Function 2
POWER (See the Applications Information section for bypass capacitor recommendations.)
Battery Power Supply for the SIMO Switch-
Mode Power Supply (SMPS). See VREGI
C9, B4 VREGI — — —
Design Considerations and Device PCB Power
Connectivity.
Bluetooth LDO Input. Bypass BLE_LDO_IN with
a 1μF capacitor to VSS placed as close as
possible to the BLE_LDO_IN device pin. This
B3 BLE_LDO_IN — — — device pin must be connected as shown in
Device PCB Power Connectivity, even if
Bluetooth functionality is not desired for the
application.
1.8V Analog Power Supply. Bypass with 1μF to
B5 VDDA — — — VSS. This device pin must be connected as
shown in Device PCB Power Connectivity.
Digital Core Supply Voltage A. VCOREA must be
greater than or equal to VCOREB. Bypass with
D9 VCOREA — — —
1μF to VSS. This device pin must be connected
as shown in Device PCB Power Connectivity.
Digital Core Supply Voltage B. VCOREA must be
greater than or equal to VCOREB. Bypass with
C8 VCOREB — — —
1μF to VSS. This device pin must be connected
as shown in Device PCB Power Connectivity.
Bluetooth Radio Baseband Supply Voltage
Output. Bypass this pin to VSS_RX with a 1μF
B1 VRXOUT — — —
capacitor close to the package. Do not connect
any other signal to this device pin.
Bluetooth Radio RF Supply Voltage Output.
Bypass this pin to VSS_TX with a 1μF capacitor
B2 VTXOUT — — —
close to the package. Do not connect any other
signal to this device pin.
The boosted supply voltage for the gate drive of
high-side switches. This device pin must be
B8 VBST — — —
connected as shown in Device PCB Power
Connectivity.
Buck Converter A Voltage Output. Bypass
VREGO_A with a 22μF capacitor to VSS placed
as close as possible to the VREGO_A device pin.
B7 VREGO_A — — —
This device pin must be connected as shown in
Device PCB Power Connectivity. Do not connect
any other signal to this device pin.
Buck Converter B Voltage Output. Bypass
VREGO_B with a 22μF capacitor to VSS placed
as close as possible to the VREGO_B device pin.
B6 VREGO_B — — —
This device pin must be connected as shown in
Device PCB Power Connectivity. Do not connect
any other signal to this device pin.

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

81 CTBGA
FUNCTION MODE
PIN NAME Primary Signal Alternate Alternate FUNCTION
(Default) Function 1 Function 2
Buck Converter C Voltage Output. Bypass
VREGO_C with a 22μF capacitor to VSS placed
as close as possible to the VREGO_C device pin.
A6 VREGO_C — — —
This device pin must be connected as shown in
Device PCB Power Connectivity. Do not connect
any other signals to this device pin.
Buck Converter D Voltage Output. Bypass
VREGO_D with a 22μF capacitor to VSS placed
as close as possible to the VREGO_D device pin.
A7 VREGO_D — — —
This device pin must be connected as shown in
Device PCB Power Connectivity. Do not connect
any other signal to this device pin.
GPIO Supply Voltage. VDDIOH must be greater
than VDDIO. Bypass this device pin to VSS with
J5 VDDIO — — — a 1μF capacitor placed as close to the package
as possible. This device pin must be connected
as shown in Device PCB Power Connectivity.
GPIO Supply Voltage, High. VDDIOH must be
greater than VDDIO. Bypass this device pin to
VSS with a 1μF capacitor placed as close to the
J4 VDDIOH — — — package as possible. This device pin must be
connected as shown in Device PCB Power
Connectivity. Do not connect any other signal to
this device pin.
D1, E9 VSS — — — Digital Ground
A5 VSSA — — — Analog Ground
Ground for the SIMO SMPS. See VREGI Design
A9 VSSPWR — — —
Considerations.
C3 VSS_RX — — — Bluetooth Radio Baseband Ground
A2 VSS_TX — — — Bluetooth Radio RF Ground
Switching Inductor Input A. Connect a 2.2μH
B9 LXA — — — inductor between LXA and LXB. See Device
PCB Power Connectivity
Switching Inductor Input B. Connect a 2.2μH
A8 LXB — — — inductor between LXA and LXB. See Device
PCB Power Connectivity
RESET AND CONTROL
External System Reset Input (Active-Low). The
device remains in reset while this pin is in its
active state. When the pin transitions to its
F6 RSTN — — —
inactive state, the device performs a system
reset and executes the first instruction. This pin
has an internal pull-up to the VDDIOH supply.

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

81 CTBGA
FUNCTION MODE
PIN NAME Primary Signal Alternate Alternate FUNCTION
(Default) Function 1 Function 2
CLOCK
32kHz Crystal Oscillator Output. Connect a
32kHz crystal between 32KIN and 32KOUT for
A3 32KOUT — — — RTC operation. If the RTC is unused, and a
crystal is not connected, do not connect this
device pin.
32kHz Crystal Oscillator Input. Connect a 32kHz
crystal between 32KIN and 32KOUT for RTC
operation. Optionally, this pin can be configured
as the input for an external CMOS-level clock
source. Load capacitors are not required. If the
A4 32KIN — — —
RTC is unused, and a crystal is not connected,
connect this device pin to VSS through a 1kΩ
resistor. See External RTC Oscillator (ERTCO)
in the Electrical Characteristics table and RTC
Crystal Guidelines for more information.
32MHz Crystal Oscillator Output. When this
C2 HFXOUT — — —
device pin is not used, do not connect.
32MHz Crystal Oscillator Input. Connect a
32MHz crystal between HFXIN and HFXOUT for
Bluetooth operation or I2S controller operation.
During the optional kick-start operation, a series
C1 HFXIN — — —
of pulses is output on this device pin to stimulate
the crystal. If the 32MHz crystal is not in use and
is not connected, connect the device pin to VSS
through a 10kΩ resistor.
GPIO AND ALTERNATE FUNCTION
F7 P0.0 P0.0 UART0A_RX — UART0 Receive Port Map A
E7 P0.1 P0.1 UART0A_TX — UART0 Transmit Port Map A
Timer 0 I/O 32 Bits or Lower 16 Bits Port Map A;
F8 P0.2 P0.2 TMR0A_IOA UART0B_CTS
UART0 Clear to Send Port Map B
External Clock for Use as SYS_OSC/Timer 0
EXT_CLK/
F9 P0.3 P0.3 UART0B_RTS I/O Upper 16 Bits Port Map A; UART0 Request
TMR0A_IOB
to Send Port Map B
SPI0 Target Select 0; Timer 0 Inverted Output
G9 P0.4 P0.4 SPI0_SS0 TMR0B_IOAN
Port Map B
SP0 Controller Out Target In Serial Data 0;
G8 P0.5 P0.5 SPI0_MOSI TMR0B_IOBN 32-Bit Timer 0 Inverted Output Upper 16 Bits
Port Map B
SPI0 Controller In Target Out Serial Data 1;
G7 P0.6 P0.6 SPI0_MISO OWM_IO
1-Wire Controller Data I/O
SPI0 Clock; 1-Wire Controller Pull-up Enable
H9 P0.7 P0.7 SPI0_SCK OWM_PE
Output
SPI0 Data 2 I/O; Timer 0 I/O 32 Bits or Lower 16
H8 P0.8 P0.8 SPI0_SDIO2 TMR0B_IOA
Bits Port Map B
SPI0 Data 3 I/O; Timer 0 I/O Upper 16 Bits Port
J9 P0.9 P0.9 SPI0_SDIO3 TMR0B_IOB
Map B
H7 P0.10 P0.10 I2C0_SCL SPI0_SS2 I2C0 Clock; SPI0 Target Select 2

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

81 CTBGA
FUNCTION MODE
PIN NAME Primary Signal Alternate Alternate FUNCTION
(Default) Function 1 Function 2
J8 P0.11 P0.11 I2C0_SDA SPI0_SS1 I2C0 Serial Data; SPI0 Target Select 1
UART1 Receive Port Map A; Timer 1 Inverted
G6 P0.12 P0.12 UART1A_RX TMR1B_IOAN
Output Port Map B
UART1 Transmit Port Map A; Timer 1 Inverted
H6 P0.13 P0.13 UART1A_TX TMR1B_IOBN
Output Upper 16 Bits Port Map B
Timer 1 I/O 32 Bits or Lower 16 Bits Port Map A;
J7 P0.14 P0.14 TMR1A_IOA UART1B_CTS
UART1 Clear to Send Port Map B
Timer 1 I/O Upper 16 Bits Port Map A; UART1
J6 P0.15 P0.15 TMR1A_IOB UART1B_RTS
Request to Send Port Map B
G5 P0.16 P0.16 I2C1_SCL PT2 I2C1 Clock; Pulse Train 2
F5 P0.17 P0.17 I2C1_SDA PT3 I2C1 Serial Data; Pulse Train 3
H5 P0.18 P0.18 PT0 OWM_IO Pulse Train 0; 1-Wire Controller Data I/O
Pulse Train 1; 1-Wire Controller Pull-up Enable
G4 P0.19 P0.19 PT1 OWM_PE
Output
SPI1 Target Select 0; Timer 1 I/O 32 Bits or
H4 P0.20 P0.20 SPI1_SS0 TMR1B_IOA
Lower 16 Bits Port Map B
SPI1 Controller Out Target In Serial Data 0;
J3 P0.21 P0.21 SPI1_MOSI TMR1B_IOB
Timer 1 I/O Upper 16 Bits Port Map B
SPI1 Controller In Target Out Serial Data 1;
H3 P0.22 P0.22 SPI1_MISO TMR1B_IOAN
Timer 1 Inverted Output Port Map B
SPI1 Clock; Timer 1 Inverted Output Upper 16
G3 P0.23 P0.23 SPI1_SCK TMR1B_IOBN
Bits Port Map B
SPI1 Data 2; Timer 2 I/O 32 Bits or Lower 16
J2 P0.24 P0.24 SPI1_SDIO2 TMR2B_IOA
Bits Port Map B
SPI1 Data 3; Timer 2 I/O Upper 16 Bits Port
J1 P0.25 P0.25 SPI1_SDIO3 TMR2B_IOB
Map B
Timer 2 I/O 32 Bits or Lower 16 Bits Port Map A;
H1 P0.26 P0.26 TMR2A_IOA SPI1_SS1
SPI1 Target Select 1
Timer 2 I/O Upper 16 Bits Port Map A; SPI1
H2 P0.27 P0.27 TMR2A_IOB SPI1_SS2
Target Select 2
G1 P0.28 SWDIO SWDIO — Serial Wire Debug Data I/O
G2 P0.29 SWCLK SWCLK — Serial Wire Debug Clock
F1 P0.30 P0.30 I2C2_SCL UART2B_CTS I2C2 Clock; UART2 Clear to Send Port Map B
I2C2 Serial Data; UART2 Request to Send Port
F4 P0.31 P0.31 I2C2_SDA UART2B_RTS
Map B
UART2 Receive Port Map A; 32-Bit RISC-V Test
F3 P1.0 P1.0 UART2A_RX RV_TCK
Port Clock
UART2 Transmit Port Map A; 32-Bit RISC-V
F2 P1.1 P1.1 UART2A_TX RV_TMS
Test Port Select
I2S Bit Clock; 32-Bit RISC-V Test Port Data
D5 P1.2 P1.2 I2S_SCK RV_TDI
Input
I2S Left/Right Clock; 32-Bit RISC-V Test Port
E4 P1.3 P1.3 I2S_WS RV_TDO
Data Output

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

81 CTBGA
FUNCTION MODE
PIN NAME Primary Signal Alternate Alternate FUNCTION
(Default) Function 1 Function 2
I2S Serial Data Input; Timer 3 I/O 32 Bits or
E1 P1.4 P1.4 I2S_SDI TMR3B_IOA
Lower 16 Bits Port Map B
I2S Serial Data Output; Timer 3 I/O Upper 16
E3 P1.5 P1.5 I2S_SDO TMR3B_IOB
Bits Port Map B
BLE_ANT_CTR Timer 3 I/O 32 Bits or Lower 16 Bits Port Map A;
E2 P1.6 P1.6 TMR3A_IOA
L2 Bluetooth Antenna Control Line 2
BLE_ANT_CTR Timer 3 I/O Upper 16 Bits Port Map A; Bluetooth
D4 P1.7 P1.7 TMR3A_IOB
L3 Antenna Control Line 3
BLE_ANT_CTR Bluetooth Antenna Control Line 0; CM4 Rx
D2 P1.8 P1.8 RXEV0
L0 Event Input
BLE_ANT_CTR Bluetooth Antenna Control Line 1; CM4 Tx
D3 P1.9 P1.9 TXEV0
L1 Event Output
Analog-to-Digital Converter Input 0/Comparator
C4 P2.0 P2.0 AIN0/AIN0N —
0 Negative Input
Analog-to-Digital Converter Input 1/Comparator
C5 P2.1 P2.1 AIN1/AIN0P —
0 Positive Input
Analog-to-Digital Converter Input 2/Comparator
D8 P2.2 P2.2 AIN2/AIN1N —
1 Negative Input
Analog-to-Digital Converter Input 3/Comparator
E8 P2.3 P2.3 AIN3/AIN1P —
1 Positive Input
Analog-to-Digital Converter Input 4/Comparator
C7 P2.4 P2.4 AIN4/AIN2N LPTMR0B_IOA 2 Negative Input; Low-Power Timer 0 I/O Port
Map B
Analog-to-Digital Converter Input 5/Comparator
D7 P2.5 P2.5 AIN5/AIN2P LPTMR1B_IOA 2 Positive Input; Low-Power Timer 1 I/O Port
Map B
Low-Power Timer 0 External Clock Input/
LPTMR0_CLK/ Analog-to-Digital Converter Input 6/Comparator
C6 P2.6 P2.6 LPUARTB_RX
AIN6/AIN3N 3 Negative Input; Low-Power UART 0 Receive
Port Map B
Low-Power Timer 1 External Clock Input/
LPTMR1_CLK/ Analog-to-Digital Converter Input 7/Comparator
D6 P2.7 P2.7 LPUARTB_TX
AIN7/AIN3P 3 Positive Input; Low-Power UART Transmit
Port Map B
Power-Down Output. Internally pulled down to
E5 P3.0 P3.0 PDOWN — VSS. This device pin can only be powered by
VDDIOH. Can be used as a WAKE-UP source.
Square-Wave Output. Internally pulled down to
E6 P3.1 P3.1 SQWOUT — VSS. This device pin can only be powered by
VDDIOH.
ANTENNA OUTPUT
Antenna for Bluetooth Radio. Attach the single-
ended, unbalanced Bluetooth radio antenna. If
A1 ANT — — — Bluetooth functionality is not used, and there is
no antenna connected, do not connect this
device pin.

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

Pin Configuration
51 WLP
TOP VIEW MAX32655
1 2 3 4 5 6 7 8

A P0.28 P0.22 P0.12 P0.11 P0.7 P0.5 A

B P0.29 P0.26 P0.21 P0.10 P0.6 P0.3 P0.2 RSTN B

C P1.6 P0.23 P0.20 P0.0 P0.1 P2.6 C

D VDDIO VDDIOH P0.4 P2.7 P2.1 VSS D

E HFXOUT HFXIN VSSA VDDA VCOREA VCOREB E

F VSS_RX VTXOUT VRXOUT P2.0 VBST VREGI F

G VSS_TX 32KOUT 32KIN VREGO_D VREGO_A VSSPWR LXA G

H ANT BLE_LDO_IN VREGI VREGO_C VREGO_B LXB H

1 2 3 4 5 6 7 8

51 WLP

Pin Descriptions – 51 WLP

FUNCTION MODE
PIN NAME Primary Signal Alternate Alternate FUNCTION
(Default) Function 1 Function 2
POWER (See the Applications Information section for bypass capacitor recommendations.)
Battery Power Supply for the SIMO Switch-
Mode Power Supply (SMPS). See VREGI
F8, H4 VREGI — — —
Design Considerations and Device PCB Power
Connectivity.

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

51 WLP
FUNCTION MODE
PIN NAME Primary Signal Alternate Alternate FUNCTION
(Default) Function 1 Function 2
Bluetooth LDO Input. Bypass BLE_LDO_IN with
a 1μF capacitor to VSS placed as close as
possible to the BLE_LDO_IN device pin. This
H3 BLE_LDO_IN — — — device pin must be connected as shown in
Device PCB Power Connectivity, even if
Bluetooth functionality is not desired for the
application.
1.8V Analog Power Supply. Bypass with 1μF to
E5 VDDA — — — VSS. This device pin must be connected as
shown in Device PCB Power Connectivity.
Digital Core Supply Voltage A. VCOREA must be
greater than or equal to VCOREB. Bypass with
E7 VCOREA — — —
1μF to VSS. This device pin must be connected
as shown in Device PCB Power Connectivity.
Digital Core Supply Voltage B. VCOREA must be
greater than or equal to VCOREB. Bypass with
E8 VCOREB — — —
1μF to VSS. This device pin must be connected
as shown in Device PCB Power Connectivity.
Bluetooth Radio Baseband Supply Voltage
Output. Bypass this pin to VSS_RX with a 1μF
F3 VRXOUT — — —
capacitor close to the package. Do not connect
any other signal to this device pin.
Bluetooth Radio RF Supply Voltage Output.
Bypass this pin to VSS_TX with a 1μF capacitor
F2 VTXOUT — — —
close to the package. Do not connect any other
signal to this device pin.
The boosted supply voltage for the gate drive of
high-side switches. This device pin must be
F7 VBST — — —
connected as shown in Device PCB Power
Connectivity.
Buck Converter A Voltage Output. Bypass
VREGO_A with a 22μF capacitor to VSS placed
as close as possible to the VREGO_A device pin.
G6 VREGO_A — — —
This device pin must be connected as shown in
Device PCB Power Connectivity. Do not connect
any other signal to this device pin.
Buck Converter B Voltage Output. Bypass
VREGO_B with a 22μF capacitor to VSS placed
as close as possible to the VREGO_B device pin.
H6 VREGO_B — — —
This device pin must be connected as shown in
Device PCB Power Connectivity. Do not connect
any other signal to this device pin.
Buck Converter C Voltage Output. Bypass
VREGO_C with a 22μF capacitor to VSS placed
as close as possible to the VREGO_C device pin.
H5 VREGO_C — — —
This device pin must be connected as shown in
Device PCB Power Connectivity. Do not connect
any other signal to this device pin.

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

51 WLP
FUNCTION MODE
PIN NAME Primary Signal Alternate Alternate FUNCTION
(Default) Function 1 Function 2
Buck Converter D Voltage Output. Bypass
VREGO_D with a 22μF capacitor to VSS placed
as close as possible to the VREGO_D device pin.
G5 VREGO_D — — —
This device pin must be connected as shown in
Device PCB Power Connectivity. Do not connect
any other signal to this device pin.
GPIO Supply Voltage. VDDIOH must be greater
than VDDIO. Bypass this device pin to VSS with
D1 VDDIO — — — a 1μF capacitor placed as close to the package
as possible. This device pin must be connected
as shown in Device PCB Power Connectivity.
GPIO Supply Voltage, High. VDDIOH must be
greater than VDDIO. Bypass this device pin to
VSS with a 1μF capacitor placed as close to the
D2 VDDIOH — — —
package as possible. This device pin must be
connected as shown in Device PCB Power
Connectivity.
D8 VSS — — — Digital Ground
E4 VSSA — — — Analog Ground
Ground for the SIMO SMPS. See VREGI Design
G7 VSSPWR — — —
Considerations.
F1 VSS_RX — — — Bluetooth Radio Baseband Ground
G2 VSS_TX — — — Bluetooth Radio RF Ground
Switching Inductor Input A. Connect a 2.2μH
G8 LXA — — — inductor between LXA and LXB. See Device
PCB Power Connectivity.
Switching Inductor Input B. Connect a 2.2μH
H7 LXB — — — inductor between LXA and LXB. See Device
PCB Power Connectivity.
RESET AND CONTROL
External System Reset Input (Active-Low). The
device remains in reset while this pin is in its
active state. When the pin transitions to its
B8 RSTN — — —
inactive state, the device performs a system
reset and executes the first instruction. This pin
has an internal pull-up to the VDDIOH supply.
CLOCK
32kHz Crystal Oscillator Output. Connect a
32kHz crystal between 32KIN and 32KOUT for
G3 32KOUT — — — RTC operation. If the RTC is unused, and a
crystal is not connected, do not connect this
device pin.

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

51 WLP
FUNCTION MODE
PIN NAME Primary Signal Alternate Alternate FUNCTION
(Default) Function 1 Function 2
32kHz Crystal Oscillator Input. Connect a 32kHz
crystal between 32KIN and 32KOUT for RTC
operation. Optionally, this pin can be configured
as the input for an external CMOS-level clock
source. Load capacitors are not required. If the
G4 32KIN — — —
RTC is unused, and a crystal is not connected,
connect this device pin to VSS through a 1kΩ
resistor. See External RTC Oscillator (ERTCO)
in the Electrical Characteristics table and RTC
Crystal Guidelines for more information.
32MHz Crystal Oscillator Output. When this
E1 HFXOUT — — —
device pin is not used, do not connect.
32MHz Crystal Oscillator Input. Connect a
32MHz crystal between HFXIN and HFXOUT for
Bluetooth operation. During the optional kick-
start operation, a series of pulses is output on
E2 HFXIN — — —
this device pin to stimulate the crystal. If the
32MHz crystal is not in use and is not
connected, connect the device pin to VSS
through a 10kΩ resistor.
GPIO AND ALTERNATE FUNCTION (See the Applications Information section for GPIO and Alternate Function Matrices.)
C6 P0.0 P0.0 UART0A_RX — UART0 Receive Port Map A
C7 P0.1 P0.1 UART0A_TX — UART0 Transmit Port Map A
Timer 0 I/O 32 Bits or Lower 16 Bits Port Map A;
B7 P0.2 P0.2 TMR0A_IOA UART0B_CTS
UART0 Clear to Send Port Map B
External Clock for Use as SYS_OSC/Timer 0
EXT_CLK/
B6 P0.3 P0.3 UART0B_RTS I/O Upper 16 Bits Port Map A; UART0 Request
TMR0A_IOB
to Send Port Map B
SPI0 Target Select 0; Timer 0 Inverted Output
D4 P0.4 P0.4 SPI0_SS0 TMR0B_IOAN
Port Map B
SP0 Controller Out Target In Serial Data 0;
A7 P0.5 P0.5 SPI0_MOSI TMR0B_IOBN 32-Bit Timer 0 Inverted Output Upper 16 Bits
Port Map B
SPI0 Controller In Target Out Serial Data 1;
B5 P0.6 P0.6 SPI0_MISO OWM_IO
1-Wire Controller Data I/O
SPI0 Clock; 1-Wire Controller Pull-up Enable
A6 P0.7 P0.7 SPI0_SCK OWM_PE
Output
B4 P0.10 P0.10 I2C0_SCL SPI0_SS2 I2C0 Clock; SPI0 Target Select 2
A5 P0.11 P0.11 I2C0_SDA SPI0_SS1 I2C0 Serial Data; SPI0 Target Select 1
UART1 Receive Port Map A; Timer 1 Inverted
A4 P0.12 P0.12 UART1A_RX TMR1B_IOAN
Output Port Map B
SPI1 Target Select 0; Timer 1 I/O 32 Bits or
C3 P0.20 P0.20 SPI1_SS0 TMR1B_IOA
Lower 16 Bits Port Map B
SPI1 Controller Out Target In Serial Data 0;
B3 P0.21 P0.21 SPI1_MOSI TMR1B_IOB
Timer 1 I/O Upper 16 Bits Port Map B
SPI1 Controller In Target Out Serial Data 1;
A3 P0.22 P0.22 SPI1_MISO TMR1B_IOAN
Timer 1 Inverted Output Port Map B

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

51 WLP
FUNCTION MODE
PIN NAME Primary Signal Alternate Alternate FUNCTION
(Default) Function 1 Function 2
SPI1 Clock; Timer 1 Inverted Output Upper 16
C2 P0.23 P0.23 SPI1_SCK TMR1B_IOBN
Bits Port Map B
Timer 2 I/O 32 Bits or Lower 16 Bits Port Map A;
B2 P0.26 P0.26 TMR2A_IOA SPI1_SS1
SPI1 Target Select 1
A2 P0.28 SWDIO SWDIO — Serial Wire Debug Data I/O
B1 P0.29 SWCLK SWCLK — Serial Wire Debug Clock
BLE_ANT_CTR Timer 3 I/O 32 Bits or Lower 16 Bits Port Map A;
C1 P1.6 P1.6 TMR3A_IOA
L2 Bluetooth Antenna Control Line 2
Analog-to-Digital Converter Input 0/Comparator
F6 P2.0 P2.0 AIN0/AIN0N —
0 Negative Input
Analog-to-Digital Converter Input 1/Comparator
D7 P2.1 P2.1 AIN1/AIN0P —
0 Positive Input
Low-Power Timer 0 External Clock Input/
LPTMR0_CLK/ Analog-to-Digital Converter Input 6/Comparator
C8 P2.6 P2.6 LPUARTB_RX
AIN6/AIN3N 3 Negative Input; Low-Power UART 0 Receive
Port Map B
Low-Power Timer 1 External Clock Input/
LPTMR1_CLK/ Analog-to-Digital Converter Input 7/Comparator
D5 P2.7 P2.7 LPUARTB_TX
AIN7/AIN3P 3 Positive Input; Low-Power UART Transmit
Port Map B
ANTENNA OUTPUT
Antenna for Bluetooth Radio. Attach the single-
ended, unbalanced Bluetooth radio antenna. If
H2 ANT — — — Bluetooth functionality is not used, and there is
no antenna connected, do not connect this
device pin.

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

Detailed Description
The MAX32655 microcontroller (MCU) is an advanced system-on-chip (SoC) featuring an Arm® Cortex®-M4F CPU for
efficient computation of complex functions and algorithms that is qualified to operate at a temperature range of -40°C
to +105°C. The SoC integrates power regulation and management with a single inductor multiple-output (SIMO) buck
regulator system. The latest generation Bluetooth® 5.2 Low Energy (LE) radio is on board, supporting long-range (coded)
and high-throughput modes and medical body area network (MBAN).
The device offers large onboard memory with 512KB flash and 128KB SRAM, with optional error correction coding (ECC)
on one 32KB SRAM bank. This 32KB bank can be optionally retained in BACKUP mode. An 8KB user OTP area is
available.
The MAX32655 supports multiple high-speed peripherals, such as I2C, 50MHz SPI, and UART, plus one I2S port for
connecting to an audio codec. An eight-input, 10-bit ADC is available to monitor analog input from external analog
sources. In addition, a low-power UART (LPUART) is available for operation in the lowest power sleep modes to facilitate
wake-up activity without any data loss. A total of six timers with I/O capability are provided, including two low-power
timers to enable pulse counting, capture/compare, and pulse-width modulation (PWM) generation, even in the lowest
power sleep modes.
The MAX32655 is available in two different packages:
● 81 CTBGA (8mm x 8mm, 0.8mm pitch)
● 51 WLP (3.09mm x 3.09mm, 0.35mm pitch)

Arm Cortex-M4 (CM4) with FPU Processor and RISC-V (RV32) Processor
The Arm Cortex-M4 with FPU processor is ideal for low-power system control. The architecture combines high-efficiency
signal processing functionality with low power, low cost, and ease of use.
The Arm Cortex-M4 with FPU DSP supports single instruction multiple data (SIMD) path DSP extensions, providing:
● Four parallel 8-bit add/sub
● Floating-point single precision
● Two parallel 16-bit add/sub
● Two parallel MACs
● 32- or 64-bit accumulate
● Signed and unsigned data with or without saturation
The addition of 32-bit RISC-V processor (RV32) provides the system with ultra-low-power consumption signal
processing.

Memory
Internal Flash Memory
512KB of internal flash memory provides nonvolatile storage of program and data memory.

Internal SRAM
The internal 128KB SRAM provides low-power retention of application information in all power modes except POWER
DOWN. The SRAM is divided into four banks. SRAM0 and SRAM1 are both 32KB, SRAM2 is 48KB, and SRAM3 is
16KB. SRAM2 and SRAM3 are accessible by the RV32 in LOW POWER mode. For enhanced system reliability, SRAM0
(32KB) can be configured with error correction coded (ECC) or single error correction-double error detection (SED-DED).
This data retention feature is optional and configurable. This granularity allows the application to minimize its power
consumption by only retaining the most essential data.

Bluetooth 5.2
Bluetooth 5.2 Low Energy Radio
Bluetooth 5.2 LE is the latest version of the Bluetooth wireless communication standard. Bluetooth LE communications

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
FPU-Based Microcontroller and Bluetooth 5.2

operate in the unlicensed 2.4GHz industrial-scientific-medical (ISM) band. A frequency-hopping transceiver is used to
combat interference and fading. It uses 40 RF channels. These RF channels have 2402 + k x 2MHz center frequencies,
where k = 0, ..., 39. The Bluetooth stack runs on RV32, so the CM4 can be freed to run the software. The features of the
radio include the following:
● Higher transmit power up to +5.5dbm
● 1Mbps, 2Mbps, and long-range coded (125kbps and 500kbps)
● Increased broadcast capability
• Advertising packet up to 255 bytes
● On-chip matching network to the antenna
● Antenna control outputs
● Provides hardware on-the-fly encryption and decryption for lower power consumption
● Low transmit current of 4.17mA at 0dbm at 3.3V
● Low receive current of 4.0mA at 3.3V
● Supports MBAN

Bluetooth 5.2 Software Stack

A Bluetooth 5.2 software stack is available for application developers to quickly add support to devices. The Arm
Cordio®-B50 software stack is provided in library form and provides application developers access to Bluetooth
technology without validation and development of a software stack. The Cordio-B50 software stack interfaces to the
Bluetooth link layer running on dedicated hardware. The dedicated hardware for the stack enables the ultimate in power
management for IoT applications. Cordio-B50 features the following:
● C library for linking directly into an application development tool
● Change PHY support
• Host selects the PHY it needs to use at any given time enabling long range or higher bandwidth only when required
• Bluetooth LE 1M
• Bluetooth LE Coded S = 2
• Bluetooth LE Coded S = 8
• Bluetooth LE 2M
● Bluetooth 5.2 advertising extension support for enabling next-generation Bluetooth beacons
• Larger packets and advertising channel offloading
• Packets up to 255 octets long
• Advertising packet chaining
• Advertising sets
• Periodic advertising
• High-duty cycle non-connectable advertising
• Sample applications using standard profiles built on the Cordio-B50 software framework

Comparators
The ADC inputs can be configured as pairs and deployed as independent comparators with the following features:
● Comparison events can trigger interrupts
● Events can wake the CM4 from SLEEP, LPM, UPM, STANDBY, or BACKUP operating modes
● Can be active in all power modes
The instances and characteristics of the peripheral are shown in Table 1. Some instances may not be available in every
package configuration; see the Ordering Information table for the specific instances available by part number.

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Table 1. MAX32655 Comparator Instances

PACKAGES
81 CTBGA 51 WLP
CMP0 (AIN0N/AIN0P)
CMP1 (AIN1N/AIN1P) CMP0 (AIN0N/AIN0P)
CMP2 (AIN2N/AIN2P) CMP3 (AIN3N/AIN3P)
CMP3 (AIN3N/AIN3P)

Clocking Scheme
Multiple clock sources can be selected as the system clock:
● Internal primary oscillator (IPO) at a nominal frequency of 100MHz
● Internal secondary oscillator (ISO) at a nominal frequency of 60MHz
● Configurable internal nano-ring oscillator (INRO) at 8kHz, 16kHz, or 30kHz
● External RTC oscillator at 32.768kHz (ERTCO)—external crystal required
● Internal baud rate oscillator at 7.3728MHz (IBRO)
● External square-wave clock up to 80MHz
● External RF oscillator at 32MHz (ERFO)—external crystal required
• An internal kick-start circuit improves the ERFO startup time.
There are multiple external clock inputs:
● LPTMR0 and LPTMR1 can be clocked from unique external sources.
● SYS_CLK can be derived from an external source.

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RTC/CALIBRATION OUTPUT
SQWOUT
(P3.1)
XTAL DRIVER OR 32KIN BYPASS
32KIN RTC_OSCCTRL.bypass
EXTERNAL CLOCK LEGEND
32.768kHz 32.768kHz 32.768kHz 32.768kHz
CRYSTAL OSC X = UNCONNECTED CLOCK
1Hz 512Hz 4096Hz 32768Hz INPUT
(ERTCO)
REAL-TIME CLOCK = DEVICE PIN
32KOUT
MICRO-POWER DOMAIN PERIPHERALS
POWER-DOWN MODE
LPUART0 WAKE-UP CONTROLLER
LPTMR0 LPTMR1 LPWDT0
2-WIRE TIMER
POWER
MANAGEMENT UNIT
LPTMR0_CLK (P2.6)
÷8
NANO-RING (INRO)
LPTMR1_CLK (P2.7) 8kHz, 16kHz, 30kHz

AUTO-CAL
100MHz GCR_CLKCN.clksel

100MHz

INTERNAL PRIMARY Arm Cortex

OSCILLATOR (IPO) M4 4-CH
SPI0
(CM4) DMA
32.768kHz
7.3728MHz

7.3728MHz
SYS_CLK ÷2
INTERNAL BAUD RATE GCR_CLKCN.psc APB CLK
OSCILLATOR (IBRO)

SYS_OSC
60MHz PRESCALER

60MHz

INTERNAL SECONDARY
OSCILLATOR (ISO)
PLPCR_LPCN.lpmclksel
RISC-V
HFXIN (RV32)
32MHz 32MHz OSC
CRYSTAL (ERFO)
500kΩ
WITH GCR_PCKDIV.adcfrq
KICK START
ADC
HFXOUT AES/CRC/
ADC CLOCK
TRNG
<8MHz SCALER
Bluetooth 5.2

EXT_CLK (P0.3)

UART0 UART1 UART2 4 x PULSE 3x

TMR0 TMR1 TMR2 TMR3 WDT0 1-Wire I2 S SPI1
4-WIRE 4-WIRE 4-WIRE TRAINS I2 C

Figure 8. 81 CTBGA Clocking Scheme Diagram

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RTC/CALIBRATION OUTPUT
SQWOUT
(P3.1)
XTAL DRIVER OR 32KIN BYPASS
32KIN RTC_OSCCTRL.bypass
EXTERNAL CLOCK LEGEND
32.768kHz 32.768kHz 32.768kHz 32.768kHz
CRYSTAL OSC X = UNCONNECTED CLOCK
1Hz 512Hz 4096Hz 32768Hz
(ERTCO) INPUT
REAL-TIME CLOCK = DEVICE PIN
32KOUT
MICRO-POWER DOMAIN PERIPHERALS
POWER-DOWN MODE
LPUART0 WAKE-UP CONTROLLER
LPTMR0 LPTMR1 LPWDT0
2-WIRE TIMER
POWER
MANAGEMENT UNIT
LPTMR0_CLK (P2.6)
÷8
NANO-RING (INRO)
LPTMR1_CLK (P2.7) 8kHz, 16kHz, 30kHz

AUTO-CAL
100MHz GCR_CLKCN.clksel

100MHz

INTERNAL PRIMARY Arm Cortex

OSCILLATOR (IPO) M4 4-CH
SPI0
(CM4) DMA
32.768kHz
7.3728MHz

7.3728MHz
SYS_CLK ÷2
INTERNAL BAUD RATE GCR_CLKCN.psc APB CLK
OSCILLATOR (IBRO)

SYS_OSC
60MHz PRESCALER

60MHz

INTERNAL SECONDARY
OSCILLATOR (ISO)
PLPCR_LPCN.lpmclksel
HFXIN RISC-V
(RV32)
32MHz OSC
32MHz (ERFO)
500kΩ
CRYSTAL WITH KICK
GCR_PCKDIV.adcfrq
START
HFXOUT ADC
AES/CRC/
ADC CLOCK
TRNG
Bluetooth 5.2 <8MHz SCALER

EXT_CLK (P0.3)

UART0
TMR0 TMR1 TMR2 TMR3
4-WIRE
WDT0 1-Wire I2 C SPI1

Figure 9. 51 WLP Clocking Scheme Diagram

General-Purpose I/O (GPIO) and Special Function Pins

Most GPIO pins share both a firmware-controlled I/O function and one or more alternate functions associated with
peripheral modules. Pins can be individually enabled for GPIO or peripheral special function use. Configuring a pin as a
special function usually supersedes its use as a firmware-controlled I/O. Although this multiplexing between peripheral
and GPIO functions is usually static, it can also be done dynamically. The electrical characteristics of a GPIO pin are
identical whether the pin is configured as an I/O or special function, except where explicitly noted in the Electrical
Characteristics tables.
Caution is needed since Port 3 (P3.0 and P3.1 device pins) is configured in a different manner from the above description.

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In GPIO mode, pins are logically divided into ports of 32 pins. Each pin of a port has an interrupt function that can be
independently enabled, and configured as a level- or edge-sensitive interrupt. All GPIOs of a given port share the same
interrupt vector.
When configured as GPIO, all features can be independently enabled or disabled on a per-pin basis. The following
features are provided:
● Configurable as input, output, bidirectional, or high impedance
● Optional internal pull-up resistor or internal pull-down resistor when configured as input
● Exit from low-power modes on rising or falling edge
● Selectable standard- or high-drive modes
Up to 52 GPIO pins are provided. The number of GPIOs varies by part package configuration; see the Ordering
Information table for the number of GPIOs available by part number.

Analog-to-Digital Converter (ADC)

The 10-bit sigma-delta (Σ-Δ) ADC provides an integrated reference generator and a single-ended input multiplexer. The
multiplexer selects an input channel from one of the eight external analog input signals (AIN0–AIN7) or the internal power
supply inputs.
The reference for the ADC can be:
● Internal 1.22V bandgap
● VSSA analog supply
An optional feature allows samples captured by the ADC to be automatically compared against user-programmable high
and low limits. Up to four channel limit pairs can be configured in this way. The comparison allows the ADC to trigger an
interrupt (and potentially wake the CPU from a power mode) when a captured sample goes outside the preprogrammed
limit range. The eight ADC inputs can be configured as pairs and deployed as independent comparators.
The ADC measures the following voltages:
● AIN[7:0] up to 3.3V
● VREGI
● VCOREA
● VCOREB
● VDDIOH
● VDDIO
● VTXOUT
● VRXOUT
● VDDA
See Table 2 for details of instances of the ADC.
Table 2. MAX32655 ADC External Inputs
PACKAGES
OPERATING MODES
81 CTBGA 51 WLP
AIN0
AIN1
AIN2 AIN0
ACTIVE
AIN3 AIN1
SLEEP
AIN4 AIN6
LPM
AIN5 AIN7
AIN6
AIN7

Single-Inductor Multiple-Output (SIMO) Switch-Mode Power Supply (SMPS)

The SIMO SMPS built into the device provides a monolithic power supply architecture for operation from a single lithium
cell. The SIMO provides four buck regulator outputs that are voltage programmable. This architecture optimizes power
consumption efficiency of the device and minimizes the bill of materials for the circuit design since only a single inductor/

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capacitor pair is required.

Power Management
Power Management Unit (PMU)
The PMU provides high-performance operation while minimizing power consumption. It exercises intelligent, precise
control of power distribution to the CPUs and peripheral circuitry.
The PMU provides the following features:
● User-configurable system clock
● Automatic enabling and disabling of crystal oscillators based on power mode
● Multiple power domains
● Fast wake-up of powered-down peripherals when activity detected

ACTIVE Mode
In this mode, the CM4 and the RV32 can execute application code and all digital and analog peripherals are available on
demand. Dynamic clocking disables peripherals not in use, providing the optimal mix of high performance and low power
consumption. The CM4 has access to all system SRAM. The RV32 has access to SRAM2 and SRAM3. Both the CM4
and the RV32 can execute from internal flash simultaneously. SRAM3 can be configured as an instruction cache for the
RV32.

SLEEP Mode
This mode allows for lower power consumption operations than ACTIVE mode. The GPIO or any active peripheral can
be configured to interrupt and cause a transition to ACTIVE mode. This mode consumes less power, but wakes faster
because the clocks can optionally be enabled.
The device status is as follows:
● CM4 is in the Arm Cortex-M4 processor SLEEP mode.
● RV32 is asleep.
● Peripherals are on.
● Standard DMA is available for optional use.

LOW POWER Mode (LPM)

This mode is suitable for running the RV32 processor to collect and move data from enabled peripherals.
The device status is a follows:
● The CM4, SRAM0, and SRAM1 are in state retention.
● The RV32 can access the SPI, all UARTS, all timers, I2C, 1-Wire, pulse train engines, I2S, CRC, AES, TRNG, PCIF,
and comparators, as well as SRAM2 and SRAM3. SRAM3 can be configured to operate as RV32 instruction cache.
● The transition from LOW POWER mode to ACTIVE mode is faster than the transition from BACKUP mode because
system initialization is not required.
● The DMA can access flash.
● IPO can be optionally powered down.
● The following oscillators are enabled:
• IBRO
• ERTCO
• INRO
• ISO
• ERFO

MICRO POWER Mode (UPM)

This mode is used for extremely low power consumption while using a minimal set of peripherals to provide wake-up
capability.
The device status is a follows:

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● Both CM4 and RV32 are state retained. (System state and all SRAM is retained.)
● The GPIO pins retain their state.
● All non-UPM peripherals are state retained.
● IBRO can be optionally powered down.
● The following oscillators are powered down:
• IPO
• ISO
• ERFO
● The following oscillators are enabled:
• IBRO
• ERTCO
• INRO
● The following UPM peripherals are available for use to wake up the device:
• LPUART0
• WWDT1
• All four low-power analog comparators

STANDBY Mode
This mode is used to maintain the system operation while keeping time with the RTC.
The device status is as follows:
● Both CM4 and RV32 are state retained. (System state and all SRAM is retained.)
● The GPIO pins retain their state.
● RTC is on.
● All peripherals are state retained.
● The following oscillators are powered down:
• IPO
• ISO
• IBRO
• ERFO
● The following oscillators are enabled:
• ERTCO
• INRO

BACKUP Mode
This mode is used to maintain the system RAM while keeping time with the RTC. The device status is as follows:
● CM4 and RV32 are powered off.
● SRAM0, SRAM1, SRAM2, and SRAM3 can be configured to be state retained as per Table 3.
● All peripherals are powered off.
● The GPIO pins retain their state.
● RTC is on.
● The following oscillators are powered down:
• IPO
• ISO
• IBRO
• ERFO
● The following oscillators are enabled:
• ERTCO
• INRO

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Table 3. BACKUP Mode SRAM Retention

RAM BLOCK RAM SIZE
SRAM0 32KB + ECC
SRAM1 32KB
SRAM2 48KB
SRAM3 16KB

POWER DOWN Mode (PDM)

This mode is used during product level distribution and storage.
The device status is as follows:
● The CM4 and RV32 are powered off.
● All peripherals and SRAM are powered down.
● All oscillators are powered down.
● 8 bytes of data are retained.
● Values in the flash are preserved.
● Voltage monitors are operational.

Wake-up Sources
The wake-up sources from the power modes are summarized in Table 4.
Table 4. MAX32655 Wake-up Sources
OPERATING MODE WAKE-UP SOURCE
SLEEP Any enabled peripheral with interrupt capability; RSTN
SPI0, I2S, I2C, UARTs, timers, watchdog timers, wake-up timer, all comparators, RTC, GPIOs, RSTN, and
LOW POWER (LPM)
RV32
MICRO POWER All comparators, LPUART (where available), LPTMR0, LPTMR1, LPWDT0, RTC, wake-up timer, GPIOs,
(UPM) and RSTN
STANDBY RTC, wake-up timer, GPIOs, CMP0 (where available), and RSTN
BACKUP RTC, wake-up timer, GPIOs, CMP0 (where available), and RSTN
POWER DOWN
P3.0 and RSTN
(PDM)

Real-Time Clock (RTC)

An RTC keeps the time of day in absolute seconds. The 32-bit seconds register can count up to approximately 136 years
and be translated to calendar format by application software.
The RTC provides a time-of-day alarm that is programmable to any future value between 1 second and 12 days. When
configured for long intervals, the time-of-day alarm is usable as a power-saving timer, allowing the device to remain in an
extremely low-power mode, but still awaken periodically to perform assigned tasks. A second independent 32-bit 1/4096
subsecond alarm is programmable with a tick resolution of 244μs. Both can be configured as recurring alarms. When
enabled, either alarm can cause an interrupt or wake the device from most low-power modes.
The time base is generated by a 32.768kHz crystal or an external clock source that must meet the electrical/timing
requirements in the Electrical Characteristics table. The RTC oscillator does not require external load capacitors.
The RTC calibration feature provides the ability for user software to compensate for minor variations in the RTC oscillator,
crystal, temperature, and board layout. Enabling the SQWOUT alternate function outputs a timing signal derived from the
RTC. External hardware can measure the frequency and adjust the RTC frequency in increments of ±127ppm with 1ppm
resolution. Under most circumstances, the oscillator does not require any calibration.

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Programmable Timers
32-Bit Timer/Counter/PWM (TMR, LPTMR)
General-purpose, 32-bit timers provide timing, capture/compare, or generation of pulse-width modulated (PWM) signals
with minimal software interaction.
The timer provides the following features:
● 32-bit up/down autoreload
● Programmable prescaler
● PWM output generation
● Capture, compare, and capture/compare capability
● External pin multiplexed with GPIO for timer input, clock gating, or capture
● Timer output pin
● TMR0–TMR3 can be configured as two 16-bit general-purpose timers
● Timer interrupt
The instances and characteristics of the peripheral are shown in Table 5. Some instances and I/O functionality may not
be available in every package configuration; see the Ordering Information table for the specific instances available by
part number.
Table 5. MAX32655 Timer Instances
REGISTER DUAL CLOCK SOURCE
SINGLE SINGLE POWER
INSTANCE ACCESS 16 LPTMR0 LPTMR1
32 BIT 16 BIT MODE PCLK ISO IBRO INRO ERTCO
NAME BIT _CLK _CLK
ACTIVE,
TMR0 TMR0 Yes Yes No SLEEP, Yes Yes Yes No Yes No No
LPM
ACTIVE,
TMR1 TMR1 Yes Yes No SLEEP, Yes Yes Yes No Yes No No
LPM
ACTIVE,
TMR2 TMR2 Yes Yes No SLEEP, Yes Yes Yes No Yes No No
LPM
ACTIVE,
TMR3 TMR3 Yes Yes No SLEEP, Yes Yes Yes No Yes No No
LPM
ACTIVE,
SLEEP,
LPTMR0 TMR4 No No Yes No No Yes Yes Yes Yes No
LPM,
UPM
ACTIVE,
SLEEP,
LPTMR1* TMR5 No No Yes No No Yes Yes Yes No Yes
LPM,
UPM
* Available as an internal timer only on the 51-bump WLP. There is no external connection to this timer on the 51-bump
WLP.

Watchdog Timer (WDT)

Microcontrollers are often used in harsh environments where electrical noise and electromagnetic interference (EMI) are
abundant. Without proper safeguards, these hazards can disturb device operation and corrupt program execution. One
of the most effective countermeasures is the WDT, which detects runaway code or system unresponsiveness.
The WDT is a 32-bit, free-running counter with a configurable prescaler. When enabled, the WDT must be periodically
reset by the application software. Failure to reset the WDT within the user-configurable timeout period indicates that the

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application software is not operating correctly and results in a WDT timeout. A WDT timeout can trigger an interrupt,
system reset, or both. Either response forces the instruction pointer to a known good location before resuming instruction
execution.
The windowed timeout period feature provides more detailed monitoring of system operation, requiring the WDT to be
reset within a specific window of time.
The instances and characteristics of the peripheral are shown in Table 6. Some instances may not be available in every
package configuration; see the Ordering Information table for the specific instances available by part number.
Table 6. MAX32655 Watchdog Timer Instances
CLOCK SOURCE
INSTANCE NAME REGISTER ACCESS NAME POWER MODE
PCLK IBRO INRO ERTCO
ACTIVE,
WDT0 WDT0 SLEEP, Yes Yes No No
LPM
ACTIVE,
SLEEP,
LPWDT0 WDT1 No Yes Yes Yes
LPM,
UPM

Pulse Train Engine (PT)

Multiple, independently-configurable pulse train generators can provide pulse-width modulation, a square wave, or a
repeating pattern from 2 to 32 bits. Any single pulse train generator or desired group of pulse train generators can be
synchronized at the bit level, allowing for multi-bit patterns.
The pulse train generators provide the following features:
● Independently enabled
● Safe enable and disable for pulse trains without bit banding
● Multiple pin configurations allow for a flexible layout
● Pulse trains can be started/synchronized independently or as a group
● Frequency of each enabled pulse train generator is also set separately, based on a divide down (divide by 2, divide
by 4, divide by 8, and so on) of the input pulse train module clock
● Input pulse train module clock can be optionally configured to be independent of the system AHB clock
● Multiple repetition options
• Single shot (nonrepeating pattern of 2 to 32 bits)
• Pattern repeats a user-configurable number of times or indefinitely
• Termination of one pulse train loop count can restart one or more other pulse trains
The instances and characteristics of the peripheral are shown in Table 7. Some instances may not be available in every
package configuration; see the Ordering Information table for the specific instances available by part number.
Table 7. MAX32655 Pulse Train Instances
PACKAGES
INSTANCE
81 CTBGA 51 WLP
Yes No PT0
Yes No PT1
Yes No PT2
Yes No PT3

Serial Peripherals
I2C Interface (I2C)
The I2C interface is a bidirectional, two-wire serial bus that provides a medium-speed communications network. It can

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operate as a one-to-one, one-to-many, or many-to-many communication medium. This interface supports Standard-
mode, Fast-mode, and Fast-mode Plus I2C speeds. It provides the following features:
● Controller or target mode operation
• Supports up to four different target addresses in target mode
● Supports standard 7-bit addressing or 10-bit addressing
● RESTART condition
● Interactive receive mode (IRXM)
● Transmitter FIFO preloading
● Support for clock stretching to allow slower target devices to operate on higher speed busses
● Multiple transfer rates
• Standard-mode: 100kbps
• Fast-mode: 400kbps
• Fast-mode Plus: 1000kbps
● Internal filter to reject noise spikes
● Receiver FIFO depth of 8 bytes
● Transmitter FIFO depth of 8 bytes
The instances and characteristics of the peripheral are shown in Table 8. Some instances may not be available in every
package configuration; see the Ordering Information table for the specific instances available by part number.
Table 8. MAX32655 I2C Instances
PACKAGES
81 CTBGA 51 WLP
I2C0
I2C1 I2C0
I2C2

I2S Interface (I2S)

The I2S interface is a bidirectional, four-wire serial bus that provides serial communications for codecs and audio
amplifiers compliant with the I2S Bus Specification, June 5, 1996. It provides the following features:
● Controller and target mode operation
● Selectable bits per word from 1 to 32
● Receive and transmit DMA support
● Word-select polarity control
● First bit position selection
● Interrupts generated for FIFO status
● Receiver FIFO depth of 32 bytes
● Transmitter FIFO depth of 32 bytes
This peripheral may not be available in every package configuration; see the Ordering Information table for the specific
instances available by part number.

Serial Peripheral Interface (SPI)

The SPI is a highly configurable, flexible, and efficient synchronous interface where multiple SPI devices can coexist on
a single bus. The bus uses a single clock signal, multiple data signals, and one or more target select lines to address
only the intended target device. The SPI operates independently and requires minimal processor overhead.
The provided SPI peripherals can operate in either target or controller mode and provide the following features:
● SPI modes 0, 1, 2, or 3 for single-bit communication
● 3- or 4-wire mode for single-bit target device communication
● Full-duplex operation in single-bit, 4-wire mode
● Dual and quad data modes supported
● Multiple target selects on some instances
● Multicontroller mode fault detection

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● Programmable interface timing

● Programmable SCK frequency and duty cycle
● 32-byte transmit and receive FIFOs
● Target select assertion and deassertion timing concerning leading/trailing SCK edge
The instances and characteristics of the peripheral are shown in Table 9. Some instances may not be available in every
package configuration; see the Ordering Information table for the specific instances available by part number.

Table 9. MAX32655 SPI Instances

PACKAGE TARGET
MAXIMUM FREQUENCY MAXIMUM FREQUENCY
INSTANCE FORMATS SELECT
81 51 CONTROLLER MODE (MHz) TARGET MODE (MHz)
LINES
CTBGA WLP

3-wire 50 (Mode 0 and Mode 2) 50 (Mode 0 and Mode 2)

Yes — SPI0 3
4-wire 25 (Mode 1 and Mode 3) 25 (Mode 1 and Mode 3)
dual
Yes — SPI1 quad 1 25 (All SPI modes) 25 (All SPI modes)

50 (Mode 0 and Mode 2) 50 (Mode 0 and Mode 2)

— Yes SPI0 3-wire 3
25 (Mode 1 and Mode 3) 25 (Mode 1 and Mode 3)
4-wire
— Yes SPI1 dual 2 25 (All SPI modes) 25 (All SPI modes)

UART (UART, LPUART)

The universal asynchronous receiver-transmitter (UART, LPUART) interface supports full-duplex asynchronous
communication with optional hardware flow control (HFC) modes to prevent data overruns. If HFC mode is enabled on a
given port, the system uses two extra pins to implement the industry-standard request to send (RTS) and clear to send
(CTS) flow control signaling. Each instance is individually programmable.
● 2-wire interface or 4-wire interface with flow control
● 8-byte send/receive FIFO
● Full-duplex operation for asynchronous data transfers
● Interrupts available for frame error, parity error, CTS, Rx FIFO overrun, and FIFO full/partially full conditions
● Automatic parity and frame error detection
● Independent baud-rate generator
● Programmable 9th-bit parity support
● Multidrop support
● Start/stop bit support
● Hardware flow control using RTS/CTS
● Two DMA channels can be connected (read and write FIFOs)
● Programmable word size (5 bits to 8 bits)
The instances and characteristics of the peripheral are shown in Table 10. Some instances may not be available in every
package configuration; see the Ordering Information table for the specific instances available by part number.
Table 10. MAX32655 UART Instances
PACKAGE INSTANCE REGISTER ACCESS HARDWARE FLOW CLOCK SOURCE
POWER MODE
81 CTBGA 51 WLP NAME NAME CONTROL PCLK IBRO ERTCO
ACTIVE,
Yes Yes UART0 UART0 Yes SLEEP, Yes Yes No
LPM
ACTIVE,
Yes No UART1 UART1 Yes SLEEP, Yes Yes No
LPM

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Table 10. MAX32655 UART Instances (continued)

PACKAGE INSTANCE REGISTER ACCESS HARDWARE FLOW CLOCK SOURCE
POWER MODE
81 CTBGA 51 WLP NAME NAME CONTROL PCLK IBRO ERTCO
ACTIVE,
Yes No UART2 UART2 81 CTBGA only SLEEP, Yes Yes No
LPM
ACTIVE,
SLEEP, No Yes Yes
Yes Yes LPUART0 UART3 No LPM
UPM No No Yes

1-Wire Controller (OWM)

Analog Devices' 1-Wire bus consists of one signal that carries data and also supplies power to the target devices and
a ground return. The bus controller communicates serially with one or more target devices through the bidirectional,
multidrop 1-Wire bus. The single-contact serial interface is ideal for communication networks requiring minimal
interconnection.
The provided 1-Wire controller supports the following features:
● Single contact for control and operation
● Unique factory identifier for any 1-Wire device
● Multiple device capability on a single line
The OWM supports both standard (15.6kbps) and overdrive (110kbps) speeds.

Standard DMA Controller

The standard DMA controller allows automatic one-way data transfer between two entities. These entities can be
either memories or peripherals. The transfers are done without using CPU resources. The following transfer modes are
supported:
● 4-channel
● Peripheral to data memory
● Data memory to peripheral
● Data memory to data memory
● Event support
All DMA transactions consist of an AHB burst read into the DMA FIFO, followed immediately by an AHB burst write from
the FIFO.
The MAX32655 provides one instance of the standard DMA controller.

Security
AES
The dedicated hardware-based AES engine supports the following algorithms:
● AES-128
● AES-192
● AES-256
The AES keys are automatically generated by the engine and stored in dedicated flash to protect against tampering. Key
generation and storage is transparent to the user.

True Random Number Generator (TRNG)

The device provides a non-deterministic entropy source that can be used to generate cryptographic seeds or strong
encryption keys as part of an overall framework for a secure customer application.
Software can use random numbers to trigger asynchronous events that add complexity to program execution to thwart

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replay attacks or key search methodologies.

CRC Module
A cyclic redundancy check (CRC) hardware module provides fast calculations and data integrity checks by application
software. It supports a user-defined programmable polynomial up to 32-bits. Direct memory access copies data into
the CRC module so that CRC calculations on large blocks of memory are performed with minimal CPU intervention.
Examples of common polynomials are depicted in Table 11.
Table 11. Common CRC Polynomials
ALGORITHM POLYNOMIAL EXPRESSION
CRC-32-ETHERNET x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + x0
CRC-CCITT x16 + x12 + x5 + x0
CRC-16 x16 + x15 + x2 + x0
USB DATA x16 + x15 + x2 + x0
PARITY x1 + x0

Secure Communications Protocol Bootloader (SCPBL)

The MAX32655 does not support an SCPBL. The user must use SWD to load software for execution.

Secure Boot
On devices that support Secure Boot, the device performs a secure boot to confirm that the root of trust has not been
compromised. Following every reset and exit from certain low-power modes, the secure boot verifies the digital signature
of the program memory to confirm it has not been modified or corrupted, ensuring the trustworthiness of the application
software. Failure to verify the digital signature transitions the device to safe mode, which prevents execution of the
customer code. During the development phase, the bootloader can be reactivated and a new, trusted program memory
loaded. Refer to the MAX32655 User Guide for more details.

Debug and Development Interface (SWD, JTAG)

The serial wire debug (SWD) interface is used for debugging the CM4 and loading software for both the CM4 and the
RV32. The JTAG interface is provided for debugging the RV32. All devices in mass production have the debugging/
development interface enabled.

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
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Applications Information
Bypass Capacitors
The proper use of bypass capacitors reduces noise generated by the IC into the ground plane. The Pin Descriptions table
indicates which pins should be connected to bypass capacitors, and the appropriate ground plane.
It is recommended that one instance of a bypass capacitor should be connected to each pin/ball of the IC package. For
example, if the Pin Descriptions table shows four device pins associated with voltage supply A, a separate capacitor
should be connected to each pin for a total of four capacitors.
Capacitors should be placed as close as possible to their corresponding device pins. Pins which recommend more than
one value of capacitor per pin should place them in parallel with the lowest value capacitor first, closest to the pin.

RTC Crystal Guidelines

The internal low-power RTC oscillator minimizes power consumption and maximizes battery life. The RTC crystal must
be designed to reach its nominal frequency with 6pF (called CL or CL_XTAL in the Electrical Characteristics table) of
load capacitance. Crystals designed for values of CL_XTAL greater than 6pF are not supported. Note that crystal load
capacitors are electrically in series across the crystal, so the correct value of total pad and trace capacitance for a "6pF
crystal" is 12pF per terminal. The RTC in this part includes integrated load capacitors. External load capacitors are not
required for RTC operation.
A digital trim feature can compensate for RTC inaccuracies of up to ±127ppm when compared against an external
reference clock. Refer to the MAX32655 User Guide for details.
Although they are not required, customers can also tune the clock using external load capacitors. Final C values must be
determined after the PCB layout is complete. However, the low-power design of the RTC oscillator imposes a maximum
of 12pF (CPAD + CSTRAY + CL_XTAL) total per pin.

Device PCB Power Connectivity

The Table 12 depicts the power supply device pin connections for any design to be made at the PCB level. No external
components can be connected to the VREGO_X regulator outputs. Doing so will cause excessive loading during low-
power operating modes, leading to possible device resets. An external 1.8V supply must bias external components
operating at the VDDIO voltage.
Table 12. Device PCB Power Connectivity
DEVICE PIN CONNECTION
VREGI Battery
VDDA VREGO_A
VDDIO VREGO_A
VDDIOH VREGI
BLE_LDO_IN VREGO_D
VCOREA VREGO_C
VCOREB VREGO_B
VBST LXB through a 3.3nF capacitor
LXA LXB through a 2.2μH inductor

VREGI Design Considerations

The internal SIMO regulator requires one minimum 22µF capacitor between VREGI and VSSPWR. Larger capacitance
values improve decoupling for the SIMO regulator and reduce current peaks drawn from the battery.
Place the capacitor as close as possible to the pin shown in Table 13. The ESR/ESL of the input capacitor should be
very low (i.e., ≤ 5mΩ + ≤ 500pH) for frequencies up to 2MHz. Ceramic capacitors with X5R or X7R dielectric are highly
recommended due to their small size, low ESR, and small temperature coefficients.

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
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Table 13. MAX32655 VREGI Capacitor Placement Priority

PACKAGE PLACEMENT
81 CTBGA C9
51 WLP H4
Proper operation requires low inductance routing and minimization of the loop area between VREGI, the capacitor, and
the VSSPWR ground plane.

Transmitted Spurious Emissions

Various local regulatory agencies can impose limits on transmitted spurious emissions. At maximum output power of
+5.5dbm, compliance with local regulations can require either an antenna with at least 6dB rejection at the 7.2GHz third
harmonic or the use of a lowpass filter network between the device RF port and antenna. The MAX32655 is designed with
an on-chip matching network providing a 50Ω impedance at the ANT device pin. Filter design must match this impedance
for best efficiency.

Typical Fixed Current Consumption Temperature Variance

ACTIVE Mode
Table 14. Fixed VREGI Current Consumption ACTIVE Mode
TYPICAL
PARAMETER SYMBOL CONDITIONS UNITS
-40°C 25°C 55°C 85°C 105°C
Fixed, IPO enabled, ISO disabled, total current into
VREGI
VREGI pin, VREGI = 3.0V, VCOREA = 1.0V, VCOREB
Current,
IREGI_FACT = 0.81V; CM4 in ACTIVE mode 0MHz, RV32 in 506 570 659 840 1103 μA
ACTIVE
ACTIVE mode 0MHz; ECC disabled; inputs tied to
Mode
VSS or VDDIO, or VDDIOH; outputs source/sink 0mA

SLEEP Mode
Table 15. Fixed VREGI Current Consumption SLEEP Mode
TYPICAL
PARAMETER SYMBOL CONDITIONS UNITS
-40°C 25°C 55°C 85°C 105°C
Fixed, IPO enabled, ISO disabled, total current into
VREGI VREGI pin, VREGI = 3.0V; VCOREA = 1.0V, VCOREB
Current, IREGI_FSLP = 0.81V, CM4 and RV32 in SLEEP mode 0MHz 506 570 659 840 1103 μA
SLEEP Mode operation; ECC disabled; inputs tied to VSS, VDDIO
or VDDIOH; outputs source/sink 0mA

STANDBY Mode
Table 16. Fixed VREGI Current Consumption STANDBY Mode
TYPICAL
PARAMETER SYMBOL CONDITIONS UNITS
-40°C 25°C 55°C 85°C 105°C
VREGI
Fixed, total current into VREGI pin, VREGI = 3.0V,
Current,
IREGI_STBY VCOREA = 1.0V, VCOREB = 0.81V; inputs tied to VSS 1.2 2.1 4.6 12 25 μA
STANDBY
or VDDIO, or VDDIOH; outputs source/sink 0mA
Mode

BACKUP Mode
Table 17. Fixed VREGI Current Consumption BACKUP Mode
PARAMETER SYMBOL CONDITIONS TYPICAL UNITS

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
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Table 17. Fixed VREGI Current Consumption BACKUP Mode (continued)

-40°C 25°C 55°C 85°C 105°C
Fixed, total current into VREGI pin, VREGI = 3.0V,
VCOREA = 1.0V, VCOREB = 0.81V; RTC disabled;
0.96 1.6 3.4 9.1 19.3
VREGI inputs tied to VSS or VDDIO, or VDDIOH; outputs
Current, source/sink 0mA. All SRAM retained.
IREGI_BK μA
BACKUP Fixed, total current into VREGI pin, VREGI = 3.0V,
Mode VCOREA = 1.0V, VCOREB = 0.81V; RTC disabled;
0.88 0.98 1.6 5 10.7
inputs tied to VSS or VDDIO, or VDDIOH; outputs
source/sink 0mA; No SRAM retained.

Ordering Information
OPTIONALLY
EXT. ADC
PULSE LPUART ENABLED PIN-
PART UART SPI I²C INPUTS/ I²S GPIO
TRAINS SECURE PACKAGE
COMPARATORS
BOOT
81 CTBGA
8mm x
2x
MAX32655GXG+ 4 3 4 8/4 1 1 52 Yes 8mm,
quad
0.8mm
pitch
81 CTBGA
8mm x
2x
MAX32655GXG+T 4 3 4 8/4 1 1 52 Yes 8mm,
quad
0.8mm
pitch
51 WLP
3.09mm x
2x
MAX32655GWJ+ 1 1 0 4/2 1 0 23 Yes 3.09mm,
dual
0.35mm
pitch
51 WLP
3.09mm x
2x
MAX32655GWJ+T 1 1 0 4/2 1 0 23 Yes 3.09mm,
dual
0.35mm
pitch
All packages contain one RTC, CRC, OWM, TRNG, I²S, two WDT, and Bluetooth 5.2;
UART = Universal Asynchronous Receiver-Transmitter; SPI = Serial Peripheral Interface;
TMR = Timer; I²C = Inter-IC; ADC = Analog-to-Digital Converter; LPUART = Low-Power UART;
I²S = Inter-IC Sound; GPIO = General-Purpose Input/Output; RTC = Real-Time Clock;
CRC = Cyclic Redundancy Check; OWM = 1-Wire Controller; TRNG = True Random Number Generator
+ Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel. Full reel.

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MAX32655 Low-Power, Arm Cortex-M4 Processor with
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Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 8/20 Release for intro —
Added 63 WLP Pin Configuration, Pin Descriptions, and Package Information. 1, 7, 11, 32–36,
1 9/21
Updated the Electrical Characteristics and Ordering Information. 41, 52
Removed 63 WLP package and replaced with 60 WLP in Pin Configuration, Pin
Descriptions, Package Information, General Description, and Detailed Description. 1, 7, 32–36, 38,
2 11/21
Updated Ordering information to reflect package change to MAX32655GWY+ and 41, 42, 46–49, 52
MAX32655GWY+T.
Added guidelines for RTC crystal, clarified RSTN causes a system reset, removed
the requirement for 32KIN/32KOUT capacitors. Removed 60 WLP package
information. Replaced all references to Master/Slave with Controller/Target. Updated
1, 2, 7–13,
the Simplified Block Diagram. Updated Electrical Characteristics for revision B
3 11/23 16–18, 20–24,
silicon. Updated Pin Description for 81 CTBGA package. Updated the Clocking
29–51
Scheme Diagram for 81 CTBGA package. Removed description of the Dynamic
Voltage Scaling. Removed support for High-Speed I2C. Updated Detailed
Description. Updated Ordering Information.
1, 7–9, 35–40,
4 1/24 Added 51 WLP package information. 41, 42, 44, 45,
49–57

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