CMOS DIGITAL VLSI DESIGN
Logical Efforts- I
SUDEB DASGUPTA
DEPARMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
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Outline
• Introduction
• Basics of Logical effort
• Calculation of Logical Efforts for Logic Gates
• Multi Stage Logic Network
• Recapitulation
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Introduction
Designing a circuit to achieve the greatest speed or to meet a delay
constraint presents a bewildering array of choices.
How large should a logic gate’s transistors be to achieve least delay?
How many stages of logic should be used to obtain least delay?
The method of logical effort is an easy way to minimize the delay in
a Logic circuit. By comparing delay estimates of different logic
structures, the fastest candidate can be selected or designed.
Logical Effort also specifies the best no stages a logic path and the
respective transistor sizes for the given load.
Logical Effort: Designing Fast CMOS Circuits Ivan E. Sutherland Bob F. Sproull David L. Harris
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Basics of Logical Effort
Logical Effort: Designing Fast CMOS Circuits Ivan E. Sutherland Bob F. Sproull David L. Harris
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Basics of Logical Effort Continue
Effort delay or
stage effort
Logical Effort: Designing Fast CMOS Circuits Ivan E. Sutherland Bob F. Sproull David L. Harris
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• The logical effort of a logic gate tells how much worse it is at
producing output current than is an inverter, given that each of its
inputs may contain only the same input capacitance as the inverter.
Delay of the logic gate increases with electrical 2-input
NAND Inverter
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effort. g = 4/3
NormalizedDelay:d
5 p=2
More complex logic gates have more logical 4 g=1
p=1
d = (4/3)h + 2
effort and parasitic delay. 3
2
d = h +1
EffortDelay:f
• Plots in the figure shows delay equation for 1
Parasitic Delay: p
0
an inverter and a two-input NAND gate. 0 1 2 3 4 5
ElectricalEffort:
h = Cout / Cin
Logical Effort: Designing Fast CMOS Circuits Ivan E. Sutherland Bob F. Sproull David L. Harris
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Inverter’s Logical Effort VDD
PMOS
In Out
NMOS
delay
Logical Effort: Designing Fast CMOS Circuits Ivan E. Sutherland Bob F. Sproull David L. Harris
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Logical effort calculation
Logical Effort: Designing Fast CMOS Circuits Ivan E. Sutherland Bob F. Sproull David L. Harris
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Logical effort & Parasitic delay of common Gates
No of Inputs Parasitic
Where n in
Logic Gate 1 2 3 n Delay
parasitic delay
Is no. of Inputs
Inverter 1 - - -
NAND - 4/3 5/3 (n+2)/3
NOR - 5/3 7/3 (2n+1)/3
XOR(parity) - 4 12
Multiplexer - 2 2 2
Logical Effort: Designing Fast CMOS Circuits Ivan E. Sutherland Bob F. Sproull David L. Harris
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EXAMPLE 1 Fan-out 4 (FO4) Inverter Delay
Calculate the delay for FO4 Inverter.
Logical Effort: Designing Fast CMOS Circuits Ivan E. Sutherland Bob F. Sproull David L. Harris
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EXAMPLE 2 Delay for 4 Input NOR Logic Gate
Calculate the delay for 4 input NOR gate which drives
10, 4 Input NOR gates?
Logical Effort: Designing Fast CMOS Circuits Ivan E. Sutherland Bob F. Sproull David L. Harris
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Logical Efforts Multi Stage Logic Networks
Source:Logical Effort: Designing Fast CMOS Circuits Ivan E. Sutherland Bob F. Sproull David L. Harris
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Source:Logical Effort: Designing Fast CMOS Circuits Ivan E. Sutherland Bob F. Sproull David L. Harris
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Recapitulation
Term Stage Path
Number of stages 1 N
Logical effort g G gi
Electrical effort h Cout
Cin H
Cout-path
Cin-path
Branching effort b
Con-path Coff-path
off-path
Con-path
B bi
Effort f gh F GBH
Effort delay f DF fi
Parasitic delay p P pi
Delay d= f+p D di DF P
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