EDC - FET

Field Effect Transistor (FET) .PART 1:.

 Is a 3 – terminal Unipolar electronic device. JFET , D – type MOSFET ,.
 is a type of transistor that controls the flow of current by
modula�ng an electric field within the channel. D – type MESFET.
This electric field is influenced by the input voltage applied to  These 3 types of transistors have a built-in Conduc�ve
the gate terminal and other factors like the inherent Channel, that’s why it is a Normally – Close (ON - switch)
doping of the channel and temperature. device and shares the same characteris�cs and Formulas.
 One of the most important characteris�cs of the FET is its
High input impedance. 𝐽𝐽 → 𝐽𝐽𝐽𝐽𝐽𝐽𝐽𝐽𝐽𝐽𝐽𝐽𝐽𝐽𝐽𝐽
 more sensi�ve (sta�c) than BJTs. 𝐷𝐷 → 𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷
𝑀𝑀𝑀𝑀𝑀𝑀 → 𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀 − 𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂 𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆
𝑀𝑀𝑀𝑀𝑀𝑀 → 𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀 – Semiconductor

Junc�on – FET
JFET construc�on

Features BJT FET

Opera�on In – Out In – Out
CC – CS VC – CS
Type of Amplifier Current Amplifier Transconductance
(𝐴𝐴𝑖𝑖 ) Amplifier (𝐴𝐴𝐺𝐺 )
Gain More Less
Heat Stability Not Stable Stable
Power Dissipa�on More Less
Switching Time slow Fast
Size Bigger Smaller
Cost Cheap Bit Expensive
Applica�on Analog Digital
1. Amplifier 1. Switch

FET Classifica�on N – Channel – N  Tering

How JFET Works?

1. Normally Close (ON – switch)
2. Voltage – Controlled Current Source (VCSS)
3. Constant Current Source
4. Act as a Voltage – Controlled Variable Resistor/Capacitor

𝑫𝑫 – 𝒎𝒎𝒎𝒎𝒎𝒎𝒎𝒎 𝑬𝑬 – 𝒎𝒎𝒎𝒎𝒎𝒎𝒎𝒎
𝑉𝑉𝐷𝐷𝐷𝐷 𝑉𝑉𝑝𝑝 𝑉𝑉𝐺𝐺𝐺𝐺 𝑉𝑉𝐺𝐺𝐺𝐺
𝑛𝑛 – 𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡 + − − +
𝑝𝑝 – 𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡 − + + −
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BJT:
• Deple�on Region decreases when Forward Bias.
• Deple�on Region increases when Reverse Bias.

JFET:
• Deple�on Region is minimum when 𝑽𝑽𝑮𝑮𝑮𝑮 = 𝟎𝟎 𝑎𝑎𝑎𝑎𝑎𝑎 𝑽𝑽𝑫𝑫𝑫𝑫 > |𝑽𝑽𝑷𝑷 |.
• Deple�on Region increases when 𝑽𝑽𝑫𝑫𝑫𝑫 increases.
• Deple�on Region increases when 𝑽𝑽𝑮𝑮𝑮𝑮 Reverse Bias.

1
𝑅𝑅𝑅𝑅 ∝ 𝐷𝐷𝐷𝐷 ∝
𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 𝐶𝐶ℎ𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎

𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷

NORMALLY – CLOSE (ON - switch)

Drain to Source Satura�on Current (𝑰𝑰𝑫𝑫𝑫𝑫𝑫𝑫 ) is the maximum drain

current for a JFET and is defined by the condi�ons Transfer Characteris�cs
𝑽𝑽𝑮𝑮𝑮𝑮 = 𝟎𝟎 𝑎𝑎𝑎𝑎𝑎𝑎 𝑽𝑽𝑫𝑫𝑫𝑫 > |𝑽𝑽𝑷𝑷 |.

Deple�on Region and Pinch – Off Voltage

�𝑽𝑽𝒑𝒑 � = 𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡 5𝑉𝑉

𝑤𝑤ℎ𝑒𝑒𝑒𝑒 𝑽𝑽𝑮𝑮𝑮𝑮 = 𝟎𝟎 𝒂𝒂𝒂𝒂𝒂𝒂 𝑽𝑽𝑫𝑫𝑫𝑫 > |𝑽𝑽𝑷𝑷 | , 𝑰𝑰𝑫𝑫 = 𝑰𝑰𝑫𝑫𝑫𝑫𝑫𝑫 → 𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺

𝑤𝑤ℎ𝑒𝑒𝑒𝑒 𝑽𝑽𝑮𝑮𝑮𝑮 = 𝑽𝑽𝑷𝑷 𝒂𝒂𝒂𝒂𝒂𝒂 𝑽𝑽𝑫𝑫𝑫𝑫 < |𝑽𝑽𝑷𝑷 | , 𝑰𝑰𝑫𝑫 = 𝟎𝟎 → 𝑷𝑷𝑷𝑷𝑷𝑷𝑷𝑷𝑷𝑷 − 𝒐𝒐𝒐𝒐𝒐𝒐

The term pinch-off at 𝑽𝑽𝑽𝑽𝑽𝑽 = |𝑽𝑽𝑽𝑽| is a misnomer, it suggests the

current 𝐼𝐼𝐷𝐷 is pinched off and drops to 𝟎𝟎𝟎𝟎. In reality a very small
channel s�ll exists, with a current of very high density, 𝑰𝑰𝑫𝑫 maintains
a satura�on level defined as 𝑰𝑰𝑫𝑫𝑫𝑫𝑫𝑫..
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Formulas: AC Equivalent Circuit

Input Impedance
 input terminals approximate an open circuit.

𝒁𝒁𝒊𝒊 → ∞
Output / Drain Impedance

Acts as a Voltage – Controlled Variable Resistor

∆𝑉𝑉𝐷𝐷𝐷𝐷 𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷
𝑍𝑍𝑜𝑜 = 𝑟𝑟𝑑𝑑 = = ∙ 𝑟𝑟
∆𝐼𝐼𝐷𝐷 𝐼𝐼𝐷𝐷 0
VC – CS CC – CS Where: 𝒓𝒓𝒅𝒅 is the output/drain resistance
𝒓𝒓𝟎𝟎 is the resistance with 𝑽𝑽𝑮𝑮𝑮𝑮 = 𝟎𝟎𝟎𝟎

Forward Transconductance

∆𝐼𝐼𝐷𝐷
𝑔𝑔𝑚𝑚 = 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 (𝑚𝑚) =
∆𝑉𝑉𝐺𝐺𝐺𝐺

𝑉𝑉𝐺𝐺𝐺𝐺
𝑔𝑔𝑚𝑚 = 𝑔𝑔𝑚𝑚(0) �1 − �
𝑉𝑉𝑝𝑝

2𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷
𝑔𝑔𝑚𝑚(0) = → max 𝑔𝑔𝑚𝑚 @ 𝑉𝑉𝐺𝐺𝐺𝐺 = 0
�𝑉𝑉𝑝𝑝 �

Power Dissipa�on

𝑷𝑷𝑫𝑫 = 𝑽𝑽𝑫𝑫𝑫𝑫 𝑰𝑰𝑫𝑫 → @ 𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇. (25℃)

𝑚𝑚𝑚𝑚
5 → 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴 𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇. (25℃)
℃
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MOSFET MESFET
 Metal – Oxide Semiconductor FET  Metal – Semiconductor FET
MOSFETs come in two main channel types:
Opera�on:
Deple�on – Type: • Uses a metal gate directly deposited on the semiconductor
 These have a pre-exis�ng conduc�ve channel built into the surface. This metal forms a Schotky barrier junc�on with the
semiconductor structure. This channel conducts current even n-type or p-type channel beneath.
when no voltage is applied to the gate terminal. However, • Forward Bias  decreases the Schotky barrier
applying a specific voltage to the gate can deplete the channel height, allowing more current to flow through the channel.
and reduce current flow, hence the name "deple�on mode." • Reverse Bias  increases the Schotky barrier
 Have 2 modes: D-mode and E-mode, where D-mode is the height, restric�ng current flow and effec�vely turning off the
primary mode. MESFET.
Key characteris�cs:
• High-frequency performance: Lower gate capacitance
compared to JFETs makes them suitable for high-speed
applica�ons.
• Smaller size and easier integra�on: Compact structure offers
advantages in circuit design.
• Sensi�ve to temperature and leakage current: More
suscep�ble to environmental varia�ons and internal power
loss.

Deple�on-type and enhancement-type MESFETs are made with an

Enhancement – Type: n-channel between the drain and the source, and therefore
 These do not have a pre-exis�ng conduc�ve channel. only n-type MESFETs are commercially available.
Applying a specific voltage to the gate terminal is necessary to
create a conduc�ve channel and allow current to flow.
This voltage is called the threshold voltage (𝑽𝑽𝑻𝑻𝑻𝑻 ).
Once 𝑽𝑽𝑻𝑻𝑻𝑻 is reached or exceeded, the channel conduc�vity
starts to increase, hence the name "enhancement mode."
 Enhancement-mode only

.PART 2:.
.E – MOSFET , E – MESFET.
 These types of transistors do not have a built-in conduc�ve
channel, that’s why it is a Normally – Open (OFF - switch)
Both deple�on- and enhancement-type MOSFETs have device and shares the same characteris�cs and Formulas.
enhancement-type regions, but the label was applied to the later
2
since it is its only Enhancement-mode of opera�on. 𝐼𝐼𝐷𝐷 = 𝑘𝑘�𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝐺𝐺𝐺𝐺(𝑇𝑇ℎ)�

𝑔𝑔𝑚𝑚 = �2𝑘𝑘�𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝐺𝐺𝐺𝐺(𝑇𝑇ℎ) ��

𝐼𝐼𝐷𝐷(𝑜𝑜𝑜𝑜)
𝑘𝑘 = 2
�𝑉𝑉𝐺𝐺𝐺𝐺(𝑜𝑜𝑜𝑜) − 𝑉𝑉𝐺𝐺𝐺𝐺(𝑇𝑇ℎ)�

𝒎𝒎𝒎𝒎
𝑖𝑖𝑖𝑖 𝑘𝑘 𝑖𝑖𝑖𝑖 𝑛𝑛𝑛𝑛𝑛𝑛 𝑔𝑔𝑔𝑔𝑔𝑔𝑔𝑔𝑔𝑔, 𝒌𝒌 = 𝟎𝟎. 𝟑𝟑
𝑽𝑽𝟐𝟐
D – for soliD
N – Channel – N  Tering
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D – mode E – mode
Region Region
𝑰𝑰𝑫𝑫 ≤ 𝑰𝑰𝑫𝑫𝑫𝑫𝑫𝑫 𝑰𝑰𝑫𝑫 > 𝑰𝑰𝑫𝑫𝑫𝑫𝑫𝑫
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.AMPLIFIERS.
 is a circuit that uses an external power supply to generate an
output signal that is larger replica of its input.

𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 𝑄𝑄 − 𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃 𝐸𝐸𝐸𝐸𝐸𝐸𝐸𝐸𝐸𝐸𝐸𝐸𝐸𝐸𝐸𝐸𝐸𝐸𝐸𝐸𝐸𝐸 (𝜂𝜂)

𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴 (𝜃𝜃)

𝐴𝐴 𝜃𝜃 = 360° Above the cut- 25 − 50%

off point

𝐴𝐴𝐴𝐴 𝜃𝜃 > 180° Slightly above 50 − 60%

the cut-off
point

𝐵𝐵 𝜃𝜃 = 180° At the cut-off 78.5%

point

𝐶𝐶 𝜃𝜃 < 180° Below the cut- 80 − 90%

off point

𝐷𝐷 → 𝑇𝑇 𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 90% +

Class A amplifier Efficiency

2
𝑉𝑉𝐶𝐶𝐶𝐶(𝑚𝑚𝑚𝑚𝑚𝑚) − 𝑉𝑉𝐶𝐶𝐶𝐶(𝑚𝑚𝑚𝑚𝑚𝑚)
𝜂𝜂 = � � × 𝜂𝜂𝑚𝑚𝑚𝑚𝑚𝑚
𝑉𝑉𝐶𝐶𝐶𝐶(𝑚𝑚𝑚𝑚𝑚𝑚) + 𝑉𝑉𝐶𝐶𝐶𝐶(𝑚𝑚𝑚𝑚𝑚𝑚)