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intel.
MCS®-51 PROGRAMMER’S GUIDE AND INSTRUCTION SET
ACALL addrtt
Function:
Description:
Example:
Encoding:
Operation:
INSTRUCTION DEFINITIONS
Absolute Call
ACALL unconditionally calls a subroutine located at the indicated address. The instruction
increments the PC twice to obtain the address of the following instruction, then pushes the
16-bit result onto the stack (low-order byte first) and increments the Stack Pointer twice. The
destination address is obtained by successively concatenating the five high-order bits of the
incremented PC, opoode bits 7-5, and the second byte of the instruction. The subroutine called
‘must therefore start within the same 2K block of the program memory as the first byte of the
instruction following ACALL. No flags are affected.
Initially SP equals 07H. The label “SUBRTN” is at program memory location 0345 H. After
‘executing the instruction,
ACALL SUBRTN
at location 0123H, SP will contain 09H, internal RAM locations 08H and 09H will contain
25H and O1H, respectively, and the PC will contain 034SH.
2
2
aio a9 a8 1 | 0001 a7 a6 a6 a4 | a3 a2 al a0
ACALL
PO) — PO) +2
(SP) <— (SP) + 1
(SP) — PCy)
(SP) — GP) #1
GSP) — Pisa)
@Cio.c) — page address
2:28 intel.
MCS®-51 PROGRAMMER’S GUIDE AND INSTRUCTION SET
AMP. addrt1
Function: Absolute Jump
Description: AJMP transfers program execution to the indicated address, which is formed at run-time by
concatenating the high-order five bits of the PC (after incrementing the PC twice), opcode bits
7-5, and the second byte of the instruction. The destination must therefore be within the same
2K block of program memory as the first byte of the instruction following AJMP.
Example: The label “JMPADR" is at program memory location 0123H. The instruction,
AIMP JMPADR
is st location 0345H and will load the PC with 0123H.
Bytes: 2
Cycles: 2
Encoding: [a10 a9 a8 0 [0001 ‘a7 a6 a5 a4 | a3 a2 at 20
Operation: AJMP
PQ PO) +2
(PCio.0) + page address
ANL ,
Function:
Description:
Example:
Logical-AND for byte variables
ANL performs the bitwise logical-AND operation berween the variables indicated and stores
the results in the destination variable. No flags are affected,
‘The two operands allow six addressing mode combinations. When the destination is the Accu-
mulator, the source can use register, direct, register-indirect, or immediate addressing; when
the destination is a direct address, the source can be the Accumulator or immediate data.
‘Note: When this instruction is used to modify an output port, the value used as the original
Port data will be read from the output data latch, no the input pins.
If the Accumulator holds OC3H (110000118) and register 0 holds 55H (010101018) then the
instruction,
ANL ARO
will leave 41H (010000018) in the Accumulator.
‘When the destination is a directly addressed byte, this instruction will clear combinations of
bits in any RAM location or hardware register. The mask byte determining the pattern of bits
to be cleared would either be a constant contained in the instruction or a value computed in
‘the Accumulator at run-time. The instruction,
ANL P1,#01110011B
will clear bits 7, 3, and 2 of output port 1
2.82 intel. MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
oootporot] | [arectaases
Operation: DEC
(Girect) <— (direct) — I
DEC @Ri
Bytes: 1
Cycles: 1
tnoouns: [Sods [O03
Operation: DEC
@®) — @i) -
DIV AB
Function: Divide
Description: DIV AB divides the unsigned eight-bt integer in the Accumulator by the unsigned eight-bit
integer in register B. The Accumulator receives the integer part of the quotient; register B
receives the integer remainder. The carry and OV flags wil be cleared
Exception: if B had originally contained OOH, the values returned in the Accumulator and B-
register will be undefined and the overflow flag will be set. The carry flag is cleared in any
Example: The Accumulator contains 251 (OFBH or 111110118) and B contains 18 (12H or 000100108).
The instruction,
DIV AB
‘will eave 13 in the Accumulator (ODH or 000011018) and the value 17 (11H or 000100018)
in B, since 251 = (13 X 18) + 17. Carry and OV will both be cleared.
Bytes: 1
cycles: 4
Encoding: [7000] 0100
Operation: DIV
o
Bi wom
2-42 intel.
MCS®-51 PROGRAMMER’S GUIDE AND INSTRUCTION SET
LCALL addrié
Function: Long call
Description: LCALL calls a subroutine located at the indicated address. The instruction adds three to the
rogram counter to generate the address of the next instruction and then pushes the 16-bit
result onto the stack (low byte first) incrementing the Stack Pointer by two. The high-order
and low-order bytes of the PC are then loaded, respectively, with the second and third bytes of
the LCALL instruction. Program execution continues with the instruction at this address. The
subroutine may therefore begin anywhere in the full 64K -byte program memory address space.
No flags are affected.
Example: Initially the Stack Pointer equals OTH. The label “SUBRTN” is assigned to program memory
location 1234H. After executing the instruction,
LCALL SUBRTN
at location 0123H, the Stack Pointer will contain O9H, internal RAM locations OSH and 09H
‘will contain 26H and O1H, and the PC will contain 1234H.
Bytes: 3
Cycles: 2
Encoding: [0001] 0010 addrt5-addr6 ‘addr7-addrO
Operation; = LCALL
PO) PO + 3
SP) — GF) + 1
(GP) — PCr)
SP) — GP) +1
(GSP) — PCs.)
(PC) — addris.o
Lump darts
Function: Long Jump
Description: LIMP causes an unconditional branch to the indicated address, by loading the high-order and
low-order bytes of the PC (respectively) with the second and third instruction bytes. The
destination may therefore be anywhere in the full 64K program memory address space. No
flags are affected.
Example: The label “JMPADR" is assigned to the instruction at program memory location 1234H. The
instruction,
LIMP JMPADR
at location 0123H will load the program counter with 1234H.
Bytes: 3
Cycles: 2
Encoding: [00000010 addrt5-addre addr7-addro
Operation: LIMP
PO) — adéris.o
251 intel. MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
MOV ,
Funetion: Move byte variable
Description: The byte variable indicated by the second operand is copied into the location specified by the
first operand. The source byte is not affected. No other register or flag is affected.
This is by far the most flexible operation. Fifteen combinations of source and destination,
addressing modes are allowed.
Example: Internal RAM location 30H holds 40H. The value of RAM location 40H is 10H. The data
[Present at input port I is 110010108 (OCAH).
MOV R0,#30H :RO <= 30H
MOV A@RO ;A <= 40H
MOV RLA RI <= 40H
MOV BRI ;B <= 10H
MOV @RI,P1 ;RAM (40H) <= OCAH
MOV P2,Pi — ;P2 #0CAH
Jeaves the value 30H in register 0, 40H in both the Accumulator and register 1, 10H in register
B, and OCAH (110010108) both in RAM location 40H and output on port 2.
MOV An
Encoding, [1410] tert
Operation: MOV
(A) Rn)
Eneoding: [1110] 0101 Girect address
‘Operation: MOV
A) + Girect)
MOV A,ACC is not a valid instruction.
252 intel.
MCS®-51 PROGRAMMER’S GUIDE AND INSTRUCTION SET
MOVC A,@A+
Function:
Description:
Example:
Move Code byte
‘The MOVC instructions load the Accumulator with a code byte, or constant from program
memory. The address of the byte fetched is the sum of the original unsigned eight-bit Accumu-
lator contents and the contents of a sixteen-bit base register, which may be either the Data
Pointer or the PC. In the latter case, the PC is incremented to the address of the following
instruction before being added with the Accumulator, otherwise the base register is not al-
tered. Sixteen-bit addition is performed so a carry-out from the low-order eight bits may
propagate through higher-order bits. No flags are affected.
A value between 0 and 3 is in the Accumulator. The following instructions will translate the
value in the Accumulator to one of four values defined by the DB (define byte) directive.
REL_PC:
INC A
MOVC A,@A+PC
RET
DB 66H
DBT
DB aH
DB 99H
Ifthe subroutine is called with the Accumulator equal to OFK, it will return with 77H in the
‘Accumulator. The INC A before the MOVC instruction is needed to “get around” the RET
instruction above the table. If several bytes of code separated the MOVC from the table, the
corresponding number would be added to the Accumulator instead.
MOVC A,eA+DPTR
Bytes:
Cycles:
Encoding:
Operation:
Move AeA + PC
Bytes:
Cycles:
Encoding:
Operation:
1
2
1001[0011
Move
(A) — (A) + PTR)
1
2
1000]|0011
Move
OE) — PO + 1
AM + PO)
257 intel.
MCS®-51 PROGRAMMER’S GUIDE AND INSTRUCTION SET
MOVX ,
Funetion:
Description:
Example:
SUBB An
Bytes:
Cycles:
Encoding:
Operation:
Subtract with borrow
SUBB subtracts the indicated variable and the carry flag together from the Accumulator,
Jeaving the result in the Accumulator. SUBB sets the carry (borrow) fag if a borrow is needed
for bit 7, and clears C otherwise. (IF C was set before executing a SUBB instruction, this
indicates that a borrow was needed for the previous step in a multiple precision subtraction, so
the carry is subtracted from the Accumulator along with the source operand.) AC is set if
borrow is needed for bt 3, and cleared otherwise, OV is set if a borrow is needed into bt 6, but
‘not into bit 7, or into bit 7, but not bit 6.
‘When subtracting signed integers OV indicates a negative number produced when a negative
value is subtracted from a positive value, or a positive result when a positive number is
subtracted from a negative number
‘The source operand allows four addressing modes: register, direct, register-indirect, or imme-
diate,
‘The Accumulator holds OC9H (110010018), register 2 holds $4H (10101008), and the carry
flag is set. The instruction,
SUBB AR?
‘will leave the value 74H (011101008) in the accumulator, with the carry flag and AC cleared
bbut OV set.
[Notice that OCOH minus $4H is 75H. The difference between this and the above result is due
to the carry (borrow) flag being set before the operation. If the state of the carry is not known
before starting a single or multiple-precision subtraction, it should be explicitly cleared by
CLR C instruction.
1001] trer
SUBB
(A) (A) - © ~ Ra)
2-70
