MEMORY HIERARCHY

The memory hierarchy is a system of different

memory types (caches, main memory, secondary
storage) organized to provide a balance between
speed, cost, and capacity.
Levels:
Caches (L1, L2): Small, fast, and expensive memory
used to store frequently accessed data and
instructions.
Main Memory (RAM): Larger, slower, and less
expensive memory used for general data and
program storage.
Secondary Storage (Hard Disk, SSD): Very large, slow,
and inexpensive memory used for persistent
storage.
Purpose:
The hierarchy aims to provide the CPU with fast
access to data while keeping the overall cost and
capacity reasonable.

Registers are managed directly by the compiler

Cache is managed automatically by the hardware
On Chip RAM is managed by the programmer
Off Chip RAM is managed by the operating system
On-chip memory
Some form of on-chip memory is essential if a microprocessor is to deliver its best performance. With today's clock
rates, only on-chip memory can support zero wait state access speeds, and it will also give better power-efficiency and
reduced electromagnetic interference than off-chip memory

In many embedded systems simple on-chip RAM is preferred to cache for a number benefits of reasons:

• It is simpler, cheaper, and uses less power. Where as cache memory carries a significant overhead in terms of the
logic that is required to enable it to operate effectively. It also incurs a significant design cost if a suitable off-the-shelf
cache is unavailable.

• It has more deterministic behaviour. Where as cache memories have complex behaviours which can make difficult to
predict how well they will operate under particular circumstances. In particular, it can be hard to guarantee interrupt
response time.

The drawback with on-chip RAM vis-d-vis cache is that it requires explicit management by the programmer, whereas a
cache is usually transparent to the programmer.

One important advantage of on-chip RAM is that it enables the programmer to allocate space in it using knowledge of
the future processing load. A cache left to its own devices has knowledge only of past program behaviour, and it can
therefore never prepare in advance for critical future tasks. Again, this is a difference which is most likely to be
significant when critical tasks must meet strict real time constraints.
 CACHES
A cache is a block of high-speed memory that contains a number of entries, each consisting of main memory address
information, commonly known as a tag and the associated data. It keeps copies of recently used memory values and supplies
these to the processor when it asks for them again, thereby avoiding an off-chip memory access. It also decides which values
to over-write when it is full.

Caches increase the average speed of a memory access. Cache operation takes account of two principles of locality:

Spatial locality : An access to one location is likely to be followed by accesses to adjacent locations. Examples of this principle
are: sequential instruction execution and accessing a data structure.

Temporal locality: An access to an area of memory is likely to be repeated in a short time period. An example of this principle
is the execution of a software loop.

Cache performance metrics

HIT: An access to an item which is in the cache is called a hit, Miss. An access to an item which is not in the cache is a miss.

Hit rate: The proportion of all the memory accesses that are satisfied by the cache is the hit rate, usually expressed as a % .
Miss rate: The proportion that are not is the miss rate.

The miss rate of a well-designed cache should be only a few per cent if a modern processor is to fulfil its potential. The miss
rate depends on a number of cache parameters, including its size (the number of bytes of memory in the cache) and its
organization.
 A unified instruction and data cache Separate data and instruction caches

Both these organizations have their merits. The unified cache automatically adjusts the proportion of the cache
memory used by instructions according to the current program requirements, giving a better performance than a
fixed partitioning. On the otherhand, the separate caches allow load and store instructions to execute in a single clock
cycle.
MEMORY MANAGEMENT UNIT (MMU)

The Memory Management Unit (MMU) is a computer hardware unit and it is responsible for the translation of virtual
addresses used by software to physical addresses used in the memory system.

The MMU contains the following:

• The table walk unit, which contains logic that reads the translation tables from memory.
• Translation Lookaside Buffers (TLBs), which cache recently used translations.

All memory addresses that are issued by software are virtual. These memory addresses are passed to the MMU, which checks
the TLBs for a recently used cached translation. If the MMU does not find a recently cached translation, the table walk unit
reads the appropriate table entry or entries, from memory.
A virtual address must be translated to a physical address before a memory access can take place (because we must know
which physical memory location we are accessing). This need for translation also applies to cached data, because on Armv6
and later processors, the data caches store data using the physical address (addresses that are physically tagged). Therefore,
the address must be translated before a cache lookup can complete.
Functions of Memory Management Unit(MMU)
With the growth of technology the function of Memory Management Unit (MMU) is in its role in address
translation, memory protection, virtual memory management, and how it becomes the backbone of multitasking in
modern operating systems. So lets get into it to know some of the functions of a Memory Management Unit we
have classified some of them below.

Address Translation: An MMU's primary job is to converting virtual addresses into physical addresses. The MMU
converts virtual addresses created by running programs to corresponding physical addresses in the computer's
memory. This translation is essential for the CPU to access the correct locations in RAM and interact with the
necessary data.
Memory Protection: MMUs also play a crucial role in implementing memory protection mechanisms. By
implementing access control rules and regulations, they stop illegal usage of particular memory locations. By doing
this, the operating system's security and data integrity are ensured.
Virtual Memory Management: MMUs serves a part in the implementation of this method, which allows heavier
programs to be executed than what can fit in the physical RAM. The system can use virtual memory to extend RAM
by using a portion of the storage space on the disc and dynamically switch data between RAM and the disc as
needed.
Memory Segmentation: Memory segmentation is a feature found in certain MMUs. It splits the computer's memory
into sections that have multiple authorizations and features. This segmentation provides a more granular control
over memory access and aids in optimizing memory utilization.
MEMORY SEGMENTS

The simplest form of memory management allows an application to view its memory as a set of segments, where each
segment contains a particular sort of information. Segmentation is a technique for allocating memory in chunks of
varying and meaningful sizes instead of one arbitrary page size. Since the segment sizes are selected by the compiler,
internal fragmentation is reduced. For instance, a program may have a code segment containing all its instructions, a
data segment and a stack segment. Every memory access provides a segment selector and a logical address to the
MMU. Each segment has a base address and a limit associated with it. The logical address is an offset from the segment
base address, and must be no greater than the limit or an access violation will occur, usually causing an exception.
Segments may also have other access controls, for instance, the code segment may be read-only and an attempt to
write to it will also cause an exception.
 MEMORY PAGING

In a paging memory management scheme both the logical and the physical address spaces are divided into fixed-size
components called pages. A page is usually a few kilobytes in size, but different architectures use different page sizes.
The relationship between the logical and physical pages is stored in page tables, which are held in main memory. most
paging systems use two or more levels of page table. For example, the top ten bits of the address can be used to identify
the appropriate second-level page table in the first-level page table directory, and the second ten bits of the address
then identify the page table entry which contains the physical page number.
Frames: Dividing the physical memory into equal sized memory units called frames.
Page: Diving the logical memory into units called pages. The pages must be the same size as the frames