Venus Digital Electronics 1

(c) 10 (d) 12
Digital Electronics Ans. (b)
11. According to De-Morgan’s second theorem -
(a) A NAND gate is always complementary to an AND
Multiple ChoiCe Question gate
(b) An AND gate is equivalent to bubbled NAND gate
1. A group of 4 bits is known as - (c) A NAND gate is equivalent to a bubbled AND gate
(a) a nibble (b) a byte (d) A NAND gate is equivalent to a bubbled OR gate
(c) a bit (d) an octal number Ans.(c)
Ans. (a) 12. A + AB + ABC + ABCD + ABCDE + ......=
2. The binary equivalent of the hexadecimal number (a) 1 (b) A
AOB5 is - (c) A + AB (d) AB
(a) 10100001010 (b) 1001111101001010 Ans.(b)
(c) 1010000010110101 (d) 1011000011000101
13. A + AB + A B C + A B C D + .... =
Ans. (c)
3. Decimal number 13 is represented in natural BCD (a) A + B + C + .... (b) A  B  C  D  .....
as - (c) 1 (d) 0
(a) 1101 (b) 00010011 Ans.(a)
(c) 00001101 (d) 00011101
14. De Morgan’s theorem states that
Ans. (a)
4. The binary equivalent of 576 is - (a) A  B  AB and AB  A  B
(a) 110000000, (b) 1000000100, (b) A  B  A  B and AB  AB
(c) 1001000000
Ans. (c) (c) A  B  A  B and AB  AB
5. Which of the following 4-bit combination is invalid (d) A  B  AB and AB  AB
BCD- Ans.(a)
(a) 0101 (b) 1010
(c) 1001 (d) 0011 15. The logic expression (A + B) (A + B) can be imple-
Ans. (b) mented by giving the inputs A and B to a two-input
6. Reflected code is - (a) NOR gate (b) NAND gate
(a) gray code (b) binary code (c) X-OR gate (d) X-NOR gate
Ans. (a) Ans.(c)
7. In octal system the value 26 is -
(a) 20 (b) 40 16. The logic expression (A + B) (A + B) can be imple-
(c) 31 (d) 100 mented by giving the inputs A and B to a two-input
Ans. (d) (a) NOR gate (b) NAND gate
8. In binary code, shifting a register to left by one bit (c) X-OR gate (d) X-NOR gate
position is equivalent to -
Ans.(d)
(a) subtraction by 2 (b) addition by 2
17. Which of the following Boolean algebraic expres-
(c) division by 2 (d) multiplication by 2
sions is incorrect ?
Ans.(c)
9. Which of the following code is used to reduce the (a) A  AB  A  B (b) A  AB  B
error due to ambiguity in reading of a binary optical (c) (A  B)(A  C)  A  BC (d) (A  B)(A  B)  A
encoder?
(a) BCD code (b) Gray code Ans.(b)
(c) Excess-3 code (d) Octal code 18. The simplified form of the Boolean expression
Ans.(b) (X+Y+XY) (X+Z) is
10. Total number of cells in the Karnaugh map of a (a) X+Y+Z (b) XY+YZ
switching function (A,B,C) consisting of only three (c) X+YZ (d) XZ+Y
variables is - Ans.(c)
(a) 4 (b) 8 19. The simplified form of the Boolean expression
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(X + Y + Z)(X + Y + Z)(X + Y + Z)
Ans.(c)
28. The logic expression F = AB + BC = AC is in
(a) XY  Z (b) X+YZ
(a) SOP form (b) POS form
(c) XY  Z (d) XY+Z (c) standard SOP form (d) standard POS form
Ans.(b) Ans.(a)
20. A + B = B + A; AB = BA represent which laws ? 29. Th logic expression
(a) Commutative (b) Associative
F = (A + B + C)(A + C)(B + C)(A + C) is in
(c) Distributive (d) Idempotence
Ans.(a) (a) SOP form (b) POS form
21. (A+B) + C = A+(B+C); (A+B) (A+C) represent (c) standard SOP form (d) standard POS form
which laws ? Ans.(b)
(a) Commutative (b) Associative 30. K-map is used
(c) Distributive (d) Idempotence (a) to minimize the number of flip-flops in a digital
Ans.(b) circuit
22. A(B+C)=AB+AC; A+BC=(A+B)(A+C) represent (b) to minimize the number of gates only in a digital
which laws? circuit
(a) Commutative (b) Associative (c) to minimize the number of gates and the fan in re-
(c) Distributive (d) Idempotence quirements of the gates in a digital circuit
Ans.(c) (d) to design gates
23. A+AB=A; A (A+B) = A represent which laws? Ans.(c)
(a) Idempotence (b) Absorption 31. The number of cells in a 6-variable K-map is
(c) Associative (d) Commutative (a) 6 (b) 12
Ans.(b) (c) 36 (d) 64
Ans.(d)
24. AB + AC + BC = AB + AC represents which theorem?
32. The code used for labelling cells of the K-map is
(a) Consensus (b) Transposition
(a) natural BCD (b) Hexadecimal
(c) De Morgan’s (d) none of these
(c) Gray (d) octal
Ans.(a)
Ans.(c)
25. AB + AC = (A + C)(A + B) represents which theorem 33. An n variable K-map can have
(a) Consensus (b) Transposition (a) n2 cells (b) 2n cells
(c) De Morgan’s (d) Included factor (c) nn cells (d) n2n cells
Ans.(b) Ans.(b)
26. The dual of a Boolean expression is obtained by 34. The binary number designations of the rows and
(a) interchanging all 0s and 1s columns of the K-map are in
(b) interchanging all 0s and 1s, all + and ‘·’signs (a) binary code (b) BCD code
(c) interchanging all 0s and 1s all + and ‘·’signs and (c) Gray code (d) XS-3 code
complementing all the variables Ans.(c)
(d) interchanging all + and ‘·’ signs and complement- 35. The number of cells in a 6 variable K-map is
ing all the variables (a) 6 (b) 12
Ans.(b) (c) 36 (d) 64
27. The complement of a Boolean expression is obtained Ans.(d)
by 36. The number of adjacent cells each cell in an n vari-
(a) interchanging all 0s and 1s able K-map can have is
(b) interchanging all 0s and 1s, all + and ‘·’ signs (a) n – 1 (b) n
(c) interchanging all 0s and 1s, all + and ‘·’ signs and (c) n + 1 (d) 2n
complementing all the variables Ans.(b)
(d) interchanging all + and ‘·’ signs and complement- 37. The first contibution to logic was made by
ing all the variables (a) George Boole, (b) Copernicus,
 Venus Digital Electronics 3

(c) Aristotle, (d) Shannon. Ans. (b)

Ans. (a) 49. This figure is the symbol of a –
38. Which logic gate is similar to the function of two (a) OR gate, (b) NOR gate, (c) XOR gate.
series switches ? Ans. (c)
(a) AND (b) OR (c) XOR (d) NAND 50. The minimum number of NAND gates required to
Ans. (a) realize a XOR gate is –
39. The gate ideally suited for bit comparison is a - (a) 4 (b) 5 (c) 6
(a) two input X-NOR gate (b) two input X-OR gate Ans. (b)
(c) two input NOR gate (d) two input NAND gate 51. The output of a logic gate ‘1’ when all its inputs are
Ans. (a) at logic ‘0’. The gate is either –
40. The expression ( A  AB) can be written as - (a) a NAND or an EX-OR gate
(b) a NOR or an EX-OR gate
(a) A (b) B (c) A  B (d) A (c) an AND or an EX-NOR gate
Ans. (c) (d) a NOR or an EX-NOR gate
41. The dual of (AB+CD): Ans. (d)
(a) (A+B) (C+D) (b) (A+B+C+D) 52. A combinational circuit can be designed using only
Ans. (a) (a) AND gates (b) OR gates
42. Law of tautology states - (c) OR and X-NOR gates (d) NOR gates
(a) A. A  A and A  A  A (b) A. A  A and A  A  A Ans.(d)
(c) A.A=A and A+A=A 53. A combinational circuit can be designed using only
Ans. (c) (a) AND gates (b) OR gates
43. Minimization of Boolean logical expressions helps (c) OR and X-NOR gates (d) NAND gates
to reduce- Ans.(d)
(a) Space (b) Cost 54. The NAND gate can function as a NOT gate if
(c) Number of gate (d) All of these (a) all inputs are connected together
Ans. (d) (b) inputs are left open
44. Which of the following does not represent Boolean (c) one input i set to 0
algebra operation? (d) one input is set to 1
(a) AND (b) OR Ans.(a)
(c) NOT (d) XOR 55. The NOR gate can function as NOT gate if
Ans. (d) (a) all inputs are connected together
45. Tri-state buffer has - (b) inputs are left open
(a) 3 output states (b) 2 output states (c) one input is set to 0
(c) 1 output states (c) no output states (d) one input is set to 1
Ans. (a) Ans.(a)
46. When an input electrical signal A = 101010 is applied 56. An X-OR gate gives a high output
to a NOT gate, the output signal will - (a) if there are odd number of is
(a) 111010 (b) 101010 (b) if it has even number of 0s
(c) 10101 (d) 101011 (c) if the decimal value of digital word is even
(d) for odd decimal value.
Ans. (c)
Ans.(a)
47. The dual of the Boolean theorem A. (B + C) is –
57. An exclusive NOR gate is logically equivalent to
(a) A + (B.C) = A. B + A.C
(a) inverter followed by a X-OR gate
(b) A. (B + C) = (A + B) (A + C)
(b) X-OR gate followed by an inverter
(c) A + (B.C) = (A + B). (A + C)
(c) NOT gate followed by a NOR gate
(d) none of these
(d) complement of a NOR gate
Ans. (c)
Ans.(b)
48. A NAND gate is called a universal gate because –
58. The X-OR and X-NOR gates can have how many
(a) many computers use this gate,
inputs ?
(b) any function can be realize by this gate,
(a) 2 (b) 1
(c) all minimization techniques are applicable to this
(c) 4 (d) any number
gate
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Ans.(a) (a) 3 (b) 4

59. The logic expression AB + AB can be implemented (c) 5 (d) 6
by giving the inputs A and B to a two input Ans.(c)
(a) NOR gate (b) NAND gate 69. An AND gate can be imagined as
(c) X-OR gate (d) X-NOR gate (a) switches connected in series
Ans.(d) (b) switches connected in parallel
(c) transistors connected in series
60. The logic expression AB + AB can be implemented byy (d) transistors connected in parallel
giving inputs A and B to a two-input Ans.(a)
(a) X-OR gate (b) NAND gate 70. An OR gate can be imagined as
(c) X-OR gate (d) X-NOR gate (a) switches connected in series
Ans.(c) (b) switches connected in parallel
61. What is the minimum number of two-input NAND (c) transistors connected in series
gates used to perform the function of 2-input OR (d) transistors connected in parallel
gate ? Ans.(b)
(a) one (b) two 71. The output of a gate is LOW when at least one of its
(c) three (d) four inputs is HIGH. This is true for
Ans.(c) (a) AND gate (b) NAND gate
62. NOT gates are to be added to the inputs of which (c) NOR gate (d) X-OR gate
gate to convert it to a NAND gate ? Ans.(c)
(a) OR (b) AND 72. The output of a gate is HIGH when at least one of
(c) NOT (d) X-OR its inputs is HIGH. This is ture for
Ans.(a) (a) AND (b) NAND
63. NOT gates are to be added to the inputs of which (c) NOR (d) OR
gate to convert it to a NOR gate ? Ans.(b)
(a) OR (b) AND 73. The output of a gate is HIGH if and only if all its
(c) NAND (d) X-NOR inputs are HIGH. It is true for
Ans.(b) (a) AND (b) X-NOR
64. The output of a NOR gate is high (c) NOR (d) NAND
(a) only when all the inputs are low Ans.(d)
(b) only when all the inputs are high 74. The output of a gate is HIGH if and only if all its
(c) only when at least one input is high inputs are LOW. It is true for
(d) only when at least one input is low (a) NOR (b) X-OR
Ans.(a) (c) NAND (d) X-NOR
65. The output of a NAND gate is low Ans.(a)
(a) only when all the inputs are low 75. The most suitable gate for comparing two bits is
(b) only when all the inputs are high (a) AND (b) OR
(c) only when at least one input is high (c) NAND (d) X-OR
(d) only when at least one input is low Ans.(d)
Ans.(b) 76. Which of the following gates cannot be used as an
66. How many NOR gates are required to obtain AND inverter ?
operation ? (a) NAND (b) AND
(a) 2 (b) 3 (c) NOR (d) X-NOR
(c) 4 (d) 1 Ans.(b)
Ans.(b) 77. A gate is enabled when its enable input is at logic 1.
67. What is the minimum number of NOR gates re- The gate is
quired to realize an X-OR gate ? (a) OR (b) NAND
(a) 3 (b) 4 (c) NOR (d) none of these
(c) 5 (d) 6 Ans.(b)
Ans.(b) 78. A gate is inhibited when its inhibit input is at logic 0.
68. What is the minimum number of NOR gates The gate is
required to realize an X-OR gate ? (a) NOR (b) AND
 Venus Digital Electronics 5

(c) NAND (d) none of these

Ans.(a)
79. A gate is inhibited when its inhibit input is at logic 1.
The gate is
(a) AND (b) NAND (a) if and only if both inputs are HIGH
(c) OR (d) none of these (b) if and only if both the inputs are LOW
Ans.(c) (c) if one of the inputs is LOW
80. A gate is disabled when its disable input is at logic 0. (d) if one of the inputs is HIGH
The gate is Ans.(b)
(a) AND (b) NOR 89. For the gate shown in the figure, the output will be
(c) OR (d) none of these HIGH
Ans.(a)
81. The output of a logic gate is 1 when all its inputs are
at logic 1. The gate is either
(a) a NAND or a NOR (b) an AND or an OR
(c) an OR or an X-OR (d) an AND or a NOR (a) if both inputs are HIGH
Ans.(b) (b) if one of the inputs is HIGH
82. The output of a logic gate is 1 when all its inputs are (c) if one of the input is LOW
at logic 1. The gate is either (d) if and only if both the inputs are LOW
(a) a NAND or a NOR (b) an AND or an X-NOR Ans.(c)
(c) an OR or a NAND (d) an X-OR or an X-NOR 90. For the gate shown in the figure, the output will be
Ans.(a) LOW
83. The output of a logic gate is 1 when all its inputs are
at logic 1. The gate is either
(a) an OR or an X-OR
(b) a NAND or an X-NOR
(c) an AND or a NAND (a) if one of the inputs is LOW
(d) an OR or an X-NOR (b) if and only if both the inputs ar LOW
Ans.(d) (c) if and only if both inputs are HIGH
84. The output of a logic gate is 1 when all its inputs are (d) if one of the inputs is HIGH
at logic 0. The gate is either Ans.(a)
(a) a NOR or an X-OR (b) a NAND or an X-OR 91. For the gate shown in the figure, the output will be
(c) an OR or an X-NOR (d) an AND or an X-OR LOW
Ans.(a)
85. The output of a logic gate is 0 when all its inputs are
at logic 1. The gate is either
(a) a NAND or an AND (b) a NAND an X-NOR (a) if one of the inputs is HIGH
(c) a NOR or an X-NOR (d) a NAND or an X-NOR (b) if both the inputs are LOW
Ans.(b) (c) if and only if both inputs are HIGH
86. The output of a logic gate is 0 when all its inputs are (d) if and only if both the inputs are LOW
at logic 0. The gate is either Ans.(d)
(a) an AND or a AND (b) a NAND or an X-OR 92. Which of the gate shown in the figure is an AND
(c) a OR or a X-OR (d) an OR or an X-NOR gate
Ans.(c)
87. The number of rows in the truth table of a 4-input (a) (b)
gate is
(a) 4 (b) 8 (c) (d)
(c) 12 (d) 16
Ans.(d) Ans.(c)
88. For the gate shown in the figure, the output will be 93. Total number of cells in the Karnaugh map of a
HIGH switching function (A,B,C) consisting of only three
variables is -
 Venus Digital Electronics 6

(a) 4 (b) 8 (c) 10 (d) 12 106.Which of the following logic circuit accepts two bi-
Ans.(b) nary digits on inputs, and produces two binary dig-
94. An N-bit adder consists of – its, a sum bit and a carry bit on its output ?
(a) (N – 1) full adders (b) (N + 1) full adders (a) full-adder (b) half-adder
(c) N full adders (d) (N – 2) full adders. (c) serial adder (d) parallel adder
Ans.(a) Ans.(b)
95. A half adder circuit is constructed by using - 107.How many inputs and outputs does a full-adder have?
(a) a 2-input OR and a 2-input AND gates (a) two inputs, two outputs (b) two inputs, one output
(b) a 2- input XOR and a 2- input AND gates (c) three inputs, two outputs
(c) a 2-input XOR and a 2-input OR gates (d) two inputs, three outputs
Ans.(b) Ans.(c)
96. Any combinational circuit can be designed using - 108.How many inputs and outputs does a full-subtractor
(a) only NAND (b) AND and OR (c) only AND circuit have ?
Ans.(a) (a) two inputs, one outputs (b) two inputs, one output
97. A multiplexer can be used as – (c) two, inputs, three outputs
(a) Counter (b) Shift register (d) three inputs, two output
(c) Combinational circuit (d) 7-segment display Ans.(d)
Ans.(c) 109.A full-adder can be realized using
98. The number of inputs and outputs in a full adder (a) one half-adder, two OR gates
are - (b) two half-adders, one OR gate
(a) 2 and 1 (b) 2 and 2 (c) 3 and 3 (d) 3 and 2 (c) two half-adders, two OR gates
Ans.(d) (d) two half-adders, on AND gate
99. A device changes parallel data to serial data – Ans.(b)
(a) encoder (b) decoder 110. The minimum number of 2-input NAND/NOR
(c) multiplexer (d) none of these gates required to realize a half-adder is
Ans.(b) (a) 3 (b) 4 (c) 5 (d) 6
100.Which device changes parallel data to serial data – Ans.(c)
(a) decoder (b) multiplexer 111. The minimum number of 2-input NAND gates re-
(c) demultiplexer (d) flip-flop quired to realize a half-subtractor is
Ans.(b) (a) 3 (b) 4 (c) 5 (d) 6
101. A 4 to 1 multiplexer requires ..... data select line – Ans.(c)
(a) 1 (b) 2 (c) 3 (d) 4 112. The minimum number of 2-input NAND gates re-
Ans.(b) quired to realize a full adder /full-subtractor is
102.The minimum number of full required in a 4-bit par- (a) 8 (b) 9 (c) 10 (d) 12
allel adder will be - Ans.(b)
(a) 2 (b) 3 (c) 4 (d) 5 113. How many full-adders are required to construct an
Ans.(c) m-bit parallel adder ?
103.A multiplexer with 4-bit data select input is a – (a) m/2 (b) m-1
(a) 4 : 1 multiplexer (b) 8 : 1 multiplexer (c) m (d) m+1
(c) 16 : 1 multiplexer (d) 32 : 1 multiplexer Ans.(b)
Ans.(c) 114. Parallel adders are
104.In K-map, when eight adjacent 1’s grouped horizon- (a) combinational logic (b) sequential logic circuits
tally or vertically the group so found is called (c) both of the above (d) none of the above
(a) pair (b) quad (c) octet (d) hex Ans.(a)
Ans. 115. In which of the following adder circuit is the carry
105.The defference output in a full-subtractor is the same ripple delay eliminated ?
as the (a) half-adder (b) full-adder
(a) difference output of a half-subtractor (c) parallel adder (d) carry-look-ahead adder
(b) sum output of a half-adder Ans.(d)
(c) sum output of a full-adder 116. A parallel adder in which the carry-out of each full-
(d) carry output of a full-adder adder is the carry-in the next significant digit adder
Ans.(c) is called a
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(a) ripple carry called a (b) look-ahead-carry adder 127.A 4-variable logic circuit can be designed using
(c) serial carry adder (d) parallel carry adder (a) 16:1 multiplexer
Ans.(a) (b) an 8:1 multiplexer and one inverter
117. The adder preferred for applications where circuit (c) two 8:1 multiplexers and one 2:1 multiplexer
minimization is more important than speed is (d) any of the above
(a) parallel adder (b) serial adder Ans.(d)
(c) full-adder (d) half-adder 128.A 16:1 multiplexer can be used to design
Ans.(b) (a) 4 variable logic function
118. A serial adder requires only one (b) BCD to binary code converter
(a) half-adder (b) full-adder (c) BCD to 7 segment decoder
(c) counter (d) multiplexer (d) full-adder
Ans.(b) Ans.(a)
119. A multiplexer is also known as
(a) data accumulator (b) a data restorer
Dear Students,
(c) a data selector (d) a data distributor
Ans.(c)  Venus Publication Question Bank are avail-
120.How many select lines are contained in a multiplexer able at your nearest book store.
with 1024 inputs and one output ? All Question are important and taken from
(a) 412 (b) 528 MSBTE, JUT and Bihar SBTE.
(c) 64 (d) 10
Ans.(d)  For any query or problem , Please whatapps
121. What is the largest number of data inputs which a on +91 9007069442.
data selector with two control inputs can handle ?
(a) 2 (b) 4 (c) 8 (d) 16
Ans.(b)
122.A multiplexer with four select bits is a
(a) 4:1 multiplexer (b) 8:1 multiplexer
(c) 16:1 multiplexer (d) 32:1 multiplexer
Ans.(c)
123.The number of select lines m, required to select one
out of n input lines is
(a) m = log2 n (b) m= log n
(c) m= 1n n (d) m=2n
Ans.(a)
124.A MUX with its address bits generated by a counter
operates as a
(a) parallel-to-serial converter
(b) serial-to-parallel converter
(c) modified counter
(d) modified multiplexer
Ans.(a)
125.A 32:1 mux can be designed using
(a) two 16:1 muxs and one two input OR gate
(b) two 16:1 muxs and one two input AND gate
(c) two 16:1 muxs and two two input OR gates
(d) two 16:1 muxs only
Ans.(a)
126.The number of 16:1 multiplexers required for design-
ing a 4-output-variable combinational circuit is
(a) 16 (b) 8 (c) 4 (d) 1
Ans.(c)