M.A.M.

SCHOOL OF ENGINEERING
(Accredited by NAAC)
Approved by AICTE, New Delhi; Affiliated to Anna University, Chennai
Siruganur, Trichy -621 105. www.mamse.in

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

CO-PO/PSO MAPPING
Course Name : Digital Principles and System Design
Course Code : CS8351
Faculty Name : Saravanan S

Course Objective:
 To design digital circuits using simplified Boolean functions
 To analyze and design combinational circuits
 To analyze and design synchronous and asynchronous sequential circuits
 To understand Programmable Logic Devices
 To write HDL code for combinational and sequential circuits

Course Outcomes:
On Completion of the course, the students should be able to:

Bloom’s Cognitive
CO No. Statement
Level
CO 1 Design digital circuits using simplified Boolean functions L3 - Applying

CO 2 Analyze and design combinational circuits L4 – Analyzing

Analyze and design synchronous and asynchronous sequential L4 – Analyzing
CO 3
circuits
CO 4 Understand Programmable Logic Devices L2 - Understanding

CO 5 Develop HDL code for combinational and sequential circuits L4 – Analyzing

CO Mapping to PO/PSOs with Justification:

Table: Mapping Levels of COs to POs / PSOs

COs Program Outcomes (POs) PSOs
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3
C211.1 3 2 3 1 2 - - - - 1 - 1 3 1 2
C211.2 3 2 3 1 2 - - - - 1 - 1 3 1 2
C211.3 3 2 3 2 2 - - - - 1 - 1 3 1 2
C211.4 2 1 2 1 3 - - - - 1 - 1 2 2 3
C211.5 2 2 3 2 3 - - - - 1 1 2 3 2 3
Avg

Course Mapped
Justification
Outcome with POs
Number
Requires foundational knowledge of Boolean algebra, logic gates,
PO1
and digital electronics.
Students analyze truth tables and simplify logic expressions, which
PO2
involve analytical thinking.

PO3 Involves designing optimized digital circuits from specifications.

Minimal investigation required but some design testing may be

PO4
involved.

PO5 Basic CAD tools or logic simulation tools might be used.

CO1 Required when presenting simplified designs or justifying them in
PO10
team reviews or reports.
Digital logic design is foundational, and skills are updated with
PO12
evolving tools.
Designing digital circuits using Boolean functions is a core
PSO1
foundational concept in computer science and engineering.
Limited application of software engineering principles in basic
PSO2 Boolean logic design, though logic design contributes to structured
thinking.
Involves using modern logic design tools and simulation software
PSO3
(e.g., Logisim, Quartus), which aligns with emerging ICT.

Course
Mapped
Outcome Justification
with POs
Number
Requires strong theoretical knowledge in logic design and number
PO1
systems.
Involves analyzing behavior of combinational circuits for
PO2
correctness.

PO3 Emphasizes designing circuits like adders, multiplexers, decoders.

PO4 May involve basic simulation or logical proof of behavior.

Often involves using tools like digital circuit simulators (e.g.,

PO5
Logisim, Quartus).
CO2
Communication of circuit design choices in documentation or oral
PO10
presentations.
Learning design approaches improves adaptability to evolving
PO12
technologies.
Combinational circuit design is essential in understanding data
PSO1
paths, ALUs, and other computer architecture components.
Only indirectly linked to software development, with minimal
PSO2
influence from engineering principles.
Can be designed using CAD tools and modern circuit simulators,
PSO3
supporting ICT-based innovation.

Course
Mapped
Outcome Justification
with POs
Number
 PO1 Requires deep understanding of flip-flops, counters, FSMs, etc.

Analyzing timing, states, and behavior of circuits needs analytical

PO2
thinking.

PO3 Design of sequential systems like traffic controllers, elevators, etc.

Involves investigation through timing diagrams, simulations, or

PO4
debugging state transitions.
Tools for design and timing analysis (ModelSim, VHDL simulators)
PO5
are often used.
CO3
Communicating design and state transitions is necessary in
PO10
teamwork or review.
Requires continuous learning to keep up with timing constraints and
PO12
new design methods.
These circuits are critical for state machines, counters, and control
PSO1
units—important computing elements
Limited connection with business/scientific applications directly,
PSO2
though logical flow resembles control structures in programming.
Sequential design uses simulation platforms that reflect
PSO3
advancements in ICT.

Course
Mapped
Outcome Justification
with POs
Number
Understanding device architecture and usage (PLA, PAL, CPLD,
PO1
FPGA).

PO2 Minor analytical component in selecting or comparing PLDs.

PO3 Designing logic functions using programmable platforms.

Basic investigations like performance comparison or suitability for

PO4
use.

PO5 Involves hands-on usage of PLD tools like Xilinx, Altera.

CO4
PO10 Minor communication required in documenting use of PLDs.

PO12 Adaptation to evolving programmable platforms is essential.

Requires application of theoretical knowledge to real-world

PSO1
hardware components, reinforcing foundational understanding.
While not software, designing PLDs involves structured
PSO2
development akin to software engineering.
PLDs are configured using modern tools like VHDL/Verilog, which
PSO3
are based on current ICT technologies.

Course
Mapped
Outcome Justification
with POs
Number
CO5 PO1 Requires application of digital system theory in coding.
 PO2 Analysis required to debug and validate code functionally.

PO3 Students design and implement circuits using Verilog/VHDL.

PO4 Verification, simulation, and testing of HDL code is critical.

Strong usage of HDL tools (Xilinx Vivado, ModelSim, etc.)

PO5
involved.

PO10 Code documentation and team discussions are part of development.

PO11 Involves understanding best practices and professional tools.

HDL languages evolve; learning newer methods (e.g.,

PO12
SystemVerilog) is needed.
Writing HDL code merges logic design with programming—an
PSO1
essential skill blending theory with practical implementation.
HDL coding follows modular design, testing, and documentation—
PSO2
mirroring software engineering practices.
HDL development uses advanced ICT tools (e.g., ModelSim,
PSO3
Vivado), and supports innovation in hardware design.

Course Coordinator HOD

M.A.M. SCHOOL OF ENGINEERING

(Accredited by NAAC)
Approved by AICTE, New Delhi; Affiliated to Anna University, Chennai
 Siruganur, Trichy -621 105. www.mamse.in

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

CO-PO/PSO MAPPING
Course Name : Microprocessors and Microcontrollers
Course Code : EC8691
Faculty Name : Saravanan S

Course Objective:
 To understand the Architecture of 8086 microprocessor.
 To learn the design aspects of I/O and Memory Interfacing circuits.
 To interface microprocessors with supporting chips.
 To study the Architecture of 8051 microcontroller.
 To design a microcontroller-based system

Course Outcomes:

Bloom’s Cognitive
CO No. Statement
Level
Understand architecture and operations of a microprocessor system
CO 1 L2 - Understanding
in depth.
Demonstrate programming proficiency using the various addressing
CO 2 L2 - Understanding
modes and data transfer through system bus of the microprocessor
Analyze, specify, design, write and test assembly language
CO 3 L2 - Understanding
programs of interfacing with I/O and memory
Perform the detailed hardware design of the microcontroller system,
CO 4 and program the microcontroller using suitable techniques and L5 - Evaluating
software tools.
CO 5 Design microprocessor and microcontroller-based applications. L2 - Understanding

CO Mapping to PO/PSOs with Justification:

Table: Mapping Levels of COs to POs / PSOs

COs Program Outcomes (POs) PSOs
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3
C212.1 3 3 3 2 - - - 1 1 2 3 3
C212.2 2 2 3 2 2 3 - - - 3 3 3
C212.3 2 2 3 3 3 3 - 2 2 3 3 3
C212.4 3 3 3 3 3 - - 2 2 3 3 3
C212.5 3 3 3 3 3 3 2 2 2 - 3 3
Avg
Course Coordinator HOD