Lecture 6 & 7

Topics covered:
CPU Architecture
 Contents

❑ Processor Internal Organization

◆ Single bus

◆ Multiple bus

❑ Writing an instruction control sequence(execution steps)

❑ Hardwired Control unit

❑ Microprogramed Control unit

1
 Internal organization of a processor

❑ Recall that a processor has several registers/building

blocks:
◆ Memory address register (MAR)
◆ Memory data register (MDR)
◆ Program Counter (PC)
◆ Instruction Register (IR)
◆ General purpose registers R0 - R(n-1)
◆ Arithmetic and logic unit (ALU)
◆ Control unit.
❑ How are these units organized and how do they communicate
with each other?

2
 Internal organization of a processor
Internal processor
bus

Control signals

PC

Instruction
Address
decoder and
lines
MAR control logic

Memory
bus

MDR
Data
lines IR

Y
Constant 4 R0

Select MUX

Add
A B
ALU Sub R ( n - 1)
control ALU
lines
Carry-in
XOR TEMP

Z
 Single bus organization

❑ Single bus organization:

◆ ALU, control unit and all the registers are connected via a
single common bus.
◆ Bus is internal to the processor and should not be confused
with the external bus that connects the processor to the
memory and I/O devices.
❑ Data lines of the external memory bus are connected to the
internal processor bus via MDR.
◆ Data may be loaded to (from) MDR from (to) internal processor
bus or external memory bus.
◆ MDR has two inputs and two outputs.
❑ Address lines of the external memory bus are connected to
the internal processor bus via MAR.
◆ MAR receives input from the internal processor bus.
◆ MAR provides output to external memory bus.

4
 Single bus organization (contd..)

❑ Instruction decoder and control logic block, or control unit

issues signals to control the operation of all units inside the
processor and for interacting with the memory bus.
◆ Control signals depend on the instruction loaded in the
Instruction Register (IR)
❑ Outputs from the control logic block are connected to:
◆ Control lines of the memory bus.
◆ ALU, to determine which operation is to be performed.
◆ Select input of the multiplexer MUX to select between
Register Y and constant 4.
◆ Control lines of the registers, to select the registers.

5
 Single bus organization (contd..)

❑ Registers Y, Z, and TEMP:

◆ Used by the processor for temporary storage during execution
of some instructions.
◆ Note that Registers R0 to R(n-1) are used to store data
generated by one instruction for later use by another
instruction.
◆ Data is stored in R0 through R(n-1) after the execution of an
instruction.
❑ Multiplexer MUX selects either the output of register Y or
a constant 4, depending upon the control input Select.
◆ Constant 4 is used to increment the value of the PC.

6
 Registers and the bus
bus line 0
bus line 1

bus line m-1 (e.g., 31)

bit 0

register

bit m-1 clock

7
 Registers and the bus (contd..)

❑ A bus may be viewed as a collection of parallel wires.

❑ Buses have no memory:
◆ They are just a collection of wires.
❑ When data is on the bus, all registers can “see” that data at
their inputs.
❑ A register may place its contents onto the bus.

8
 Registers and the bus (contd..)

❑ At any one time, only one register may output its contents to
the bus:
◆ Which register outputs its content to the bus is determined by
the control signal issued by the control logic.
◆ Control signal depends on the instruction loaded in the
instruction register IR.
❑ Registers can load data from the bus:
◆ Which registers load data from the bus is determined by the
control signal issued by the control logic.
❑ Registers are clocked (sequential) entities (unlike ALU which
is purely combinatorial).

9
 Riin
Registers are connected to the bus via
switches controlled by the signals
Ri Rin & Rout.

Riout
Each register Ri has two control signals,
Riin and Riout.
Y in

If Riin=1, the data from the bus is loaded

into the register.
Y

Constant 4 If Riout=1, the data from the register is

loaded onto the bus.
Select MUX
The same holds for registers Y and Z as
well.
A B

ALU

Z in

Z out
 Registers and the bus (contd..)

Bus

D Q
1
R iout
Q
Clock
R i in

•Each bit in a register may be implemented by an edge-triggered D flip flop.

•Two input multiplexer is used to select the data applied to the input of an
edge triggered flip-flop.
•Q output of the flip-flop is connected to the bus via a tri-state gate.

11
Registers and the bus (contd..)

Bus

D Q
1
R iout
Q
Clock
R i in

Riin = 1:
Multiplexer selects the data on the bus.
Data is loaded into the flip-flop at the rising edge of the clock.
Riin = 0:
Multiplexer feeds back the value currently stored in the flip-flop.
Q output represents the value currently stored in the flip-flop.

12
Registers and the bus (contd..)

Bus

D Q
1
R iout
Q
Clock
R i in

Riout = 1:
Tri-state gate loads the value of the flip-flop onto the bus.
Data is loaded onto the bus at the rising edge of the clock.
Riout = 0:
Gate’s output is in high-impedance (electrically disconnected) state.
Corresponds to open-circuit state.

13
 Registers and the bus (contd..)

Operation of a tri-state gate

•A tri-state gate can enter one of three output states.
- its output can be in a logic low state (L).
- its output can be in a logic high state (H).
- its output can be effectively an open-circuit (high impedance)
•When a tri-state gate is connected to a bus in high-impedance state, its outputs
are effectively disconnected from the bus.
Riout = 1, output is: Riout = 0:
Logic low, if Q = 0 High impedance
Logic high, if Q = 1 Open circuit condition
Bus Bus

0 0
D Q D Q
1 1
Clock
Q Clock
Q
Riin Riin

14
 Loading multiple registers from the bus (contd..)

❑ It is possible to load multiple registers simultaneously from

the bus.
◆ For e.g., transfer the contents of register R3 to registers R4
and R7 simultaneously.
❑ The number of registers that can be simultaneously loaded
depends on:
◆ Drive capability (fan-out)
◆ Noise.
◆ Note that this is an electrical issue, not a logical issue.
❑ Distinguish this from multiple registers loading the bus:
◆ For e.g. load the contents of registers R3 and R4 onto the bus
simultaneously.
◆ Logically inconsistent event.
◆ Physically dangerous event.

15
 Arithmetic Logic Unit (ALU)

❑ ALU is a purely combinatorial device:

◆ It has no memory or internal storage.
❑ It has 2 input vectors:
◆ These may be called the A- and B-vector or the R- and S-vector
◆ The inputs are as wide as the registers/system bus (e.g., 16, 32
bits)
❑ It has 1 output vector
◆ Usually denoted F

16
Arithmetic Logic Unit (ALU) (contd..)

Sample functions performed by the ALU

• F = A+B F = A+B+1
• F = A-B F = A-B-1
• F = A and B F = A or B
• F = not A F = not B
• F = not A + 1 F = not B + 1
• F = (not A) and BF = A and (not B)
• F = A xor B F = not (A xor B)
•F=A F=B

17
Arithmetic Logic Unit (ALU) (contd..)

ALU is basically a black-box

A, B Inputs purely combinatorial logic(AND/OR/

NOT/NAND/NOR etc) inside the
ALU
Add
--no registers
A B
Sub
ALU
control ALU Carry in
lines

XOR

Output F

18
 Performing an arithmetic operation
Add the contents of registers R1 and R2 and place the result in R3.
That is: R3 = R1 + R2

1. Place the contents of register R1 into the Y register in the first

clock cycle.
2. Place the contents of register R2 onto the bus in the second
clock cycle.
Both inputs to the ALU are now valid. Select register Y, and
assert the ALU command F=A+B.
3. In the third clock cycle, Z register has latched the output of the
ALU. Thus the contents of the Z register can be copied into
register R3.

19
 Performing an arithmetic operation (contd..)

Instruction
PC Control
decoder and
Signals
control logic
Address
lines
MAR
Memory
bus
Clock cycle 1:
Data
MDR IR R1out, Yin
lines

Y
Constant 4 R1

R
Select MUX
R
Add
A B
ALU Sub R( n - 1 )
control ALU
lines
Carry-in
XOR TEMP

20
 Performing an arithmetic operation (contd..)

Instruction
PC Control
decoder and
Signals
control logic
Address
lines
MAR
Memory
bus
Clock cycle 2:
Data
MDR IR R2out, SelectY,
lines Add, Zin
Y
Constant 4 R1

R
Select Y MUX
R
Add=1
A B
ALU Sub R( n - 1 )
control ALU
lines
Carry-in
XOR TEMP

21
 Performing an arithmetic operation (contd..)

Instruction
PC Control
decoder and
Signals
control logic
Address
lines
MAR
Memory
bus
Clock cycle 3:
Data
MDR IR Zout, R3in
lines

Y
Clock cycle 4:
Constant 4 R1
R3 has the sum.
R
SelectY MUX
R
Add
A B
ALU Sub R( n - 1 )
control ALU
lines
Carry-in
XOR TEMP

22
Performing an arithmetic operation (contd..)

Clock Cycle 1:
R1out, Yin (Y=R1)
Clock Cycle 2:

R2out, SelectY, Add, Zin (Z = R1+R2)

Clock Cycle 3:

Zout, R3in (R3=Z)

23
 Fetching a word from memory

❑ Processor has to specify the address of the memory location

where this information is stored and request a Read
operation.
❑ Processor transfers the required address to MAR.
◆ Output of MAR is connected to the address lines of the
memory bus.
❑ Processor uses the control lines of the memory bus to
indicate that a Read operation is needed.
❑ Requested information are received from the memory and
are stored in MDR.
◆ Transferred from MDR to other registers.

24
 Fetching a word from memory (contd..)
Connections for register MDR
Memory-bus
data lines MDRoutE MDRout bus

MDR

MDR inE MDRin

MDRoutE and MDRinE control MDRout and MDRin control

connection to external bus. connection to internal bus.

25
 Fetching a word from memory (contd..)

❑ Timing of the internal processor operations must be

coordinated with the response time of memory Read
operations.
❑ Processor completes one internal data transfer in one clock
cycle.
❑ Memory response time for a Read operation is variable and
usually longer than one clock cycle.
◆ Processor waits until it receives an indication that the
requested Read has been completed.
◆ Control signal Memory Function Completed (MFC) is used for
this purpose.
◆ MFC is set to 1 by the memory to indicate that the contents of
the specified location have been read and are available on the
data lines of the memory bus.

26
 Fetching a word from memory (contd..)

MOVE (R1), R2
1. Load the contents of Register R1 into MAR.
2. Start a Read operation on the memory bus. Steps can be performed
3. Wait for MFC response from the memory. separately, some may be
4. Load MDR from the memory bus. combined.
5. Load the contents of MDR into Register R2.

1. Steps 1 and 2 can be combined.

- Load R1 to MAR and activate Read control signal simultaneously.
2. Steps 3 and 4 can be combined.
- Activate control signal MDRinE while waiting for response from
the memory MFC.
3. Last step loads the contents of MDR into Register R2.

Hence, Memory Read operation takes 3 steps.

27
 Fetching a word from memory (contd..)

MOVE (R1) , R2:Memory operation takes 3 steps.

Step 1:
- Place R1 onto the internal processor bus.
- Load the contents of the bus into MAR.
- Activate the Read control signal.
- R1out, MARin, Read.
Step 2:
- Wait for MFC from the memory.
- Activate the control signal to load data from external bus to MDR.
- MDRinE, WMFC
Step 3:
- Place the contents of MDR onto the internal processor bus.
- Load the contents of the bus into Register R2.
- MDRoutI, R2in

28
 Storing a word into memory

MOVE R2, (R1): Memory operation takes 3 steps.

Step 1:
- Place R1 onto the internal processor bus.
- Load the contents of the internal processor bus into MAR.
- R1out, MARin.
Step 2:
- Place R2 onto the internal processor bus.
- Load the contents of the internal processor bus into MDR.
- Activate Write operation.
- R2out, MDRin, Write
Step 3:
- Place the contents of MDR into the external memory bus.
- Wait for the memory write operation to be completed MFC.
- MDRoutE, WMFC

29
 Execution of a complete instruction
Add the contents of a memory location pointed to by Register R3
to register R1.
ADD (R3), R1

To execute the instruction we must execute the following tasks:

1. Fetch the instruction.

2. Fetch the operand (contents of the memory location pointed to by R3.)
3. Perform the addition.
4. Load the result into R1.

30
 Execution of a complete instruction
Task 1: Fetch the instruction
Recall that:
- PC holds the address of the memory location which has the next
instruction to be executed.
- IR holds the instruction currently being executed.
Step 1
- Load the contents of PC to MAR.
- Activate the Read control signal.
- Increment the contents of the PC by 4.
- PCout, MARin, Read, Select4, Add, Zin.
Step 2
- Update the contents of the PC.
- Copy the updated PC to Register Y (useful for Branch instructions).
- Activate the control signal to load data from external bus to MDR
- Wait for MFC from memory.
- Zout, PCin, Yin, MDRinE ,WMFC
Step 3
- Place the contents of MDR onto the bus.
- Load the IR with the contents of the bus.
- MDRout, IRin

31
 Execution of a complete instruction (contd..)
Task 2. Fetch the operand (contents of memory pointed to by R3.)
Task 3. Perform the addition.
Task 4. Load the result into R1.

Step 4: - Place the contents of Register R3 onto internal processor bus.

- Load the contents of the bus onto MAR.
- Activate the Read control signal.
- R3out, MARin, Read
Step 5: - Place the contents of R1 onto the bus.
- Load the contents of the bus into Register Y (Recall one operand in Y).
- Wait for MFC.
- R1out, Yin, MDRinE ,WMFC
Step 6: - Load the contents of MDR onto the internal processor bus.
- Select Y, and perform the addition.
- Place the result in Z.
- MDRout, SelectY, Add, Zin.
Step 7: - Place the contents of Register Z onto the internal processor bus.
- Place the contents of the bus into Register R1.
- Zout, R1in

32
Execution of a complete instruction (contd..)

ADD (R3), R1

Step Action

1 PC out , MAR in ,Read, Select4, Add, Z in

2 Z out , PC in , Y in , WMF C
3 MDR out , IR in
4 R3 out , MAR in , Read
5 R1 out , Y in , WMF C
6 MDR out ,SelectY, Add, Z in
7 Z out , R1 in , End

Control sequence of instruction execution

33
 Branch instructions

❑ Recall that the updated contents of the PC are copied into

Register Y in Step 2.
◆ Not necessary for ADD instruction, but useful in BRANCH
instructions.:
◆ Branch target address is computed by adding the updated
contents of the PC to an offset.
❑ Copying the updated contents of the PC to Register Y
speeds up the execution of BRANCH instruction.
❑ Since the Fetch cycle is the same for all instructions, this
step is performed for all instructions.
◆ Since Register Y is not used for any other purpose at that time
it does not have any impact on the execution of the instruction.

34
Unconditional Branch instructions

Select_Y

35
Conditional Branch instructions

36
 Control sequence writing constraints
1- it is not allowed to activate input (Rin) and
output(Rout) gating signals of a specific register in
the same step.
2- it is not allowed to execute read and write
operations for the memory in the same step.
3- it is not allowed to execute read/write operations
and WMFC in the same step.
4- it is not allowed to activate the output gating
signals of two registers on the bus at the same time.
37
 Multiple-bus organization

❑ Simple single-bus structure:

◆ Results in long control sequences, because only
one data item can be transferred over the bus
in a clock cycle.
❑ Most commercial processors provide multiple
internal paths to enable several transfers to take
place in parallel.
◆ Multiple-bus organization.

38
 Multiple bus organization (Three-bus
organization)
Incrementer
Bus A Bus B Bus C

PC

Register
file

Constant
MUX A
4

ALU R

Instruction
decoder

IR

MDR Memory data lines

MAR Memory address lines

39
 Multiple bus organization (contd..)

❑ Three-bus organization to connect the registers and the ALU

of a processor.
❑ All general-purpose registers are combined into a single block
called register file.
◆ Register file has three ports.
◆ Two outputs ports connected to buses A and B, allowing the
contents of two different registers to be accessed simultaneously,
and placed on buses A and B.
◆ Third input port allows the data on bus C to be loaded into a third
register during the same clock cycle.
❑ Inputs to the ALU and outputs from the ALU:
◆ Buses A and B are used to transfer the source operands to the A
and B inputs of the ALU.
◆ Result is transferred to the destination over bus C.

40
 Multiple bus organization (contd..)

❑ ALU can also pass one of its two input operands unmodified
if needed:
◆ Control signals for such an operation are R=A or R=B.
❑ Three bus arrangement obviates the need for Registers Y
and Z in the single bus organization.
❑ Incrementer unit:
◆ Used to increment the PC by 4.
◆ Source for the constant 4 at the ALU multiplexer can be used
to increment other addresses such as the memory addresses in
multiple load/store instructions.

41
Multiple bus organization (contd..)

Three operand instruction: ADD R4, R5, R6

Step Action

1 PC out , R=B, MAR in , Read, IncPC

2 WMF C
3 MDR outB , R=B, IR in

4 R4 , R5 , SelectA, Add, R6 , End

outA outB in

1. Pass the contents of the PC through ALU and load it into MAR.
Increment PC.
2. Wait for MFC.
3. Load the data received into MDR and transfer to IR through ALU.
4. Execution of the instruction is the last step.

42
 Control unit

❑ To execute instructions the processor must generate the

necessary control signals in proper sequence.
❑ Hardwired control:
◆ Control unit is designed as a finite state machine.
◆ Inflexible but fast.
◆ Appropriate for simpler machines (e.g. RISC machines)
❑ Microprogrammed control:
◆ Flexible, but slow.
◆ Appropriate for complex machines (e.g. CISC machines)

43
 Hardwired control

Step Action

1 PC out , MAR in , Read, Select4, Add, Z in

2 Z out , PC in , Y in , WMF C
3 MDR out , IR in
4 R3 out , MAR in , Read
5 R1 out , Y in , WMF C
6 MDR out , SelectY, Add, Z in
7 Z out , R1 in , End

•Each step in this sequence is completed in one clock cycle.

•A counter may be used to keep track of the control steps.
•Each state or count, of this counter corresponds to one control step.

44
 Hardwired control (contd..)

❑ Required control signals are determined by the following

information:
◆ Contents of the control step counter.
• Determines which step in the sequence.
◆ Contents of the instruction register.
• Determines the actual instruction
◆ Contents of the condition code flags.
• Used for example in a BRANCH instruction.
◆ External input signals such as MFC.

45
 Hardwired control (contd..)
Control unit organization

CLK Control step

Clock counter

•Control unit consists of

External a decoder/encoder block to
inputs
accept the following inputs:
Decoder/
IR - Control step counter.
encoder
- Instruction Register. IR
Condition
codes - Condition codes
- External inputs.
•Generates control signals.

Control signals

46
Hardwired control (contd..)
CLK
Clock Control step Reset
counter

Separate signal line for each step

Step decoder
Separate signal line for
Combines inputs to generate
each instruction T 1 T2 Tn
control signals
INS 1
External
INS 2 inputs
Instruction
IR Encoder
decoder
Condition
codes
INS m

Run End

Control signals

47
 Hardwired control (contd..)

Control signals such as Zin, PCout, ADD are generated by encoder block

Suppose if Zin is asserted:

- During T1 for all instructions.
- During T6 for ADD instruction.
- During T4 for unconditional BRANCH instruction
- ..............
BRANCH ADD

T4 T6

T1

Z in = T1 + T6 . ADD + T4 .BRANCH + .....

48
 Hardwired control (contd..)

❑ Control hardware can be viewed as a state machine:

◆ Changes state every clock cycle depending on the contents of
the instruction register, condition codes, and external inputs.
❑ Outputs of the state machine are control signals:
❑ Sequence of control signals generated by the machine is
determined by wiring of logic elements, hence the name
“hardwired control”.
❑ Speed of operation is one of the advantages of hardwired
control is its speed of operation.
❑ Disadvantages include:
◆ Little flexibility.
◆ Limited complexity of the instruction set it can implement.

49
 Microprogrammed control

❑ Hardwired control generates control signals using:

◆ A control step counter.
◆ Decoder/encode circuit.
❑ Microprogrammed control:
◆ Control signals are generated by a program
similar to machine language programs.

50
 Microprogrammed control (contd..)

Control Word (CW) is a word whose individual bits represent various

control signals.
Control Signals:
Step Action PCout
PCin
MARin
1 PC out , MAR in , Read, Select4, Add, Z in Read
MDRout
2 Z out , PC in , Y in , WMF C
IRin
3 MDR out , IR in Yin
SelectY
4 R3 out , MAR in , Read Select4
5 R1 out , Y in , WMF C Add
Zin
6 MDR out , SelectY, Add, Z in Zout
7 Z out , R1 in , End R1out
R1in
At every step, some control signals R3out
are asserted (=1) and all others are 0. WMFC
End ......

51
 An example of a microroutine in Bit-Patterns Format

MDR out
in

WMFC
Select
PC out

R1 out

R3 out
Read
Micro -

MAR

R1 in
PC in

Z out

End
Add
IR in
Y in

Z in
instruction
Bit-Patterns Format

1 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0
2 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0
3 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
4 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0
5 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0
6 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1

•At every step, a Control Word needs to be generated.

•Every instruction will need a sequence of CWs for its execution.
•Sequence of CWs for an instruction is the microroutine for the instruction.
•Each CW in this microroutine is referred to as a microinstruction.

(SelectY is represented by Select=0, & Select4 by Select=1)

52
 Microprogrammed control (contd..)

❑ Every instruction will have its own microroutine

which is made up of microinstructions.
❑ Microroutines for all instructions in the instruction
set of a computer are stored in a special memory
called Control Store.
❑ Recall that the Control Unit generates the control
signals:
◆ Sequentially reading the CWs of the
corresponding microroutine from the control
store.

53
 Microprogrammed control (contd..)

Basic organization of a microprogrammed control unit.

•Microprogram counter (mPC) is used to

Starting read CWs from control store sequentially.
IR address
generator •When a new instruction is loaded into IR,
Starting address generator generates the
starting address of the microroutine.
•This address is loaded into the mPC.
mPC is automatically incremented by the
Clock mP C
clock, so successive microinstructions are
read from the control store.

Control
store CW

54
 Microprogrammed control (contd..)

❑ Basic organization of the microprogrammed control

unit cannot check the status of condition codes or
external inputs to determine what should be the next
microinstruction.
❑ Recall that in the hardwired control, this was handled
by an appropriate logic function.
❑ How to handle this in microprogrammed control:
◆ Use conditional branch microinstructions.
◆ These microinstructions, in addition to the branch
address also specify which of the external inputs,
condition codes or possibly registers should be
checked as a condition for branching.

55
 Microroutine for the instruction (Branch < 0)

Address Microinstruction

0 PC out , MAR in , Read, Select4, Add, Z in

Fetch BRANCH<0 instruction,
1 Z out , PC , Y in , WMF C
in
microroutine is at address 25.
2 MDR out , IR in
3 Branch to starting address of appropriate microroutine Branch to address 25.
. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ... ..
25 If N=0, then branch to microinstruction 0 Test the N bit of the condition
26 Offset-field-of-IR , SelectY, Add, Z in codes
If 0, go to 0 and get new instr.
out

27 Z out , PC in , End Else execute microinstruction

located at 26 and put the branch
target address into Register Z.
(Microinstruction at location 27).

Address 25 is the output of starting address generator and is loaded

into the microprogram counter (mPC).

56
Microprogrammed control (contd..)
Control Unit with Conditional Branching in the Microprogram

External
inputs

Starting and
branch address Condition
IR codes
generator

Starting and branch

address generator instead
of starting address
Clock mPC generator.

Control
store CW

57
 Microprogrammed control (contd..)

❑ Starting and branch address generator accepts as inputs:

◆ Contents of the Instruction Register IR (as before).
◆ External inputs
◆ Condition codes
❑ Generates a new address and loads it into microprogram
counter (mPC) when a microinstruction instructs it do so.
❑ mPC is incremented every time a microinstruction is fetched
except:
◆ New instruction is loaded into IR, mPC is loaded with the
starting address of the microroutine for that instruction.
◆ Branch instruction is encountered and branch condition is
satisfied, mPC is loaded with the branch address.
◆ End instruction is encountered, mPC is loaded with the address
of the first CW in the microroutine for the instruction fetch
cycle.

58
 Microprogrammed control (contd..)
Microinstruction format
•Simple approach is to allocate one bit for each control signal
- Results in long microinstructions, since the number of control
signals is usually very large.
- Few bits are set to 1 in any microinstruction, resulting in a poor
use of bit space.

•Reduce the length of the microinstruction by taking advantage of

the fact that most signals are not needed simultaneously, and many
signals are mutually exclusive.

•For example:
- Only one ALU function is active at a time.
- Source for a data transfer must be unique.
- Read and Write memory signals cannot be active simultaneously.

59
 Microprogrammed control (contd..)
Microinstruction format
•Group mutually exclusive signals in the same group.
•At most one microperation can be specified per group.
•Use binary coding scheme to represent signals within a
group.

Examples:
•If ALU has 16 operations, then 4 bits can be sufficient.
•Group register output signals into the same group, since only one of
these signals will be active at any given time (Why?)
If the CPU has 4 general purpose registers, then PCout, MDRout, Zout,
Offsetout, R0out, R1out, R2out, R3out and Tempout can be placed in a single
group, and 4 bits will be needed to represent these.

60
 Microprogrammed control (grouping mechanizm)
Microinstruction

F1 F2 F3 F4 F5

F1 (4 bits) F2 (3 bits) F3 (3 bits) F4 (4 bits) F5 (2 bits)

0000: No transfer 000: No transfer 000: No transfer 0000: Add 00: No action
0001: PC out 001: PC in 001: MAR in 0001: Sub 01: Read
0010: MDR out 010: IR in 010: MDR in 10: Write •Each group occupies a
0011: Z out 011: Z in 011: TEMP in
0100: R0 out 100: R0 in 100: Y in 1111: XOR large enough field to
0101: R1 out 101: R1 in
16 ALU
represent all the signals.
0110: R2 out 110: R2 in
0111: R3 out 111: R3 in
functions •Most fields must include
1010: TEMP out one inactive code, which
1011: Offsetout specifies no action.
•All fields do not have to
F6 F7 F8 include inactive code.

F6 (1 bit) F7 (1 bit) F8 (1 bit)

0: SelectY 0: No action 0: Continue

1: Select4 1: WMFC 1: End

61
 Vertical and Horizontal Organization

In vertical organization :
• Each microinstruction contains a small number of
control functions leading to more microinstructions
required for the execution of each instruction.
• results in slower operating speeds.

• In horizontal organization :
• Many resources can be controlled with a single
instruction leading into small number of microinstructions
required for the execution of each instruction.
• require that the CPU structure allows
parallel use of resources.
• results in higher operating speed
62
END

63