COMPUTER ORGANIZATION AND

ARCHITECTURE
Dr.M.Sindhuja
Assistant Professor(Senior Grade)
School of Electronics
VIT, Chennai
MODULE 1
 OVERVIEW OF IAS COMPUTER
• First-generation computer, known as the IAS computer

• A fundamental design approach first implemented in the IAS computer is known as

the stored-program concept.

• This idea is attributed to the mathematician John von Neumann

• In 1946, Von Neumann and his colleagues began the design of a new stored-program
computer, now referred to as the IAS computer, at the Institute for Advanced Studies,
Princeton.

• Nearly, all modern computers still use this stored-program concept.

 STORED PROGRAM CONCEPT
This concept has three main principles
• Program and data can be stored in the same memory.

• The computer executes the program in sequence as directed by the instructions

in the program.

• program can modify itself when the computer executes the program.
 INSTRUCTION FORMAT
• The basic unit of information i.e. the amount of information that can be
transferred between the main memory and CPU in one step is a 40-bit word

• The memory has a capacity of 212 = 4096 words.

• A word stored in the memory can represent either instruction or data.

• Data
 INSTRUCTION FORMAT
Instructions
• IAS instructions are 20 bits long, so that two instructions can be stored in
each 40-bit memory location.
• An instruction consists of two parts,:
• an 8-bit opcode (operation code), which defines the operation to be
performed (add, subtract, etc.) and
• 12-bit address part, which can identify any of 212 memory locations
that may be used to store an operand of the instruction.
STRUCTURE OF IAS COMPUTER
 STRUCTURE OF IAS COMPUTER
• Memory buffer register (MBR): Contains a word to be stored in memory or sent to
the I/O unit, or is used to receive a word from memory or from the I/O unit.

• Memory address register (MAR): Specifies the address in memory of the word to
be written from or read into the MBR.

• Instruction register (IR): Contains the 8-bit opcode instruction being executed.

• Instruction buffer register (IBR): Employed to hold temporarily the right-hand

instruction from a word in memory.

• Program counter (PC): Contains the address of the next instruction pair to be
fetched from memory
 Von-Neumann Bottleneck

• The CPU has to wait longer to obtain a data-word from the memory than from
its registers, because the registers are very fast and are logically placed inside the
processor (CPU).

• This CPU-memory speed disparity is referred to as Von-Neumann bottleneck

 HARVARD ARCHITECTURE
•named from Harvard Mark I rely-based computer

•It wasn't so modern as the computer from von Neumann team. But it introduced a
slightly different architecture.

• Separate memory for data and instructions

•This concept is called HARVARD ARCHITECTURE

• It was basically developed to overcome the bottleneck of Von Neumann’s Architecture

DESIGN OF HARVARD ARCHITECTURE
In Harvard architecture, there are separate buses for both in
struction and data.
Types of Buses:
Data Bus: It carries data among the main memory system,
processor, and I/O devices.
Data Address Bus: It carries the address of data from the p
rocessor to the main memory system.
Instruction Bus: It carries instructions among the main
memory system, processor, and I/O devices.
Instruction Address Bus: It carries the address of
instructions from the processor to the main memory system
.
 ADVANTAGES
• Increase the performance by access program and data memory simultaneously

• Both memory can use different cell size

•Due to use of different buses for instruction and data, less chance of data
corruption

DISADVANTAGES
•Two buses for control unit is complicated and expensive

•Impossible to modify program by itself

 APPLICATIONS

 Von Neumann Architecture used in

- Personal computers
- Laptops and
-Workstations

Harvard Architecture used in

-Microprocessors and
-Signal processing
CISC AND RISC ARCHITECTURES
 CISC ARCHITECTURE
 A complete instruction set of processor is often referred to as the instruction set architecture (ISA).

The design of instruction set is the most important aspect of computer architecture.

The instruction set chosen for particular computer determines the way that machine language programs are
constructed.

CISC

In early days of computer history (before 1980s), most computer families started with simple instruction set,
due to high cost of hardware.

Then the digital hardware cost has dropped due to advent of ICs and the software cost has gone up steadily
in the past three decades.

Also, the semantic gap between HLL (high-level language) and computer architecture has widened.

As the result of these, more and more functions have been built into hardware, making the instruction set
very large and complex.
CISC SCENARIO
The goal of complex instruction set is,
 to reduce the size of the compiled program (machine
language) with limited number of instructions.

main memory space is small and low cost

lesser the number of instructions in a (compiled) program,

the lesser is the time spent by the CPU for fetching
instructions leads to decreases CPU execution time

Highly efficient compiler is required to use the powerful

instructions more frequently while translating the high level
language program into a machine language program.

Hence, the system software (compiler) becomes huge in

order to generate a small object code.

Examples : Intel’s pentium and VAX 11/780

Major characteristics of CISC

A large number of instruction types used – typically from 100 to 250 instructions.

A large number of addressing modes used- typically from 5 to 15 different modes.

Some instructions that perform specialized tasks are used infrequently.

Variable-length instruction formats.

Small number of general-purpose registers (GPRs) – typically 8-24 GPRs.

Clock per instruction (CPI) lies between 2 and 15.

Mostly micro-programmed control units.

Most instructions manipulate operands in memory.

Demerits of CISC machines

CPU complexity:
The micro-programmed control unit design becomes complex since the instruction set is large.

 System size and cost:

Due to complexity of the CPU, a lot of hardware circuitry is used in the system. Thus, the hardware
cost of the system and the power consumption have increased.

Clock per instruction (CPI):

Due to increased hardware circuitry, the propagation delays are more and the number of clock periods
needed for each instruction execution is large and hence the overall execution time is reduced.

Reliability:
As heavy hardware is prone to frequent failures, the reliability of the system degrades.

Maintainability:
Since there are a large number of huge circuits, troubleshooting and detecting a fault is tough task.
 RISC ARCHITECTURE

We started with RISC instruction sets and gradually moved to CISC instruction sets during the 1980s.

After two decades of using CISC machines, computer scientists realized that only 25% of instructions
are frequently used.

Gradually VLSI (Very Large Scale Integration) technology has been invented, which offers design of
very small-size chips (processor on a chip) with reasonable cost.

Thus, we can replace micro-store, which earlier occupied about 70% of chip area, with registers.

There was increased difference between CPU and memory speeds and complex instructions were not
used by new compilers in CISC machines.

These lead to the new concept of load/store architecture called RISC

RISC SCENARIO
Major characteristics of RISC
Relatively few number of instruction types—typically less than100 instructions.

Relatively few addressing modes—typically less than or equal to 5.

 Fixed-length, easily decoded instruction formats.

Mostly split data cache and instructions cache

 Most operations should be register to register

– Memory operands are accessed only using Load and Store instructions.
– All operands involved in an arithmetic or logic operation must either be in processor registers, or one of the
operands may be given explicitly within the instruction word.

For example,
RISC instruction set may include only one or two ADD instructions (e.g., integer add, add with carry); the
VAX has 25 different ADD instructions.
 All operations are executed within registers of the CPU.

One instruction per cycle

Mostly hardwired control units rather than microprogrammed control

Examples: Power PC, ARM, Intel 860, MIPS series, ARM Processor

Demerits of RISC

• Difficult to program at assembly level

• No solution for floating point numbers

• Lacks some sophisticated instructions found in CISC processors

• Several RISC instructions may be needed to replace one CISC instruction, which results in longer
programs

• Performance is intimately tied to compiler optimisation

• More error-prone and less flexible hardwired control units

 Comparison: CISC and RISC
• RISC is good in environments requiring
— small size.
— low power consumption.
— low heat dissipation.
• On modern-day general-purpose machines, RISC and CISC have converged to an
extent.
• For example, Intel’s Pentium series, the VAX 9000 and Motorola 88100 are built
with mixed features taken from both the RISC and CISC camps.
• Modern RISCs (ARM, Sun SPARC, HP PA-RISC) more complex than forebears.
• Modern CISCs incorporate many features learned from RISC