Stanford University

Department of Electrical Engineering

EE 410
INTEGRATED CIRCUIT
FABRICATION LABORATORY
Professor Krishna C. Saraswat
Final Project: CIS/CMOS-II Process and Device
Modeling/Fabrication/Characterization
Deji Akinwande (dejia)
Aaron Gibby (agibby)
Jinendra Raja Jain (jrjain)
Saeroonter Oh (sroonter)
Shiyu Sun (sysun)
Gloria Wong (gloriamt)
March 18, 2005
Contents
1 Introduction 1
2 Analytical Calculations 3
2.1 Field and Gate Oxide Thicknesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Ion Implant Proles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Junction Depths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Sheet Resistivities of Junctions and Poly-Silicon Gates . . . . . . . . . . . . . . . . . 8
2.5 Threshold Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 TSUPREM-IV Simulation Results 13
3.1 Field and Gate Oxide Thicknesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Ion Implant Proles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Junction Depths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 Sheet Resistivities of Junctions and Poly-Silicon Gates . . . . . . . . . . . . . . . . . 14
3.5 Threshold Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 Analysis/Simulation Results Comparison and Discussion 23
4.1 Field and Gate Oxide Thicknesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2 Ion Implant Proles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3 Junction Depths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4 Sheet Resistances of Junctions and Poly-Silicon Gate . . . . . . . . . . . . . . . . . . 24
4.5 Threshold Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 MEDICI Simulation Results 26
5.1 pMOS Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6 Characterization 29
6.1 Device Test Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1.1 nMOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1.2 pMOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.1.3 MOSCAPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.1.4 Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.2 Process Test Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.2.1 Sheet Resistivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.2.2 Contact Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.2.3 Contact Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.2.4 Continuity and Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.3 SEM Test Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7 Discussion 97
7.1 Finding The Fault Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.2 pMOSFET Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.3 Comparison of Wafers B2 and B5: Gate Etch . . . . . . . . . . . . . . . . . . . . . . 98
7.4 Suggested Process Improvements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.4.1 Wafer B1 Sheet Resistivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.4.2 General Process Improvements . . . . . . . . . . . . . . . . . . . . . . . . . . 102
8 Conclusions and Comments 103
9 Appendices 105
9.1 Appendix A: CIS/CMOS-II Process Flow by Cross-Section . . . . . . . . . . . . . . 105
9.2 Appendix B: Analytical Calculations (Handwritten Notes) . . . . . . . . . . . . . . . 107
9.3 Appendix C: MATLAB Simulation Code . . . . . . . . . . . . . . . . . . . . . . . . . 134
9.3.1 nMOS Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
9.3.2 nMOS Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
9.3.3 pMOS Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
9.3.4 pMOS Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
9.3.5 nMOS Metal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
9.3.6 nMOS Poly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
9.3.7 pMOS Metal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
9.3.8 pMOS Poly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
9.4 Appendix D: TSUPREM-IV Simulation Code . . . . . . . . . . . . . . . . . . . . . . 144
9.4.1 Substrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
9.4.2 Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
9.4.3 Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
9.4.4 nMOS Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
9.4.5 pMOS Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
9.4.6 nMOS Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
9.4.7 pMOS Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
9.4.8 nMOS Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
9.4.9 nMOS Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
9.4.10 pMOS Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
9.4.11 pMOS Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
9.4.12 nMOS Metal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
9.4.13 nMOS Poly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
9.4.14 pMOS Metal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
9.4.15 pMOS Poly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
9.5 Appendix E: MEDICI Simulation Code . . . . . . . . . . . . . . . . . . . . . . . . . 164
9.6 Appendix F: Individual Group Member Contributions . . . . . . . . . . . . . . . . . 173
References 174
List of Figures
1 CIS/CMOS-II Cross-Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Dopant Proles for NMOS Cross-Sections . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Dopant Proles for PMOS Cross-Sections . . . . . . . . . . . . . . . . . . . . . . . . 10
4 I
d
vs. V
d
, 100m, pMOS Device Simulation . . . . . . . . . . . . . . . . . . . . . . . 26
5 I
d
vs. V
d
, 20m, pMOS Device Simulation . . . . . . . . . . . . . . . . . . . . . . . . 27
6 log(I
d
) vs. V
g
, 100m, pMOS Device Simulation . . . . . . . . . . . . . . . . . . . . . 27
7 log(I
d
) vs. V
g
, 20m, pMOS Device Simulation . . . . . . . . . . . . . . . . . . . . . 28
8 Test Pad Conguration for nMOSFET Contacts . . . . . . . . . . . . . . . . . . . . 30
9 nMOS Short Channel Eect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10 nMOS Narrow Width Eect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11 nMOS Transconductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
12 nMOS Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
13 2m x 2m nMOS I
D
V
D
Characteristics . . . . . . . . . . . . . . . . . . . . . . . 34
14 2m x 1.5m nMOS I
D
V
D
Characteristics . . . . . . . . . . . . . . . . . . . . . . 34
15 1.5m x 1.5m nMOS I
D
V
D
Characteristics . . . . . . . . . . . . . . . . . . . . . 35
16 1.5m x 1m nMOS I
D
V
D
Characteristics . . . . . . . . . . . . . . . . . . . . . . 35
17 100m x 100m nMOS I
D
V
D
Characteristics . . . . . . . . . . . . . . . . . . . . 36
18 100m x 100m nMOS Gate-Drain Short I
D
V
D
Characteristic . . . . . . . . . . . 37
19 100m x 20m nMOS Gate-Source Short I
D
V
D
Characteristic . . . . . . . . . . . 38
20 100m x 20m Four-Node nMOS Short I
D
V
D
Characteristic . . . . . . . . . . . . 39
21 PMOS1 I
d
vs. V
d
plot used in pMOS analysis . . . . . . . . . . . . . . . . . . . . . . 41
22 PMOS1 I
d
vs. V
g
Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
23 PMOS1 log(I
d
) vs. V
g
Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
24 PMOS2 I
d
vs. V
d
plot used in pMOS analysis . . . . . . . . . . . . . . . . . . . . . . 43
25 PMOS2 I
d
vs. V
g
Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
26 PMOS2 log(I
d
) vs. V
g
Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
27 IV Characteristics of the smallest functioning devicea 1.5 x 1 m device . . . . . . 45
28 V
t
Histogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
29 V
t
Histogram, Wafer B1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
30 V
t
Histogram, Wafer B2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
31 V
t
Histogram, Wafer B3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
32 Single Transistor g
m
Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
33 g
m
Histogram, Wafer B1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
34 Eect of Back Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
35 pMOS Subthreshold Slope Histogram . . . . . . . . . . . . . . . . . . . . . . . . . . 51
36 Breakdown Characteristics for 100x100 m PMOS Device . . . . . . . . . . . . . . . 54
37 pMOS SCE Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
38 pMOS NCE Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
39 Representative n
+
Poly/p-Well Gate MOSCAP . . . . . . . . . . . . . . . . . . . . . 59
40 Representative p
+
Poly/n-Substrate Gate MOSCAP . . . . . . . . . . . . . . . . . . 59
41 Representative Gate MOSCAP Periphery (BF) . . . . . . . . . . . . . . . . . . . . . 60
42 Representative Gate MOSCAP Periphery (DF) . . . . . . . . . . . . . . . . . . . . . 61
43 Wafer B5 (Center) - n
+
Poly/FOX/p-Well MOSCAP . . . . . . . . . . . . . . . . . . 61
44 Wafer B5 (Center) - p
+
Poly/FOX/n-Substrate MOSCAP . . . . . . . . . . . . . . . 62
45 Wafer B2 (Center) - n
+
Poly/FOX/p-Well MOSCAP . . . . . . . . . . . . . . . . . . 62
46 Wafer B2 (Center) - p
+
Poly/FOX/n-Substrate MOSCAP . . . . . . . . . . . . . . . 63
47 Wafer B1 (Center) - p
+
Poly/FOX/n-Substrate MOSCAP . . . . . . . . . . . . . . . 64
48 Wafer B2 (center) - p
+
Poly/FOX/n-Substrate MOSCAP . . . . . . . . . . . . . . . 64
49 Wafer B2 (Bottom) - p
+
Poly/FOX/n-Substrate MOSCAP . . . . . . . . . . . . . . 65
50 Representative FOX MOSCAP Periphery (BF) . . . . . . . . . . . . . . . . . . . . . 67
51 Representative FOX MOSCAP Periphery (DF) . . . . . . . . . . . . . . . . . . . . . 67
52 Wafer B3 (Center) - Metal/FOX & LTO/p-Well MOSCAP . . . . . . . . . . . . . . 68
53 Wafer B1 (Center) - Metal/FOX & LTO/n-Substrate MOSCAP . . . . . . . . . . . 68
54 Wafer B5 (Center) - Metal/LTO/p
+
Poly MOSCAP . . . . . . . . . . . . . . . . . . 70
55 Wafer B5 (Center) - Metal/LTO/n
+
Poly MOSCAP . . . . . . . . . . . . . . . . . . 70
56 Representative poly-poly Diode IV Characteristic . . . . . . . . . . . . . . . . . . . . 72
57 Poly-poly Diodes Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 72
58 Tunneling in a pn-Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
59 Four-Point Probe Test Pad Conguration . . . . . . . . . . . . . . . . . . . . . . . . 74
60 Van der Pauw Test Pad Conguration . . . . . . . . . . . . . . . . . . . . . . . . . . 75
61 Representative (1m x 30m) 4-Point Probe IV . . . . . . . . . . . . . . . . . . . . 77
62 Representative (P-well with Oxide) Van de Pauw IV . . . . . . . . . . . . . . . . . . 77
63 4-Point Probe Sheet Resistance Wafer Comparison . . . . . . . . . . . . . . . . . . . 78
64 Contact Chain Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
65 20 Contact (2m x 2m), p
+
Poly IV Characteristic . . . . . . . . . . . . . . . . . . 80
66 20 Contact (2m x 2m), n
+
Poly IV Characteristic . . . . . . . . . . . . . . . . . . 81
67 Kelvin Contact Resistance Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
68 Kelvin Contact Resistance - Representative Schottky . . . . . . . . . . . . . . . . . . 85
69 Kelvin Contact Resistance - Representative Ohmic . . . . . . . . . . . . . . . . . . . 86
70 Kelvin Contact Resistance Representative Completely Linear . . . . . . . . . . . . . 86
71 MS Contacts - Doping Dependence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
72 n
+
Active Contact - VI Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . 89
73 Current vs. Applied Voltage of Metal Lines . . . . . . . . . . . . . . . . . . . . . . . 89
74 Cross-Section of 20 m Gate Width Transistor . . . . . . . . . . . . . . . . . . . . . 91
75 Magnied Cross-Section of 20 m Gate Length Transistor . . . . . . . . . . . . . . . 92
76 Surface of Width Series Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
77 Surface of Contact Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
78 Magnied Image of Link within Contact Chains . . . . . . . . . . . . . . . . . . . . . 94
79 Surface Image of Continuity Structure: Metal over All Topography . . . . . . . . . . 94
80 Magnied Image of Continuity Structure End . . . . . . . . . . . . . . . . . . . . . . 95
81 Magnied Image of Continuity Structure Middle . . . . . . . . . . . . . . . . . . . . 95
82 Cross-Section of Minimum Dimension Device . . . . . . . . . . . . . . . . . . . . . . 96
83 Cross-Section of Wafer B2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
84 Cross-Section of Wafer B5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
85 Cross-Section of Wafer B5, 20 m Gate Length . . . . . . . . . . . . . . . . . . . . . 100
86 B1/B2 Sheet Resistance Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
List of Tables
1 CIS/CMOS-II Detailed Process Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Field Oxidation Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Sacricial/Gate Oxidation Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4 Oxide Thickness Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5 Dopant Ion Implant Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6 PMOS Source (CS 1) Implant Diusion Data . . . . . . . . . . . . . . . . . . . . . . 6
7 PMOS Channel (CS 2) Implant Diusion Data . . . . . . . . . . . . . . . . . . . . . 6
8 PMOS Metal (CS 3) Implant Diusion Data . . . . . . . . . . . . . . . . . . . . . . . 7
9 PMOS Poly (CS 4) Implant Diusion Data . . . . . . . . . . . . . . . . . . . . . . . 7
10 NMOS Source (CS 5) Implant Diusion Data . . . . . . . . . . . . . . . . . . . . . . 7
11 NMOS Channel (CS 6) Implant Diusion Data . . . . . . . . . . . . . . . . . . . . . 7
12 NMOS Metal (CS 7) Implant Diusion Data . . . . . . . . . . . . . . . . . . . . . . 7
13 NMOS Poly (CS 8) Implant Diusion Data . . . . . . . . . . . . . . . . . . . . . . . 8
14 Junction Depth Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
15 NMOS and PMOS Source/Drain Sheet Resistivity Calculations . . . . . . . . . . . . 11
16 NMOS and PMOS Poly Sheet Resistivity Calculations . . . . . . . . . . . . . . . . . 11
17 Threshold Voltage Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
18 Oxide Thickness Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
19 Junction Depth Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
20 Sheet Resistivity Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
21 Threshold Voltage Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . 14
22 Oxide Thickness Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
23 Junction Depth Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
24 Sheet Resistance Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
25 Threshold Voltage Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
26 Simulated pMOS Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
27 Sample nMOS Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
28 nMOS Analysis, Simulation, and Electrical Characterization Results . . . . . . . . . 39
29 HP4145 Setup, Low V
t
Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
30 HP4145 Setup, High V
t
Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
31 Body Eect Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
32 Extracted N
d
values, pMOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
33 Values used in determining channel mobility and Values calculated from experimental
data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
34 Sun and Plummer Model Parameters. [7] . . . . . . . . . . . . . . . . . . . . . . . . 53
35 Values used in determining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
36 MOS Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
37 MOSCAPs - Theoretical Values for C
ox
. . . . . . . . . . . . . . . . . . . . . . . . . 58
38 MOSCAP TSUPREM-IV-Extracted V
t
. . . . . . . . . . . . . . . . . . . . . . . . . . 58
39 n
+
Poly/FOX/p-Well MOSCAP Data and Calculations . . . . . . . . . . . . . . . . 65
40 n
+
Poly/FOX/p-Well MOSCAP Data and Calculations . . . . . . . . . . . . . . . . 66
41 Metal/FOX & LTO/p-Well MOSCAP Data and Calculations . . . . . . . . . . . . . 69
42 Metal/FOX & LTO/p-Well MOSCAP Data and Calculations . . . . . . . . . . . . . 69
43 Wafer B5 - Metal/LTO/Poly MOSCAPs . . . . . . . . . . . . . . . . . . . . . . . . . 71
44 Average Sheet Resistivity Measurements for Wafers 2 and 3 . . . . . . . . . . . . . . 76
45 Sheet Resistivity Analysis, Simulation, and Electrical Characterization Results . . . 78
46 Contact Chains: Wafer-to-Wafer Variation . . . . . . . . . . . . . . . . . . . . . . . . 81
47 Contact Chains: Intra-Wafer (B3) Variation . . . . . . . . . . . . . . . . . . . . . . . 82
48 Kelvin Contact Resistance Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
49 Continuity Testing Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
50 Modeled Process Flows for CIS/CMOS-II Cross-Sections . . . . . . . . . . . . . . . . 106
51 Individual Group Member Contributions - Testing/Characterization . . . . . . . . . 173
52 Individual Group Member Contributions - Report . . . . . . . . . . . . . . . . . . . 173
CIS/CMOS-II Modeling/Fabrication/Characterization 1 INTRODUCTION
1 Introduction
The CIS/CMOS-II chip is the result of a simplied 1.5m CMOS process ow designed for the
EE410 course at Stanford University. The process ow was executed in the Stanford Nanofabrica-
tion Facility (SNF), part of the Universitys Paul Allen Center for Integrated Systems.
The CIS/CMOS-II product involves n-type substrates, six (6) mask levels utilizing conventional
optical lithography with positive photoresist, 40nm gate oxides and 500nm eld oxides, dual-implant
p-well formation, amorphous poly-silicon gates, single-mask n
+
and p
+
-Source/Drain denition,
single-level aluminum/silicon metallization, 600nm PSG passivation, and non-silicided contacts.
The dice measure 8mmx16mm in area and contain 1.5m transistors, inverters, ring oscillators,
and a variety of process test structures.
Over the course of ten weeks, the EE410 CIS/CMOS-II chip was simulated, fabricated, tested
and characterized according to the prescribed EE410 process schedule [1]. Analytical calculations
of eight chip cross-sections were compared with simulations from TSUPREM-IV software. Output
from TSUPREM-IV was then used to model transistor characteristics using MEDICI software.
Upon completion of six weeks of fabrication, the fabrication, process, device and SEM test struc-
tures of CIS/CMOS-II were evaluated on ve wafers, hereafter referred to as B1-B5, along with a
test wafer. Those results, and comparisons with the calculations and simulations have been dis-
cussed in this report.
Figure 1 presents the product chip with materials and cross-sections indicated [2]. The cross-
sections are enumerated as follows: 1) PMOS Source/Drain; 2) PMOS Channel; 3) PMOS Metal;
4) PMOS Poly; 5) NMOS Source/Drain; 6) NMOS Channel; 7) NMOS Metal; and 8) NMOS Poly.
Figure 1: CIS/CMOS-II Cross-Sections
Table 1 presents the most relevant features of the CIS/CMOS-II process, along with the pa-
rameters for each step used in approximate analysis and TSUPREM-IV/MEDICI modeling.
Akinwande, Gibby, Jain, Oh, Sun, Wong 1
CIS/CMOS-II Modeling/Fabrication/Characterization 1 INTRODUCTION
Table 1: CIS/CMOS-II Detailed Process Flow
Step Specications
1. INITIALIZATION <100> Silicon, P Doping = 8 10
14
cm
3
( = 5-10 -cm)
2. BLANKET IMPLANT P
31
, Dose = 1.75 10
12
cm
2
, Energy = 100 keV, Tilt = 7

3. FIELD SiO
2
(5000

A) a. Time = 35 min, T.Start = 800

C, T.Final = 1000

C, Argon
b. Time = 10 min, Temp. = 1000

C, DryO
2
c. Time = 100 min, Temp. = 1000

C, Steam
d. Time = 10 min, Temp. = 1000

C, DryO
2
e. Time = 35 min, T.Start = 1000

C, T.Final = 800

C, Argon
4. PHOTOLITHOGRAPHY #1 Active Area
5. ETCH SiO
2
(all)
6. SACRIFICIAL SiO
2
(40 nm) a. Time = 20 min, T.Start = 800

C, T.Final = 900

C, Argon
b. Time = 5 min, Temp. = 900

C, DryO
2
c. Time = 12 min, Temp. = 900

C, Steam
d. Time = 5 min, Temp. = 900

C, DryO
2
e. Time = 15 min, T.Start = 900

C, T.Final = 800

C, Argon
7. PHOTOLITHOGRAPHY #2 P-Well
8. P-WELL DOUBLE IMPLANT a. B
11
, Dose = 5.0 10
12
cm
2
, Energy = 180 keV, Tilt = 7

b. B
11
, Dose = 1.4 10
12
cm
2
, Energy = 50 keV, Tilt = 7

9. P-WELL DRIVE-IN a. Time = 30 min, T.Start = 800

C, T.Final = 1000

C, Argon
b. Time = 60 min, Temp = 1000

C, Argon
c. Time = 20 min, T.Start = 800

C, T.Final = 1000

C, Argon
10. ETCH Sacricial SiO
2
(40 nm + 50% overetch = 60 nm)
11. GATE SiO
2
(40 nm) a. Time = 20 min, T.Start = 800

C, T.Final = 900

C, Argon
b. Time = 5 min, Temp. = 900

C, DryO
2
c. Time = 12 min, Temp. = 900

C, Steam
d. Time = 5 min, Temp. = 900

C, DryO
2
e. Time = 15 min, T.Start = 900

C, T.Final = 800

C, Argon
12. POLY-SI DEPOSITION (5000

A) Poly-silicon
13. PHOTOLITHOGRAPHY #3 Poly-silicon
14. ETCH Poly-silicon (all)
15. PHOTOLITHOGRAPHY #4 N-Select
16. N-SOURCE/DRAIN IMPLANT As
75
, Dose = 5.0 10
15
cm
2
, Energy = 100 keV, Tilt = 7

17. BLANKET IMPLANT BF

49
2
, Dose = 1.0 10
15
cm
2
, Energy = 80 keV, Tilt = 7

18. LTO DEPOSITION (6000

A) Low-Temperature Oxide
19. LTO DENSIFICATION a. Time = 30 min, T.Start = 800

C, T.Final = 950

C, Argon
b. Time = 5 min, Temp. = 950

C, DryO
2
c. Time = 30 min, Temp. = 950

C, Steam
d. Time = 5 min, Temp. = 950

C, DryO
2
e. Time = 20 min, T.Start = 950

C, T.Final = 800

C, Argon
20. PHOTOLITHOGRAPHY # 5 Contact Holes
21. ETCH SiO
2
(all)
22. AL/SI DEPOSITION (1m) Al/Si (99%/1%) Alloy
23. PHOTOLITHOGRAPHY #6 Metal
24. ETCH Al/Si Alloy (all)
Akinwande, Gibby, Jain, Oh, Sun, Wong 2
CIS/CMOS-II Modeling/Fabrication/Characterization 2 ANALYTICAL CALCULATIONS
2 Analytical Calculations
2.1 Field and Gate Oxide Thicknesses
The linear-parabolic Deal-Grove model was used to estimate oxide thicknesses [3]. Since oxides
exceed 20nm in target thickness (sacricial/gate oxides are 40nm thick), the failures of the model
for thin layers are generally avoided in this analysis. Should oxides thinner than the 20nm limit be
needed, modications to the Deal-Grove model, such as those provided by Massoud, Han & Helms,
and others, would be appropriate. Equations 1-4 present the Deal-Grove model in brief.
x
0
=
A
2
_
1 +
t +
A
2
/4B
1
_
(1)
=
x
2
i
+Ax
i
B
(2)
where
B = C
1
e

E
1
kT
(3)
B
A
= C
2
e

E
2
kT
(4)
The constants C
1
and C
2
, along with the activation energies E
1
and E
2
, are dened in [3] and used
to calculate the rate coecients A, and
B
A
.
Model parameters for the Dry O
2
and Steam ambients used during oxidations were calculated
and are provided in 9.2. Table 2 presents the Field Oxidation process in a cumulative fashion.
Table 2: Field Oxidation Process
Ambient Temperature (
o
C) Time (sec) x
0
(m) Si Consumed (m)
Dry O
2
1000 600 0.0072 0.0033
Steam 1000 6000 0.5450 0.2477
Dry O
2
1000 600 0.5463 0.2483
Table 3 presents the Sacricial/Gate Oxidation process in a cumulative fashion.
Akinwande, Gibby, Jain, Oh, Sun, Wong 3
CIS/CMOS-II Modeling/Fabrication/Characterization 2 ANALYTICAL CALCULATIONS
Table 3: Sacricial/Gate Oxidation Process
Ambient Temperature (
o
C) Time (sec) x
0
(m) Si Consumed (m)
Dry O
2
900 300 7.8684E-4 3.5766E-4
Steam 900 7200 0.0302 0.0137
Dry O
2
900 300 0.0309 0.0141
The nal FOX thickness is 546.3nm, while the target thickness is 500nm. Since eld oxide is
grown for device isolation, this variation is unimportant. However, the nal Sacricial/Gate oxide
thickness is 30.0nm, compared to the target value of 40nm. This discrepancy is more important
for device operation but its eects are not considered here.
Some of the oxidations in the CIS/CMOS-II process ow start with initial SiO
2
surface layers.
The processes shown in Tables 2 and 3 are given for oxidation of bare Silicon. Calculations for
continued oxidations account for the decrease in species diusions through pre-existing oxides.
Note: The actual process ow as performed in SNF incorporates an excess of O
2
for the sake of
safety [1]. Also, species ow rates presumed for the model and those cited in the run sheet dier.
These, along with other discrepancies, account for some portion of the dierence in calculated and
desired SiO
2
thicknesses. It should also be noted that calculations of oxide thicknesses neglect
oxidation of the Silicon surface during ramp steps. In most instances, this simplication results
in negligible error in the hand analysis. TSUPREM-IV process runs were conducted to test the
importance of the ramp steps and verify appropriateness of the ramp omission. Also note that LTO
and Thermal oxides are treated identically in this analysis.
Table 4 presents the nal total oxide thickness values for each cross-section.
Table 4: Oxide Thickness Calculations
Cross-Section 1 2 3 4 5 6 7 8
SiO
2
Thickness (m) N/A 0.0308 1.1588 0.5185 N/A 0.0308 1.1588 0.5185
2.2 Ion Implant Proles
Implant proles for both hand analysis and TSUPREM-IV simulations were modeled by symmetric
Gaussian proles. The more accurate Pearson distribution is the default model in TSUPREM-IV,
but Gaussian proles are simpler to study. The model used for implantation is derived from [3].
Equation 5 presents the Gaussian implant model.
Akinwande, Gibby, Jain, Oh, Sun, Wong 4
CIS/CMOS-II Modeling/Fabrication/Characterization 2 ANALYTICAL CALCULATIONS
C(x) =
Q

2R
P
e

(xR
P
)
2
2R
2
P
(5)
Equation 6 presents the model used for dopant evolution due to annealing (temperature cycling).
C(x, t) =
Q
_
2(R
2
P
+ 2

Dt)
e

(xR
P
)
2
2
(
R
2
P
+2
P
Dt
)
(6)
Peak range and standard deviation statistics for dopants with dierent implant energies were taken
from [3]. Table 5 presents the dopant implant data most immediately relevant.
Table 5: Dopant Ion Implant Calculations
Dopant/Region Energy (keV ) Dose (cm
2
) R
P
(m) R
P
(m)
P/Blanket 100 1.75E12 0.127 0.0461
B/P-Well 180 5E12 0.469 0.107
B/P-Well 50 1.4E12 0.171 0.0628
As/N-Source/Drain 100 5E15 0.0692 0.0261
BF
2
/Blanket 80 1E15 0.0746 0.0353
Note: As per TSUPREM-IV behavior, the BF
2
implant was treated as a Boron implant with
E

= 0.2215E and Q

= 3Q (for damage only) [4]. This correction results in appropriate range and
standard deviation statistics for the heavier implant species.
Attempts were made to include concentration-dependent diusivities as well, but the complex-
ity of dealing with enhanced portions of dopant proles precluded a reasonable treatment. The
diusivities and resulting diusion lengths resulting from these attempts can be found throughout
the hand analysis materials in 9.2.
Several points should be made with regard to the treatment of implant anneals in this work.
Reection at oxidizing Si surfaces was not considered. Any amount of dopant that diused towards
the Si-SiO
2
interface was assumed integrated into the growing oxide. Accurately considering re-
ection would require modeling of the rate of oxidation at the surface coupled with dopant ux at
the interface.
To consider masking eects, thicknesses of surface oxides and poly-Si layers were used as di-
rect osets in the calculation of implant peaks. Furthermore, individual dopant diusivities and
electronic and nuclear stopping forces were assumed constant and equal across all material layers,
Akinwande, Gibby, Jain, Oh, Sun, Wong 5
CIS/CMOS-II Modeling/Fabrication/Characterization 2 ANALYTICAL CALCULATIONS
including poly-silicon and SiO
2
.
Since the silicon surface changes location as a result of oxidation, its position was tracked
throughout the process ow for each cross section. This is necessary when considering the place-
ment of dopant proles relative to other dopants and material layers.
Finally, certain higher-order eects (e.g. dopant segregation, concentration-dependent diusiv-
ity, and oxidation-enhanced diusion (OED)) were neglected. However, as mentioned, transient-
enhanced diusion (TED) was modeled throughout the process. For Arsenic implant and diusion,
the diusivity enhancement was multiplied by a factor of 0.4 to account for vacancies-dominated
diusion mechanism [3]. Equations 7 and 8 present the TED equations used during implant anneals.
C
max
I
C

I
=
1
4a
3
C
0
I
e

E
b
E
F
kT

(7)

enh
=
4a
3
R
p
Q
d
0
I
e
E
b
+Em
kT
(8)
Tables 6-13 present the total Dt results for each cross section. The data include the nal peak
location for each dopant, considering the location of the top material surface at the time of implant.
Table 6: PMOS Source (CS 1) Implant Diusion Data
Species Peak Location (m) Final Dt (cm
2
)
Blanket P 0.127 3.2273E-10
Blanket BF
2
0.3201 2.1596E-10
Table 7: PMOS Channel (CS 2) Implant Diusion Data
Species Peak Location (m) Final Dt (cm
2
)
Blanket P 0.127 3.2273E-10
Blanket BF
2
-0.1799 2.1596E-10
Akinwande, Gibby, Jain, Oh, Sun, Wong 6
CIS/CMOS-II Modeling/Fabrication/Characterization 2 ANALYTICAL CALCULATIONS
Table 8: PMOS Metal (CS 3) Implant Diusion Data
Species Peak Location (m) Final Dt (cm
2
)
Blanket P 0.127 3.2273E-10
Blanket BF
2
-0.1809 2.1596E-10
Table 9: PMOS Poly (CS 4) Implant Diusion Data
Species Peak Location (m) Final Dt (cm
2
)
Blanket P 0.127 3.2273E-10
Blanket BF
2
-0.6809 2.1596E-10
Table 10: NMOS Source (CS 5) Implant Diusion Data
Species Peak Location (m) Final Dt (cm
2
)
Blanket P 0.127 5.9680E-10
P-Well Deep Boron 0.7005 5.8879E-10
P-Well Shallow Boron 0.4025 5.8879E-10
N-Source/Drain As 0.3147 1.9271E-11
Blanket BF
2
0.3201 5.3614E-10
Table 11: NMOS Channel (CS 6) Implant Diusion Data
Species Peak Location (m) Final Dt (cm
2
)
Blanket P 0.127 5.9680E-10
P-Well Deep Boron 0.7005 5.8879E-10
P-Well Shallow Boron 0.4025 5.8879E-10
N-Source/Drain As -0.1853 1.9271E-11
Blanket BF
2
-0.1799 5.3614E-10
Table 12: NMOS Metal (CS 7) Implant Diusion Data
Species Peak Location (m) Final Dt (cm
2
)
Blanket P 0.127 5.9680E-10
P-Well Deep Boron 0.1624 5.8879E-10
P-Well Shallow Boron -0.1356 5.8879E-10
N-Source/Drain As -0.1863 1.9271E-11
Blanket BF
2
-0.1809 5.3614E-10
Akinwande, Gibby, Jain, Oh, Sun, Wong 7
CIS/CMOS-II Modeling/Fabrication/Characterization 2 ANALYTICAL CALCULATIONS
Table 13: NMOS Poly (CS 8) Implant Diusion Data
Species Peak Location (m) Final Dt (cm
2
)
Blanket P 0.127 5.9680E-10
P-Well Deep Boron 0.1624 5.8879E-10
P-Well Shallow Boron -0.1356 5.8879E-10
N-Source/Drain As -0.6863 1.9271E-11
Blanket BF
2
-0.6809 5.3614E-10
Figures 2 and 3 illustrate the nal hand/MATLAB-simulated doping proles for the nMOS and
pMOS cross-sections, respectively.
2.3 Junction Depths
Junction depths are obtained directly from the MATLAB simulation output of Figures 2 and 3.
Table 14 presents the junction data for each cross-section.
Table 14: Junction Depth Calculations
Cross-Section 1 2 3 4 5 6 7 8
Junction Depth (m) 1.2634 N/A N/A N/A 0.5934 1.7420 1.1725 1.1811
2.4 Sheet Resistivities of Junctions and Poly-Silicon Gates
The sheet resistivity of a diused layer can be calculated according to Equation 9 [3].

S
=
1
x
j
=
1
q
_
x
j
0
[n(x) N
B
(x)] [n(x)]dx
(9)
However, analytical/numerical integration of diused proles is more complicated than necessary
Akinwande, Gibby, Jain, Oh, Sun, Wong 8
CIS/CMOS-II Modeling/Fabrication/Characterization 2 ANALYTICAL CALCULATIONS
Figure 2: Dopant Proles for NMOS Cross-Sections
Akinwande, Gibby, Jain, Oh, Sun, Wong 9
CIS/CMOS-II Modeling/Fabrication/Characterization 2 ANALYTICAL CALCULATIONS
Figure 3: Dopant Proles for PMOS Cross-Sections
Akinwande, Gibby, Jain, Oh, Sun, Wong 10
CIS/CMOS-II Modeling/Fabrication/Characterization 2 ANALYTICAL CALCULATIONS
for hand analysis. Instead, Equations 10 and 11 yield a more tractable method for calculating sheet
resistivity values for the CIS/CMOS-II process.
=
1
q (n
n
+p
p
)
(10)

S
=

x
j
(11)
Assuming Gaussian implant distributions naturally leads to the use of Irvins Curves to calculate
Source/Drain sheet resistivities. Granted, unavoidable error is present in this method, due to the
incompleteness of the proles extent into the diused regions. However, applying Irvins Curves
yields acceptable approximations. Table 15 presents the resulting sheet resistivity values for the
NMOS and PMOS Source/Drain Regions. N
B
, N
A
, and N
D
refer to the corresponding peak
concentration within the Source/Drain region. Eective conductivity values are obtain from Irvins
Curves.
Table 15: NMOS and PMOS Source/Drain Sheet Resistivity Calculations
Cross-Section N
B
(cm
3
) N
A
or N
D
(cm
3
)
_
1
cm
_
x
j
(cm)
S
_

sq.
_
NMOS S/D 6.7411E16 2.9207E20 280 0.5934E-4 60.1859
PMOS S/D 2.1046E16 1.8923E19 200 1.2634E-4 39.5758
Sheet resistivity values for the n- and p-poly-silicon layers can be approximated by using Equa-
tions 10 and 11 more directly. Grain boundaries in poly-silicon act as fast diusion paths along
which atoms travel more rapidly than in bulk crystalline material [3]. Hence, a reasonable approx-
imation for sheet resistivity calculation is the uniform doping of poly-silicon at the peak concen-
tration. The treatment here assumes that charge carrier mobility in the poly material is half that
in crystalline Silicon [5]. Table 16 presents the resulting sheet resistivity data.
Table 16: NMOS and PMOS Poly Sheet Resistivity Calculations
Cross-Section N
A
or N
D
(cm
3
) Dominant
_
cm
2
sec
_

_
1
cm
_
x
j
(cm)
S
_

sq.
_
NMOS Poly 1E19 131.5 21.04 0.4721E-4 100.6747
PMOS Poly 1E19 36 57.6 0.4271E-4 367.7422
Akinwande, Gibby, Jain, Oh, Sun, Wong 11
CIS/CMOS-II Modeling/Fabrication/Characterization 2 ANALYTICAL CALCULATIONS
2.5 Threshold Voltages
Equations 12-15 are used to calculate threshold voltages for the CIS/CMOS-II cross-sections.
V
t,n
=
MS

Q
SS
C
ox
+ 2
F
+
K
S
K
ox
x
ox
_
4qN
B
K
S

0
(
F
) (12)
V
t,p
=
MS

Q
SS
C
ox
+ 2
F

K
S
K
ox
x
ox
_
4qN
B
K
S

0
(
F
) (13)

F,n
=
kT
q
ln
N
A
n
i
(14)

F,p
=
kT
q
ln
N
D
n
i
(15)
The doping concentration values at the Silicon surface are used to calculate the corresponding
threshold voltages. This introduces some error, since dopant distributions are non-uniform. Q
SS
is taken equal to 5E10 cm
2
, the value used for TSUPREM-IV simulations. The aluminum work
function,
M
, is equal to 4.05eV, while the Silicon electron anity, is 4.10eV. An intrinsic
carrier concentration, n
i
of 1.45E10 cm
3
is used. Table 17 presents the resulting threshold voltage
calculations.
Table 17: Threshold Voltage Calculations
Cross-Section Surface Doping (cm
3
) Threshold Voltage (V )
2 1.5E16 -0.8212
3 1.5E16 -31.2335
4 1.5E16 -14.9976
6 3E16 -0.5342
7 6E16 31.2203
8 6E16 22.3424
As expected, the parasitic MOSFETs have much larger threshold voltages than the normal
devices.
Akinwande, Gibby, Jain, Oh, Sun, Wong 12
CIS/CMOS-II Modeling/Fabrication/Characterization 3 TSUPREM-IV SIMULATION RESULTS
3 TSUPREM-IV Simulation Results
3.1 Field and Gate Oxide Thicknesses
Oxidation cycles were simulated using the Dry O
2
, Steam, Dry O
2
procedure discussed earlier.
Table 18 presents the nal TSUPREM-simulated oxide thickness results.
Table 18: Oxide Thickness Simulation Results
Cross-Section 1 2 3 4 5 6 7 8
SiO
2
Thickness (m) N/A 0.0366 1.1971 0.5543 N/A 0.0366 1.1971 0.5543
3.2 Ion Implant Proles
TSUPREM-simulated dopant implants and anneals were obtained using the PD.FULL Method.
This Method includes TED (which was simulated by hand calculation), as well as OED and inter-
face segregation. The following pages illustrate the TSUPREM results.
3.3 Junction Depths
Table 19 presents the TSUPREM-simulated junction depths for the appropriate cross sections.
Aside from the PMOS Source/Drain , no other PMOS regions contain junctions. Additionally,
TSUPREM yielded ostensibly poor results for the NMOS Poly and NMOS Metal regions, indicating
that no P-Bulk existed. It was veried that this is a failing of TSUPREM and not of the process
itself.
Table 19: Junction Depth Simulation Results
Cross-Section 1 2 3 4 5 6 7 8
Junction Depth (m) 0.69 N/A N/A N/A 0.23 0.9148 N/A N/A
Akinwande, Gibby, Jain, Oh, Sun, Wong 13
CIS/CMOS-II Modeling/Fabrication/Characterization 3 TSUPREM-IV SIMULATION RESULTS
3.4 Sheet Resistivities of Junctions and Poly-Silicon Gates
TSUPREM-simulated results for sheet resistivities are provided in Table 20.
Table 20: Sheet Resistivity Simulation Results
Cross-Section NMOS Poly NMOS Source PMOS Poly PMOS Source
Sheet Resistivity (

sq.
) 28 60 249 52
3.5 Threshold Voltages
TSUPREM-simulated results for device threshold voltages are provided in Table 21. As mentioned
above, TSUPREM results indicated the lack of a P-Bulk region for the NMOS Poly and NMOS
Metal regions. Hence, no reasonable or meaningful threshold voltage value was obtained for these
regions.
Table 21: Threshold Voltage Simulation Results
Cross-Section 2 3 4 6 7 8
Threshold Voltage (V ) -1.032 -38.424 -17.135 0.172 N/A N/A
Akinwande, Gibby, Jain, Oh, Sun, Wong 14
CIS/CMOS-II Modeling/Fabrication/Characterization 3 TSUPREM-IV SIMULATION RESULTS
.
Akinwande, Gibby, Jain, Oh, Sun, Wong 15
CIS/CMOS-II Modeling/Fabrication/Characterization 3 TSUPREM-IV SIMULATION RESULTS
.
Akinwande, Gibby, Jain, Oh, Sun, Wong 16
CIS/CMOS-II Modeling/Fabrication/Characterization 3 TSUPREM-IV SIMULATION RESULTS
.
Akinwande, Gibby, Jain, Oh, Sun, Wong 17
CIS/CMOS-II Modeling/Fabrication/Characterization 3 TSUPREM-IV SIMULATION RESULTS
.
Akinwande, Gibby, Jain, Oh, Sun, Wong 18
CIS/CMOS-II Modeling/Fabrication/Characterization 3 TSUPREM-IV SIMULATION RESULTS
.
Akinwande, Gibby, Jain, Oh, Sun, Wong 19
CIS/CMOS-II Modeling/Fabrication/Characterization 3 TSUPREM-IV SIMULATION RESULTS
.
Akinwande, Gibby, Jain, Oh, Sun, Wong 20
CIS/CMOS-II Modeling/Fabrication/Characterization 3 TSUPREM-IV SIMULATION RESULTS
.
Akinwande, Gibby, Jain, Oh, Sun, Wong 21
CIS/CMOS-II Modeling/Fabrication/Characterization 3 TSUPREM-IV SIMULATION RESULTS
.
Akinwande, Gibby, Jain, Oh, Sun, Wong 22
CIS/CMOS-II Modeling/Fabrication/Characterization 4 ANALYSIS/SIMULATION RESULTS COMPARISON AND DISCUSSION
4 Analysis/Simulation Results Comparison and Discussion
4.1 Field and Gate Oxide Thicknesses
Table 22 presents the analytical and simulated oxide thickness results.
Table 22: Oxide Thickness Results
Cross-Section 1 2 3 4 5 6 7 8
SiO
2
Thickness (m) (calc.) N/A 0.0308 1.1588 0.5185 N/A 0.0308 1.1588 0.5185
SiO
2
Thickness (m) (sim.) N/A 0.0366 1.1971 0.5543 N/A 0.0366 1.1971 0.5543
The analytical and TSUPREM-simulated oxide thickness results agree well, save gate oxida-
tion. Generally, the hand analysis oxide results are thinner than the simulated values. This is also
expected, given the inuence of ramp oxidations, variable ow rates, etc. However, both models
made use of Deal-Grove and therefore signicantly underestimate the gate oxide thicknesses. This
is likely due to the fact that the model fails for thin oxides. Discrepancies between hand analysis
and simulation in this case could be due to modications to Deal-Grove (e.g. Massoud) employed
in TSUPREM to account for more rapid oxidation for thin layers.
4.2 Ion Implant Proles
As expected, the dopant concentration proles vary widely between hand analysis results and
TSUPREM-obtained curves. The discrepancies are an obvious consequence of neglecting concentration-
dependent diusivities, dopant segregation at interfaces (esp. SiO
2
and Si), surface reection, OED,
variable dopant stopping mechanisms and powers among dierent materials, implant angles, and
others. The consideration of TED, however, likely reduced the error present in the hand analysis.
4.3 Junction Depths
Table 23 presents the analytical and simulated junction depth results.
Cross-Sections 1 and 5 yield relatively reasonable agreement between the hand analysis and sim-
ulation results. Discrepancies in these and other junction depths depend largely on segregation
eects at the SiO
2
-Si interface. This is especially true for Boron, which has a strong tendency to
segregate into the oxide. The omission of B segregation is evident the MATLAB PMOS doping
plots, in which a large P-Type doping prole extends into the Si substrate.
Akinwande, Gibby, Jain, Oh, Sun, Wong 23
CIS/CMOS-II Modeling/Fabrication/Characterization 4 ANALYSIS/SIMULATION RESULTS COMPARISON AND DISCUSSION
Table 23: Junction Depth Results
Cross-Section 1 2 3 4 5 6 7 8
Junction Depth (m) (calc.) 1.2634 N/A N/A N/A 0.5934 1.7420 1.1725 1.1811
Junction Depth (m) (sim.) 0.69 N/A N/A N/A 0.23 0.9148 N/A N/A
4.4 Sheet Resistances of Junctions and Poly-Silicon Gate
Table 24 presents the analytical and simulated sheet resistance results.
Table 24: Sheet Resistance Results
Cross-Section NMOS Poly NMOS Source PMOS Poly PMOS Source
Sheet Resistance (

sq.
) (calc.) 100.6747 60.1859 367.7422 39.5758
Sheet Resistance (

sq.
) (sim.) 28 60 249 52
The Source/Drain results for hand analysis and TSUPREM simulations agree well. Thus, the
methodology of using Irvins Curves ostensibly worked well. However, notable discrepancies exist
for the Poly regions. This is likely due to the method of averaging used to approximate a uniform
distribution. Numerical integration would yield the most accurate results in this case.
4.5 Threshold Voltages
Table 25 presents the analytical and simulated threshold voltage results.
Table 25: Threshold Voltage Results
Cross-Section 2 3 4 6 7 bf 8
Threshold Voltage (V ) (calc.) -0.8212 -31.2335 -14.9976 -0.5342 31.2203 22.3424
Threshold Voltage (V ) (sim.) -1.032 -19.010 -17.117 0.172 N/A N/A
Akinwande, Gibby, Jain, Oh, Sun, Wong 24
CIS/CMOS-II Modeling/Fabrication/Characterization 4 ANALYSIS/SIMULATION RESULTS COMPARISON AND DISCUSSION
PMOS threshold voltage results are in reasonable agreement for hand analysis and TSUPREM
simulations. Values for the parasitic devices are large in both models, while the PMOS Channel
threshold voltage values are acceptably-close. Due to the mentioned issue with TSUPREMs treat-
ment of the P-Bulk, a meaningful comparison cannot be carried out for the NMOS Poly and Metal
regions. However, one notable dierence regarding the NMOS Channel involves the simulation-
obtained result of a depletion-mode device. The discrepancy between the weak enhancement-result
of hand analysis may be an artifact of second-order eects (e.g. segregation).
Generally, dierences in threshold voltage values are inevitable given the treatment of surface
concentration. Dopant proles are non-uniform and signicant approximations were made in order
to arrive at meaningful values for the hand analysis. Dierences in material thicknesses, band
calculation variances, and the like would also contribute to disagreement between the hand results
and simulation output.
Akinwande, Gibby, Jain, Oh, Sun, Wong 25
CIS/CMOS-II Modeling/Fabrication/Characterization 5 MEDICI SIMULATION RESULTS
5 MEDICI Simulation Results
5.1 pMOS Simulation Results
As shown later in Section 6.1.2, fabricated pMOS devices displayed a wide range of characteristic
parameters, varying with wafer, die, and transistor size. In order to dene a realistic expecta-
tion for device performance, pMOS transistors were simulated using Avant!s 2-D device simulator,
MEDICI. In particular, the longest and most common fabricated gate lengths100 m, and 20
m, respectivelywere chosen as the simulated structures.
The complete script used in simulations can be seen in Section 9.5. Doping proles were not
simulated using analytic proles, rather the 1-D outputs from the TSUPREM simulations (see Sec-
tion 3.2), were imported, with an approximate XY.RATIO set to .75 to account for lateral spreading
of implanted dopants.
Results of the pMOS simulations are seen in gures 4, 5, 6, and 7. Transistor parameters can
be seen in Table 26. As can be seen in the gures and in Table 26, Short Channel eects, including
Drain Induced Barrier Lowering (DIBL), are absent from the simulations.
Figure 4: I
d
vs. V
d
, 100m, pMOS Device Simulation
Akinwande, Gibby, Jain, Oh, Sun, Wong 26
CIS/CMOS-II Modeling/Fabrication/Characterization 5 MEDICI SIMULATION RESULTS
Figure 5: I
d
vs. V
d
, 20m, pMOS Device Simulation
Figure 6: log(I
d
) vs. V
g
, 100m, pMOS Device Simulation
Akinwande, Gibby, Jain, Oh, Sun, Wong 27
CIS/CMOS-II Modeling/Fabrication/Characterization 5 MEDICI SIMULATION RESULTS
Figure 7: log(I
d
) vs. V
g
, 20m, pMOS Device Simulation
Table 26: Simulated pMOS Parameters
Parameter 100 m 20 m
V
t
, low V
d
, (V) 1.049 0.8864
V
t
, high V
d
, (V) 1.059 0.8757
Subthreshold Slope, (mv/dec) 87.18 88.69
Akinwande, Gibby, Jain, Oh, Sun, Wong 28
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
6 Characterization
6.1 Device Test Structures
6.1.1 nMOSFETs
Introduction
Several nMOS devices were built on ve separate wafers using the EE410 CMOS II process.
Devices ranging from 100m x 100m to 1.5m x 1m were evaluated. Only wafer 5 had some
working nMOS devices. The other wafers showed no transistor behavior at all. The current hypoth-
esis why the other wafers failed to show a working nMOS is due to over-etching of the source/drain
regions using the Drytek plasma etch. Wafer 5 was etched using the P5000 machine with endpoint
detection algorithm. A full explanation of this hypothesis is presented later in this section.
The nMOS devices were built in isolated p-wells and are meant to operate as enhancement
mode devices. The following parameters were measured (or extracted from measurement):
Threshold voltages (V
t
)
Transconductance (g
m
)
Channel length modulation ()
Small signal output resistance (r
0
)
Channel doping (N
A
)
Body eect ()
Subthreshold slope ()
Size of smallest functioning device
Small dimension eects - V
t
as a function of L and W
Due to a sudden catastrophic failure of all nMOS devices on wafer 5 (after initial testing),
additional testing could not be performed to obtain data for extraction of breakdown voltage.
After much troubleshooting including wafer probe adjustment and re-calibration and prior years
nMOS device verication, a satisfactory reason for the sudden blowout of nMOS devices on wafer
5 is yet to be determined. Furthermore, limited statistical analysis was performed as there were
only a few working nMOS samples. All measurements are with the source and bulk grounded. A
summary of extracted parameters for several devices is presented at the end of this section. A
picture of the pad arrangement for contacting the transistors is shown in Figure 8.
Threshold Voltage (V
t
) and Small Dimension Eects
The threshold voltages were obtained from graphs of I
D
V
G
curves. Specically,
t
is the x-axis
intercept of the plot of Equation 16.
Akinwande, Gibby, Jain, Oh, Sun, Wong 29
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 8: Test Pad Conguration for nMOSFET Contacts
_
I
D
=
_
(V
GS
V
t
) (16)
where =
1
2
C
ox
W
L
for a transistor biased in the saturation region. The threshold voltage
ranged from 0.67V for a 100m x 100m device to a minimum of 0.3V for a 100m x 1.5m
device. Figures 9 and 10 present the short-channel and narrow-width eects, respectively. Note:
Only two data points (W = 1.5m and W = 100m) are available for narrow width eect.
Figure 9: nMOS Short Channel Eect
In addition, the subthreshold region was investigated, and the slope was extracted to be about
44mv/dec for a 100m x 100m device.
Akinwande, Gibby, Jain, Oh, Sun, Wong 30
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 10: nMOS Narrow Width Eect
Transconductance (g
m
)
The transconductance is a very important parameter for analog applications. It represents the
intrinsic small signal gain of the transistor. It is measured as the slope of the I
D
V
G
curve for
a transistor biased in the saturation region. Formally g
m
for a long channel device is given by
Equation 17
g
m
= C
ox
W
L
(V
G
V
t
) = 2 (V
G
V
t
) (17)
The transconductance is plotted in Figure 11 for dierent lengths with constant width W = 100m.
The dramatic increase at very short lengths is due to short channel eects (reduction) on V
t
and additional multiplier in Equation 17 resulting from channel length modulation (nite ).
Channel Length Modulation () and Output Resistance (r
0
)
Channel length modulation is similarly of interest in analog applications. It models the de-
pendence of the drain current on drain voltage. This dependence arises from an increase in the
depletion width around the drain region (as drain voltage increases) consequentially resulting in a
reduction of the channel length and an increase in drift current. For the popular common-source
amplier, r
0
represents the intrinsic output resistance and together with g
m
denes the maximum
small signal voltage gain. is measured by extrapolating V
D
to obtain the intercept from the
I
D
V
D
curves, and is simply the inverse of the V
D
intercept. was measured to be 0.095V
1
and
0.2V
1
for 100m x 100m and 100m x 1.5m devices, respectively. The output resistance was
obtained from the slope of the I
D
V
D
curve for saturation biases. Figure 12 shows r
0
for dierent
Akinwande, Gibby, Jain, Oh, Sun, Wong 31
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 11: nMOS Transconductance
lengths (W = 100m).
Figure 12: nMOS Output Resistance
Channel Doping (N
A
) and Body Eect ()
For a given threshold voltage, the surface channel doping (N
A
for nMOS devices) can be ex-
tracted from Equation 18.
Akinwande, Gibby, Jain, Oh, Sun, Wong 32
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
V
t
=
ms
+ 2
f

Q
f
C
ox

Si
x
0

ox

4qN
A
(
f
)

Si

0
(18)
where
f
=
kT
q
ln
_
N
A
n
i
_
.
The workfunction is taken to be -1V [5], xed oxide charge Q
f
= 5E11cm
2
, and gate oxide
thickness of 40nm is used. Equation 18 is a transcendental equation (since
f
depends on N
A
) and
must be solved numerically or graphically. Using a graphical technique, N
A
was determined to be
about 1E17cm
3
. The threshold voltage of the longest device (100m x 100m) was used in order
to minimize small-dimension eects.
Due to the sudden failure of nMOS devices on wafer 5, and the resulting inability to obtain
back-gate bias data, was determined to be 2.1 from Equation 19 using the channel doping estimate
and taking oxide thickness to be 40nm.
=
1
C
ox
_
2q
Si

0
N
A
(19)
Smallest Working nMOSFET
All the four minimum-sized transistors were found to be working on wafer 5. The ability to ob-
tain channel lengths as small as 1m is mostly due to the accurate anisotropic etching and end-point
detection precision of the P5000 plasma etcher. The I
D
V
D
curves for the four minimum-sized
devices are shown in Figures 13-16.
Data for a 100m x 100m is shown in Figure 17.
Device Parameter Summary
A summary of some of the key electrical data for nMOS transistors are presented in Table 27
for several devices ranging from the biggest to the smallest, with N
A
= 1E17cm
3
, = 2.1, and
= 44mV/dec. A discussion of bad nMOS devices now follows.
nMOS Device Failures
Many nMOS transistors were observed to function improperly, were shorted, or had no drain
Akinwande, Gibby, Jain, Oh, Sun, Wong 33
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 13: 2m x 2m nMOS I
D
V
D
Characteristics
Figure 14: 2m x 1.5m nMOS I
D
V
D
Characteristics
Akinwande, Gibby, Jain, Oh, Sun, Wong 34
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 15: 1.5m x 1.5m nMOS I
D
V
D
Characteristics
Figure 16: 1.5m x 1m nMOS I
D
V
D
Characteristics
Akinwande, Gibby, Jain, Oh, Sun, Wong 35
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 17: 100m x 100m nMOS I
D
V
D
Characteristics
Table 27: Sample nMOS Electrical Data
W/L V
t
(V) g
m
(mS) (V
1
)
1.5/1 0.61 0.215 0.136
2/1.25 0.61 0.296 0.116
1.5/1.5 0.38 1.19 0.153
100/1.5 0.3 23.8 0.2
2/2 0.42 1.16 0.147
100/10 0.64 3.82 0.2
6/20 0.54 0.17 0.128
100/100 0.67 0.11 0.095
Akinwande, Gibby, Jain, Oh, Sun, Wong 36
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
current. These failures are presented and explained below.
Gate-Drain Short. Figure 18 shows the I
D
V
D
curves for a 100m x 100m transistor.
Figure 18: 100m x 100m nMOS Gate-Drain Short I
D
V
D
Characteristic
As can be seen the data suggests that the gate and drain have been shorted leading to an
I
D
V
G
curve instead. There are many reasons why this can happen. Two possible reasons are 1)
possible aluminum shorting of the gate and drain region or 2) polysilicon shorting of the gate to the
drain. The latter can happen if there is insucient etching of the gate polysilicon after deposition
or an alignment error during gate denition lithography, such that the mask is shifted towards the
drain. As a result, part of the mask is blocking some of the drain region from been etched. If
this shift occurs, there may be a depletion region between the source and channel because there is
no gate at that edge to control the surface charges. However, for very short depletion region (or
barrier), tunneling current can exist and therefore the behavior in Figure 18 can occur.
Gate-Source Short. If indeed there exists a reasonable probability of shorting of gate and
drain regions, one would likewise expect a reasonable probability of shorting between gate and
source regions. This shorting has been observed and is shown in Figure 19.
Such a shorted structure is essentially a pn diode with the bulk representing the p region and
the drain representing the n region. Current will then ow for negative drain biases resulting in
negative current. The magnitude of the threshold voltage is estimated to be 0.8V. The 100mA
Akinwande, Gibby, Jain, Oh, Sun, Wong 37
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 19: 100m x 20m nMOS Gate-Source Short I
D
V
D
Characteristic
current limit is due to tester compliance.
Shorted nMOS. To complete the shorting trilogy, we have also observed shorting of the
entire nMOS, i.e., the source and drain are shorted to the gate. This can happen as a result of
insucient etching (under-etch) of the gate polysilicon in the source/drain regions. The resulting
behavior of the device would then be similar to a resistor. A graph of a 100m x 20m device
showing this failure is shown in Figure 20.
The current limit of 100mA is the current compliance of the tester. The eective resistance is
about 8.
Faulty nMOS. The majority of the failures observed were devices that simply did not draw
any current, as if the source and drain were not connected to the channel, thus resulting in an
open-circuit. As mentioned earlier, one explanation is over-etch of the source and drain regions.
nMOS Characterization and TSUPREM-IV Simulation Comparison
The values calculated, simulated and measured for the nMOS transistor are compared in Table
28. The measured values are taken from the longest channel device.
Akinwande, Gibby, Jain, Oh, Sun, Wong 38
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 20: 100m x 20m Four-Node nMOS Short I
D
V
D
Characteristic
Table 28: nMOS Analysis, Simulation, and Electrical Characterization Results
Parameter Analytical TSUPREM-IV Measured
V
t
(V) 0.75 0.69 0.67
N
A
(cm
3
) 1.2E17 1.1E17 1E17
Akinwande, Gibby, Jain, Oh, Sun, Wong 39
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
The common parameters are threshold voltage and channel doping. The surface depletion at
the channel surface predicted by TSUPREM-IV has been understood to be an artifact of a 1-D
simulation. Taking the peak boron concentration to occur at the surface, the TSUPREM-IV sim-
ulation values have thus been recalculated.
6.1.2 pMOSFETs
Like the nMOS Devices, pMOSFET transistors were characterized on a Hewlett-Packard HP4145B
Semiconductor Parameter analyzer. Probes were used to contact individual pads for each device
corresponding to Source, Drain, Gate and Substrate contacts. With the exception of tests run to
determine the body eect, the Substrate and Source contacts were held at ground. Drain and Gate
voltages were then varied while Drain current was measured. Specic values used on Wafers 1, and
35 are shown in Table 29. Wafer 2 was shown to have a much wider distribution in threshold
voltages, so V
g
was swept through a greater range of values. The parameters for this setup are
shown in Table 30.
Table 29: HP4145 Setup, Low V
t
Transistors
Contact Begin V Step End V
Source 0 const
Drain 0 0.2 5.0
Gate 0 0.5 5.0
Substrate 0 const
Table 30: HP4145 Setup, High V
t
Transistors
Contact Begin V Step End V
Source 0 const
Drain 0 0.2 5.0
Gate 0 3.0 27.0
Substrate 0 const
pMOS devices were tested on all ve manufactured wafers on at least three dice in the center
of the wafer and two dice near the edge. In the event that no working devices were found on the
initial ve dice, more dice were tested to nd functioning devices. Despite exhaustive probing of
wafers B4 and B5, no working pMOS devices were found on those wafers. Wafers B1B3, however,
Akinwande, Gibby, Jain, Oh, Sun, Wong 40
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
had working devices, and data was generated for a total of 180 devices, 64 from wafer B1, and 95
from B2. Only 21 working devices were found on wafer B3. This was probably due to a bad metal
deposition that plagued the whole process (See Section 7).
After measurement, data was converted to a PC-readable format and drain current was plotted
as I
d
vs. V
d
, I
d
vs. V
g
, and log(I
d
) vs. V
g
. Threshold voltages were then extracted from the linear
I
d
V
g
curves and subthreshold slopes were pulled from the logarithmic curves. In particular, one
device of 100 m channel length and another with a channel length of 20 m were chosen for anal-
ysis and comparison. These transistors were chosen because their threshold voltages and lengths
were similar to those simulated in MEDICI (See Section 5.1). Both devices were on wafer B1 and
will be referred to as PMOS1 for the 100 m device and PMOS2 for the 20 m device. PMOS1
was in series D-5, on the die one column to the right of the center die, where the wafer at is at
the bottom of the wafer. PMOS2 was from series D-5 one die to the left of center. Characteristic
plots for PMOS1 are shown in Figures 21, 22, and 23, while plots for PMOS2 are shown in 24, 25,
and 26. In the following sections, plots of characteristics from a single transistor are taken from
PMOS1, unless otherwise specied.
Figure 21: PMOS1 I
d
vs. V
d
plot used in pMOS analysis
Though many devices were far from idealmany displayed severe DIBL eects, as will be dis-
cussed in Section 7working devices were found at even the smallest dimensions on wafers B1B3.
As proof, an IV diagram of a 1.5 m/1 m W/L device is shown in Figure 27. This device was the
Akinwande, Gibby, Jain, Oh, Sun, Wong 41
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 22: PMOS1 I
d
vs. V
g
Plot
Figure 23: PMOS1 log(I
d
) vs. V
g
Plot
Akinwande, Gibby, Jain, Oh, Sun, Wong 42
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 24: PMOS2 I
d
vs. V
d
plot used in pMOS analysis
Figure 25: PMOS2 I
d
vs. V
g
Plot
Akinwande, Gibby, Jain, Oh, Sun, Wong 43
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 26: PMOS2 log(I
d
) vs. V
g
Plot
last of the D-8 series on the die just left of center on wafer B1. Transistor characteristics are obvi-
ous from the gure, though DIBL causes an increase in Drain current with increasing drain voltage.
pMOSFET Threshold Voltages
A histogram of measured threshold voltages is displayed in Figure 28. From the gure, it is
readily apparent that a wide range of threshold voltages were measured. However, when comparing
Figure 28 with Figures 29, 30, and 31, one sees that much of the threshold voltage variation exists
solely on wafer B2. Also, wafer B2 shows a shifted mean threshold voltage that is not predicted
by simulations. Wafers B1 and B3, on the other hand, have average threshold voltages that are
within one standard deviation of the predicted value.
pMOSFET Transconductance
As shown in Figure 32 pMOS Transconductance was found to be a function of both V
g
and V
d
.
In order to have a parameter to compare from one transistor to the next, g
m
was measured as the
slope of the near-linear low V
d
curve on the linear I
d
vs. V
g
plots. The histogram of measured g
m
values is shown in Figure 33.
Akinwande, Gibby, Jain, Oh, Sun, Wong 44
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 27: IV Characteristics of the smallest functioning devicea 1.5 x 1 m device
Figure 28: A plot of all measured V
t
. Mean value = 3.03V . Standard Deviation = 2.92V
Akinwande, Gibby, Jain, Oh, Sun, Wong 45
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 29: A plot of V
t
measured on wafer B1. Mean value = 1.31V . Standard Deviation =
0.94V
Figure 30: A plot of V
t
measured on wafer B2. Mean value = 4.33V . Standard Deviation = 3.4V
Akinwande, Gibby, Jain, Oh, Sun, Wong 46
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 31: A plot of V
t
measured on wafer B3. Mean value = 2.42V . Standard Deviation =
1.05V
Figure 32: A plot of g
m
for a transistor taken from a center die on wafer B1
Akinwande, Gibby, Jain, Oh, Sun, Wong 47
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 33: A plot of g
m
measured on wafer B1. Mean value = 1.04 10
5
A/v. Standard Deviation
= 2.00 10
5
A/V
pMOSFET Body Eect
An adjustment of the threshold voltage can also be accomplished by reverse biasing the back
contact of an MOS transistor. This causes inversion layer carriers to migrate into the source and
drain regions since these regions are now at a lower potential. Thus, the point at which inversion
occurs, and hence the threshold voltage, shifts according to the amount of back bias applied. For
a PMOS device, the eect of a positive back bias would be to increase the magnitude of the ideal
threshold voltage. That is, with increasing positive back bias, the threshold voltage should become
more negative. For pMOS devices, this can be described by the relation,
V
t
= V
to
+[
_
V
SB
2
f

_
2
f
] (20)
where V
to
is the threshold voltage under no gate bias, is the body eect coecient and V
SB
is the substrate bias. The results from the testing of a 100 m by 100 m PMOS device from the
center die of wafer B1 are found in Figure 34 and the table of extracted threshold voltages is found
in Table 31. Solving for using the above expression gives an average value of -2.6. We would
expect to have a positive value, thus indicating an increase in the magnitude of threshold voltage
as a function of substrate bias. Our results are contrary to predictions, as increasing the substrate
bias was seen to shift the threshold voltage values towards positive values. This may indicate that
the inversion layer carriers are not being swept into the source and drain regions but instead remain
in the channel region. This would cause the threshold voltage to decrease in magnitude.
Akinwande, Gibby, Jain, Oh, Sun, Wong 48
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
-300x10
-6
-200
-100
0
I
d

(
A
)
-10 -5 0 5 10
Vg (V)
Vsb = 0V
Vsb = 1V
Vsb = 2V
Vsb = 3V
Vsb = 4V
Figure 34: Eect of Back Bias
Table 31: Body Eect Summary
V
SB
(V) V
t
(V) V
t
-V
to
(V)
0 -1.27 -
1 -0.32 -0.95
2 0.84 -2.11
3 1.86 -3.12
4 2.63 -3.90
Akinwande, Gibby, Jain, Oh, Sun, Wong 49
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
pMOSFET Channel Doping
Channel doping was determined from the measured threshold voltage on PMOS1 and PMOS2.
In order to calculate the surface doping concentration, the formula,
V
t
=
MS

Q
f
C
ox

_
2
s
qN
d
(2
p
)
C
ox
2
p
(21)
was used, where Q
f
= 5e10cm
2
. Also,

MS
= 0.56 +
p
(22)

p
=
kT
q
ln
N
d
n
i
(23)
which assumes that the gate is degenerately doped, pinning the gate fermi level at the valence band
edge. From SEM images of our devices, the measured gate oxide thickness is close to the target
thickness of 400

A. Thus,
C
ox
=

ox
x
ox
=
8.85 10
14
3.9
400 10
8
= 8.63 10
8
F/cm (24)
Solving this system of equations numerically for N
d
, using the measured values for V
t
we get the
values shown in Table 32.
Table 32: Extracted N
d
values, pMOSFETs
Parameter PMOS1 PMOS2
Channel Length 100 m 20 m
V
t
1.0V 0.9V
N
d
3.46E16 cm
3
2.93E16 cm
3
pMOSFET Subthreshold Behavior
Subthreshold slopes were taken as the inverse of the largest slope on the log I
d
vs. V
g
curves.
Data was obtained from wafers B1B3, though the large V
g
used in measuring wafer B2 resulted
in articially large subthreshold slopes. Because of this, only the data from wafers B1 and B3 is
presented in Figure 35. A few devices can be seen to approach the ideal value from simulations of
88 mV/dec, though these values could be artifacts of the experimental setup due to discontinuities
in the log I
d
vs. V
g
curves. In fact, the pA current resolution of the HP4145 prevented very accurate
measurement of the subthreshold slope. The measured values for PMOS1 and PMOS2 were 162
Akinwande, Gibby, Jain, Oh, Sun, Wong 50
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
and 127 mV/dec, respectively.
Figure 35: Subthreshold Slope Distribution for wafers B1 and B3. Mean = 214 mV/dec. Standard
Deviation = 123 mV/dec.
pMOSFET Channel Mobility
Like channel doping, channel mobility was not directly measured; rather, it was derived from
measured data. By taking the triode region current to be,
I
d
=

P
C
ox
2
W
eff
L
eff
[2(V
gs
V
t
) V
ds
] V
ds
(25)
this equation can be solved for
P
:

P
=
2I
d
C
ox
L
eff
W
eff
1
[2(V
g
V
t
) V
d
] V
d
(26)
For simplicity and given the relatively large size of the devices involved, W
eff
and L
eff
were
both chosen to be identical to lithographic gate width, though the accuracy of this assumption will
be discussed later in this section. The values used in determining
P
are shown in Table 33, as well
as the calculated mobilities.
Also shown in Table 33 are the surface mobilities calculated using the Sun & Plummer Model
[6]. In this model, an eective electric eld, E
eff
between the semiconductor bulk and the gate is
Akinwande, Gibby, Jain, Oh, Sun, Wong 51
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Table 33: Values used in determining channel mobility and Values calculated from experimental
data
Parameter [unit] PMOS1 PMOS2
V
g
[V] -2 -2
V
d
[V] -0.6 -0.6
V
t
[V] -1 -0.9
L
eff
[m] 100 20
W
eff
[m] 100 100
I
d
[A] -9.05E-6 -2.39E-5
Experimental
P
[cm
2
/V*s] 216 105
Sun-Plummer Value [cm
2
/V*s] 135 134
Burried Channel [cm
2
/V*s] 209 211
partially screened by the inversion layer such that,
E
eff
=
1

s
_
1
2
C
ox
[V
g
V
t
] +Q
bulk
_
(27)
where
Q
bulk
=
_
2
s
qN
d
(2
p
). (28)
and N
d
values were determined above. The eective mobility is then calculated as a fraction of the
low eld surface mobility,
P0
:

eff
=

P0
1 +
_
E
eff
E
0
_

. (29)
where the empirically tted parameters, and E
0
as well as
P0
are shown in Table 34. Note
that with this model, the surface mobility is never higher than the low eld value, 160 cm
2
/Vs.
However, our calculated value for PMOS1 was signicantly higher than the surface low eld hole
mobility. A possible explanation is that the carriers are traveling in a buried channel. This possibil-
ity will be discussed further in Section 7. Applying the tting parameters for a burred channel (see
Table 34), we arrive at the nal row of Table 33, where values are very similar to those calculated
from experimental data for PMOS1.
pMOSFET Channel Length Modulation. The parameter that describes channel length mod-
ulation, , can be dened such that,
I
DSAT
=

P
C
ox
2
W
L
(V
g
V
t
)
2
(1 +V
d
) (30)
Akinwande, Gibby, Jain, Oh, Sun, Wong 52
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Table 34: Sun and Plummer Model Parameters. [7]
Parameter [unit] Surface Channel Burried Channel

P0
[cm
2
/Vs] 160 290
E
0
[MV/cm] 0.7 0.35
1 1
where I
DSAT
is the saturation drain current. Taking the derivative with respect to V
d
and
solving for , we get,
=
2

p
C
ox
L
W
1
(V
g
V
t
)
2
dI
DSAT
dV
d
(31)
can therefore be determined from the measured data by taking a nite dierence, I
d
/V
d
, at
each point on the I
d
vs. V
d
curve. The resulting values for were then averaged to determine a
nal value. Table 35 shows the parameters used and the average for PMOS1 and PMOS2. As can
be seen numerically in the table and graphically in Figures 21 and 24, channel length modulation
is much more severe for the shorter channel device, as we would expect.
Table 35: Values used in determining
Parameter [unit] PMOS1 PMOS2
V
g
[V] -2 -2
V
t
[V] -1 -0.9
L [m] 100 20
W [m] 100 100
[V
1
] 0.027 0.263
pMOSFET Breakdown Voltage
There are two principal reasons for breakdown in MOSFETs. The rst reason is punch-through,
which is when the depletion region at the drain extends across the entire channel region and reaches
the source. Punch-through is very sensitive to channel length, but not largely aected by decreas-
ing channel widths. As a result, it is expected that shorter channel lengths would have a lower
breakdown voltage. The second mechanism for breakdown is the due to a parasitic BJT eect.
Again, shorter channel lengths would cause breakdown to occur earlier. For the pMOS devices,
breakdown characteristics were tested on a 100 by 100 m device on wafer B1 and are shown in
Akinwande, Gibby, Jain, Oh, Sun, Wong 53
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 36. In this case, the breakdown occurred when the drain voltage exceeded -10V. At lower
voltages, normal I
d
V
d
characteristics were obtained (but cannot be observed on due to the scale
of the gure). When the drain voltage went beyond -10V, the current dramatically increased.
-250x10
-6
-200
-150
-100
-50
0
50
I
d

(
A
)
-14 -12 -10 -8 -6 -4 -2 0
Vd (V)
Figure 36: Breakdown Characteristics for 100x100 m PMOS Device
pMOSFET Short Channel Eect
The Short Channel Eect (SCE) was observed statistically by taking all devices with a gate
width of 100 m (the most frequently occurring gate width) and plotting their threshold voltages
as a function of gate length. (See Figure 37) To show the decreasing trend, a logarithmic t was
performed and the curve is also plotted in Figure 37. The trend is obvious; however, due to statis-
tical scatter in the measured points, the reverse short channel eect was not observed.
pMOSFET Narrow Channel Eect
When plotting V
t
as a function of gate width for all 20 m channel length devices, the plot
unfortunately shows a similar trend to the SCE discussed above. Instead of the expected rise in
|V
t
| with decreasing width, |V
t
| is found to decrease. This is shown in Figure 38.
pMOSFET Eective Channel Length, L
eff
As we saw in the section dealing with channel length modulation, has a non-zero value and
therefore our assumption that L
eff
is equal to the lithographically dened gate length might be
inaccurate. We now explore that possibility further.
If we assume that is entirely a result of a change in channel length, we can replace L in
equation 30 with an eective channel length such that,
Akinwande, Gibby, Jain, Oh, Sun, Wong 54
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 37: Plot of |V
t
| as a function of gate length. Solid line is a simple logarithmic t to the data
points, indicating the downward trend with decreasing gate length.
Figure 38: Plot of |V
t
| as a function of gate width.
Akinwande, Gibby, Jain, Oh, Sun, Wong 55
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
(V
d
V
DSAT
)
W
L
=
W
L
eff
(32)
L
eff
= L + L (33)
combining equations and solving for L, we get,
L =
L
(V
d
V
DSAT
)
L (34)
Now we revisit the assumptions that we made when discussing channel mobility in Section 6.1.2.
By choosing V
DSAT
as the point where the rst derivative of I
d
with respect to V
d
approaches its
minimum, we nd that V
DSAT
is -1V for both PMOS1 and PMOS2. Since V
d
for both devices was
chosen to be -0.6 V, the channel length modulation as we have discussed here does not come in to
eect.
One could also argue that L is eectively shortened by the source/drain depletion regions.
Thus, L
eff
would be less than L because of encroachment of the drain depletion region into the
channel under increasing drain bias. Taking the worst-case simplication that the source depletion
region does not shrink as it is forward biased, and assuming a depletion region thickness, W, for a
step-function doping prole, we nd,
W =
_
2
s
qN
d
(V
bi
V
d
) (35)
V
bi
= 0.56 +
kT
q
ln
N
d
n
i
(36)
which assumes N
a
N
d
, and that the drain is degenerately doped. Solving this system of
equations for the N
d
values determined above, we nd that under an applied bias of -0.6 V, W
is 0.241 m for PMOS1 and 0.262 m for PMOS2. Since these values are much less that the
lithographic gate lengths, it is reasonable to make the simplifying assumption that L
eff
L when
calculating channel mobility.
6.1.3 MOSCAPs
Methodology
Eight (8) dierent MOS capacitors were tested as part of CIS/CMOS-II characterization. Table
36 describes the general composition and geometry of each type of MOSCAP in brief.
Akinwande, Gibby, Jain, Oh, Sun, Wong 56
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Table 36: MOS Capacitors
Composition Area (m
2
)
n
+
Poly/Gate SiO
2
/p-Well 300,000
p
+
Poly/Gate SiO
2
/n-Substrate 300,000
n
+
Poly/Field SiO
2
/p-Well 300,000
p
+
Poly/Field SiO
2
/n-Substrate 300,000
Metal/Field SiO
2
+ LTO/p-Well 600,000
Metal/Field SiO
2
+ LTO/n-Substrate 600,000
Metal/LTO/n
+
Poly 300,000
Metal/LTO/p
+
Poly 300,000
CV curves were extracted using the HP4275A multi-frequency LCR meter. AC signal ampli-
tude was set at 10mV with a high-frequency oscillation at 100kHz. Bidirectional voltage sweeps
were executed with a step time of 0.1sec.
MOSCAP characterization started with inversion biasing in order to extract meaningful ap-
proximations for C
min
and display deep depletion eects on return sweeps.
Theoretical Calculations
Capacitance. Equations 37-39 present the expressions describing MOSCAP capacitance un-
der accumulation, depletion, and inversion (HF) conditions [5].
C(acc) = C
ox
=

ox
A
t
ox
(37)
C(depl) =
C
ox
1 +
KoxW
K
S
tox
(38)
C(inv)|
HF
=
C
ox
1 +
KoxW
T
K
S
tox
(39)
With estimates for gate oxide, FOX, and LTO thickness as in Table 1, Table 37 presents the
expected ideal capacitance values for MOSCAPs with the dierent dielectric compositions of the
CIS/CMOS-II chip.
SiO
2
Dielectric Thickness. From Equation 37, assuming an SiO
2
dielectric and given value
for C
ox
, an estimate for dielectric thickness can be calculated as in Equation 40.
Akinwande, Gibby, Jain, Oh, Sun, Wong 57
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Table 37: MOSCAPs - Theoretical Values for C
ox
Dielectric Dielectric Thickness (nm) Area (m
2
) C
ox
(pF)
Gate SiO
2
40 300,000 258.8625
Field SiO
2
500 300,000 20.709
Field SiO
2
+ LTO 1100 600,000 18.8264
LTO 600 300,000 17.2575
t
ox
=

ox
A
C
ox
(40)
Threshold Voltage. Table 21 presented TSUPREM-IV-based estimates of threshold voltage
values. V
t
expectations are reproduced according to MOSCAP type in Table 38. Note: Metal gate
MOSCAPs were not simulated as part of the TSUPREM-IV exercise.
Table 38: MOSCAP TSUPREM-IV-Extracted V
t
Composition Area (m
2
) TSUPREM-IV V
t
n
+
Poly/Gate SiO
2
/p-Well 300,000 0.172
p
+
Poly/Gate SiO
2
/n-Substrate 300,000 -1.032
n
+
Poly/Field SiO
2
/p-Well 300,000 N/A
p
+
Poly/Field SiO
2
/n-Substrate 300,000 -17.135
Metal/Field SiO
2
+ LTO/p-Well 600,000 N/A
Metal/Field SiO
2
+ LTO/n-Substrate 600,000 -38.424
Metal/LTO/n
+
Poly 300,000 N/A
Metal/LTO/p
+
Poly 300,000 N/A
Characterization Results
Gate MOSCAPs. 240 gate MOSCAPs (two per die, 24 o-edge dice per wafer, ve wafers)
were tested. Unfortunately, but not surprisingly, none of these capacitors yielded acceptable CV
curves. Figures 39 and 40 are representative curves for the n
+
Poly/p-Well and p
+
Poly/n-Substrate
gate capacitors, respectively.
The poor gate MOSCAP results are not entirely surprising in the light of poor Al/Si alloy
deposition and relatively large step heights for contact to polysilicon gates from above the LTO
layer. Specically, the step height involved for gate MOSCAPs is approximately 600nm, i.e. the
LTO thickness. While this height does not seem so dicult to surmount by itself, the already-poor
quality of metal coverage even on planar surfaces indicates potential diculty for metal continuity
Akinwande, Gibby, Jain, Oh, Sun, Wong 58
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
5 4 3 2 1 0 1 2 3 4 5
8.55
8.6
8.65
8.7
x 10
13
Applied Voltage, V
A
(V)
C
a
p
a
c
ita
n
c
e
, C
(
F
)
Wafer B1, Center Die, Gate SiO
2
, n
+
Poly/ pWell nMOSCAP
dV/dt > 0
dV/dt < 0
Figure 39: Representative n
+
Poly/p-Well Gate MOSCAP
5 4 3 2 1 0 1 2 3 4 5
3.44
3.46
3.48
3.5
3.52
3.54
3.56
3.58
3.6
3.62
3.64
x 10
13
Applied Voltage, V
A
(V)
C
a
p
a
c
ita
n
c
e
, C
(
F
)
Wafer B1, Center Die, Gate SiO
2
, p
+
Poly/ nSub pMOSCAP
dV/dt > 0
dV/dt < 0
Figure 40: Representative p
+
Poly/n-Substrate Gate MOSCAP
Akinwande, Gibby, Jain, Oh, Sun, Wong 59
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
over any surface topography whatsoever. Figures 41 and 42 present representative top-view images
of the gate MOSCAP peripheries in bright- and dark-eld, respectively. The images are taken from
the center die of Wafer B2.
Figure 41: Representative Gate MOSCAP Periphery (BF)
Admittedly, conclusive statements regarding Al/Si step coverage cannot be made on the basis
of such top-view images. However, several points are worth noting. In the Bright Field image of
Figure 41, considerable Si accumulation (presumable) is evident at the pad/MOSCAP step inter-
face. Such accumulation represents severe nonuniformity, increased resistance, and likely poorer
coverage at a crucial point in the metal layer. Also present in the BF image is an apparent break in
the Al/Si line at the top of the image, where the metal attempts to continue down a step onto the
gate oxide. Inability of the optical microscope to resolve coverage over the step is a possibility, but
the Dark Field image of Figure 42 appears to support the hypothesis that the coverage is indeed
poor and thus the likely cause of the open-circuit measurement. SEM images, which are included
in Section 6.3, indicate the near ubiquity of poor metal coverage over such steps and additionally
corroborates the hypothesis.
FOX MOSCAPs. In contrast to the Gate MOSCAP results, FOX capacitors generally pro-
vided attractive CV results, save p
+
Poly/n-Substrate devices for wafers other than B5. Figures 44
and 44 were obtained from the center die of Wafer B5 and present the best results for n
+
Poly and
p
+
Poly FOX MOSCAPs, respectively. Given the increased anisotropy and edge-point detection of
the P5000 used for B5 etching, these results are not surprising.
For the sake of comparison, Figures 45 and 46 present CV results for Wafer 2.
The p
+
Poly/FOX/n-Substrate result for Wafer B2 represents the best CV curve of the wafers
Akinwande, Gibby, Jain, Oh, Sun, Wong 60
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 42: Representative Gate MOSCAP Periphery (DF)
25 20 15 10 5 0 5 10 15 20 25
1.98
2
2.02
2.04
2.06
2.08
2.1
2.12
2.14
2.16
x 10
11
Applied Voltage, V
A
(V)
C
a
p
a
c
it
a
n
c
e
,

C

(
F
)
Wafer B5, Center Die, FOX nMOSCAP
dV/dt > 0
dV/dt < 0
Figure 43: Wafer B5 (Center) - n
+
Poly/FOX/p-Well MOSCAP
Akinwande, Gibby, Jain, Oh, Sun, Wong 61
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
25 20 15 10 5 0 5 10 15 20 25
1.9
1.95
2
2.05
2.1
2.15
2.2
x 10
11
Applied Voltage, V
A
(V)
C
a
p
a
c
it
a
n
c
e
,

C

(
F
)
Wafer B5, Center Die, FOX, p
+
Poly/ nSub pMOSCAP
dV/dt > 0
dV/dt < 0
Figure 44: Wafer B5 (Center) - p
+
Poly/FOX/n-Substrate MOSCAP
25 20 15 10 5 0 5 10 15 20 25
1.98
2
2.02
2.04
2.06
2.08
2.1
2.12
2.14
x 10
11
Applied Voltage, V
A
(V)
C
a
p
a
c
it
a
n
c
e
,

C

(
F
)
Wafer B2, Center Die, FOX, n
+
Poly/ pWell nMOSCAP
dV/dt > 0
dV/dt < 0
Figure 45: Wafer B2 (Center) - n
+
Poly/FOX/p-Well MOSCAP
Akinwande, Gibby, Jain, Oh, Sun, Wong 62
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
25 20 15 10 5 0 5 10 15 20 25
4.2
4.22
4.24
4.26
4.28
4.3
4.32
4.34
x 10
12
Applied Voltage, V
A
(V)
C
a
p
a
c
it
a
n
c
e
,

C

(
F
)
Wafer B2, Center Die, FOX, p
+
Poly/ nSub pMOSCAP
dV/dt > 0
dV/dt < 0
Figure 46: Wafer B2 (Center) - p
+
Poly/FOX/n-Substrate MOSCAP
etched using the standard prescribed Drytek etch process (not P5000). For the sake of completeness,
Figures 47, 48, and 49 present the other p
+
Poly/FOX/n-Substrate CV results from the center
dice of Wafers B1 and B3, and the bottom die of Wafer B3, respectively.
Figures 47-49 represent unusual results for MOSCAP characterization. The only known dif-
ference between Wafers B1-B3 and Wafer B5 is the use of the P5000 etch for B5. A tentative
conclusion that smaller diusivities for typical n-type dopants (P and As) may hinder their ability
to reestablish substrate doping continuity after overetching in the Drytek can be proposed [3]. More
detailed explanation of this potential eect is provided in sections to follow.
Particular attention should be paid to Figure 47, which presents the CV plot for the p
+
Poly/FOX/n-Substrate MOSCAP on the center die of Wafer B1. Although exhibiting the gener-
ally expected order-of-magnitude for C, the curve indicates an nMOSCAP rather than the pMOS
expectation. Such a reversal of the CV curve suggests identication of the course sta-introduced
fault wafer and its corresponding fault as an additional p-type or missed n-type substrate implant.
However, a concrete argument regarding the fault cannot be made on the basis of one CV plot,
especially given the widespread prevalence of device failures on all wafers and the lack of supporting
transistor data for this hypothesis. Sheet resistance results will indicate odd behavior on Wafer B1
as well, but a conclusive argument is still unreasonable given the lack of unequivocal evidence.
Table 39 summarizes the n
+
Poly/FOX/p-Well MOSCAP CV results and calculations for
all center dice to present wafer-to-wafer variation. Variation data for p
+
Poly/FOX/n-Substrate
Akinwande, Gibby, Jain, Oh, Sun, Wong 63
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
10 8 6 4 2 0 2 4 6 8 10
3.4
3.42
3.44
3.46
3.48
3.5
3.52
3.54
x 10
12
Applied Voltage, V
A
(V)
C
a
p
a
c
it
a
n
c
e
,

C

(
F
)
Wafer B1, Center Die, FOX, p
+
Poly/ nSub pMOSCAP
dV/dt > 0
dV/dt < 0
Figure 47: Wafer B1 (Center) - p
+
Poly/FOX/n-Substrate MOSCAP
25 20 15 10 5 0 5 10 15 20 25
3.97
3.98
3.99
4
4.01
4.02
4.03
4.04
4.05
x 10
12
Applied Voltage, V
A
(V)
C
a
p
a
c
it
a
n
c
e
,

C

(
F
)
Wafer B3, Center Die, FOX, p
+
Poly/ nSub pMOSCAP
dV/dt > 0
dV/dt < 0
Figure 48: Wafer B2 (center) - p
+
Poly/FOX/n-Substrate MOSCAP
Akinwande, Gibby, Jain, Oh, Sun, Wong 64
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
25 20 15 10 5 0 5 10 15 20 25
2.5
3
3.5
4
x 10
12
Applied Voltage, V
A
(V)
C
a
p
a
c
it
a
n
c
e
,

C

(
F
)
Wafer B3, Bottom Die, FOX, p
+
Poly/ nSub pMOSCAP
dV/dt > 0
dV/dt < 0
Figure 49: Wafer B2 (Bottom) - p
+
Poly/FOX/n-Substrate MOSCAP
MOSCAPs are not presented due to their order-of-magnitude discrepancy with the expected result.
Table 39: n
+
Poly/FOX/p-Well MOSCAP Data and Calculations
Wafer/Die C
ox
(acc) (pF) C
inv
(pF) t
ox
(nm)
B1/Center 1 21.216 20.809 488.05
B1/Center 2 21.319 19.867 485.69
B2/Center 21.357 19.947 484.83
B3/Center 21.287 19.896 486.42
B5/Center 21.497 20.051 481.67
Average 21.3552 20.1140 485.332
0.1042 0.3948 2.3644
Little wafer-to-wafer variation plagues the n
+
Poly/FOX/p-Well MOSCAP results. C(acc) =
C
ox
, C(inv), and t
ox
values are tightly distributed about their averages. Assuming the theoretical
20.709pF C
ox
value provided in Table 37 and the target FOX thickness of 500nm, the average mea-
sured value of oxide capacitance, 21.3552pF, diers by 3.1204%, while average measured t
ox
diers
by 2.9336%. Thus, the prescribed process ow for FOX growth is relatively accurate, especially for
FOX thickness, which is noncritical above a threshold needed for isolation.
Akinwande, Gibby, Jain, Oh, Sun, Wong 65
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Table 40 presents the n
+
Poly/FOX/p-Well MOSCAP CV results and calculations for Wafer
B3 for intra-wafer variation.
Table 40: n
+
Poly/FOX/p-Well MOSCAP Data and Calculations
Die C
ox
(acc) (pF) C
inv
(pF) t
ox
(nm)
Top 21.414 20.016 483.54
Left 21.660 20.264 478.05
Center 21.287 19.896 486.42
Right 21.275 19.907 486.70
Bottom 21.425 20.009 483.29
Average 21.4122 20.0184 483.600
0.1550 0.1482 3.4808
Intra-wafer variations are comparable to wafer-to-wafer variations. Specically, variations in C
ox
and t
ox
across Wafer B3 are more severe than trans-wafer variations in the center dice. However,
variation across B3 for C(inv) is less than that across wafers. Nevertheless, both wafer-to-wafer
and intra-wafer variations in FOX thickness are negligible, and the process ow seems reliable in
this regard.
For the sake of comparison with the Gate MOSCAPs, Figures 50 and 51 present the Bright Field
and Dark Field images of the n
+
Poly/p-Well FOX MOSCAP on the center die of Wafer B3. The
step onto oxide, while visibly steeper for the Gate capacitors, is more gradual and better-covered
for the thicker oxides. Open areas in the Al/Si alloy at boundaries are not apparent, supporting
the hypothesis that the poor metal coverage over relatively large steps played an important role in
Gate MOSCAP failures.
FOX/LTO MOSCAPs. As with the FOX MOSCAPs, FOX/LTO capacitors exhibit gen-
erally attractive results for p-Well devices but less impressive n-Substrate results. Figures 52 and
53 were obtained from the center dice of Wafers B3 and B1 and present the best results for p-Well
and n-Substrate FOX/LTO MOSCAPs, respectively.
Table 41 summarizes the Metal/FOX & LTO/p-Well MOSCAP CV results and calculations for
all center dice to present wafer-to-wafer variation. Wafer B5 is not included due to erroneous results,
which would skew the statistics beyond meaning interpretation. Variation data for Metal/FOX &
LTO/n-Substrate MOSCAPs are not presented due to their order-of-magnitude discrepancy with
the expected result.
As with FOX MOSCAPs, little wafer-to-wafer variation plagues the Metal/FOX & LTO/p-
Well MOSCAP results. Assuming the theoretical 18.8264pF C
ox
value provided in Table 37 and
Akinwande, Gibby, Jain, Oh, Sun, Wong 66
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 50: Representative FOX MOSCAP Periphery (BF)
Figure 51: Representative FOX MOSCAP Periphery (DF)
Akinwande, Gibby, Jain, Oh, Sun, Wong 67
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
25 20 15 10 5 0 5 10 15 20 25
1.98
2
2.02
2.04
2.06
2.08
2.1
2.12
x 10
11
Applied Voltage, V
A
(V)
C
a
p
a
c
it
a
n
c
e
,

C

(
F
)
Wafer B3, Top Die, FOX & LTO, Metal/pWell nMOSCAP
dV/dt > 0
dV/dt < 0
Figure 52: Wafer B3 (Center) - Metal/FOX & LTO/p-Well MOSCAP
25 20 15 10 5 0 5 10 15 20 25
2.6
2.8
3
3.2
3.4
3.6
3.8
4
x 10
12
Applied Voltage, V
A
(V)
C
a
p
a
c
it
a
n
c
e
,

C

(
F
)
Wafer B1, Center Die, FOX & LTO, Metal/nSub pMOSCAP
dV/dt > 0
dV/dt < 0
Figure 53: Wafer B1 (Center) - Metal/FOX & LTO/n-Substrate MOSCAP
Akinwande, Gibby, Jain, Oh, Sun, Wong 68
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Table 41: Metal/FOX & LTO/p-Well MOSCAP Data and Calculations
Wafer/Die C
ox
(acc) (pF) C
inv
(pF) t
ox
(nm)
B1/Center 21.112 20.022 980.091
B2/Center 21.874 20.662 946.74
B3/Center 21.671 20.471 955.61
Average 21.5523 20.3850 960.814
0.3946 0.3286 17.2737
the target FOX+LTO thickness of 1100nm, the average measured value of oxide capacitance,
21.5523pF, diers by 14.4791%, while average measured t
ox
diers by 12.6533%. Unlike the case
for FOX MOSCAPs, the prescribed process ow for FOX growth followed by LTO deposition
needs some modication. However, since the FOX and LTO layers are noncritical past a threshold
thickness for isolation, the nearly 15% variation may be negligible. Table 40 presents the
Metal/FOX & LTO/p-Well MOSCAP CV results and calculations for Wafer B3 for intra-wafer
variation.
Table 42: Metal/FOX & LTO/p-Well MOSCAP Data and Calculations
Die C
ox
(acc) (pF) C
inv
(pF) t
ox
(nm)
Top 21.111 20.006 980.96
Left 21.969 20.766 942.6
Center 21.671 20.471 955.61
Right 21.535 20.350 961.64
Bottom 21.863 20.635 947.22
Average 21.6298 20.4456 957.616
0.3351 0.2922 14.9768
Intra-wafer variations across B3 are smaller relative to wafer-to-wafer variations. Nevertheless,
both wafer-to-wafer and intra-wafer variations in FOX thickness may be negligible so long as a
minimum threshold for isolation is met.
LTO MOSCAPs. Only Wafer B5 exhibited moderately attractive results for Metal/LTO/Poly
MOSCAPs. Figures 54 and 55 present the CV curves for Metal/LTO/p
+
Poly and Metal/LTO/n
+
Poly, respectively, on the center die of Wafer B5.
While the curves themselves do not appear as expected, the extracted oxide thickness approxi-
mates the ideal value well. Table 43 summarizes the data for Wafer B5.
Akinwande, Gibby, Jain, Oh, Sun, Wong 69
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
10 8 6 4 2 0 2 4 6 8 10
1.7026
1.7028
1.703
1.7032
1.7034
1.7036
1.7038
1.704
x 10
11
Applied Voltage, V
A
(V)
C
a
p
a
c
ita
n
c
e
, C
(
F
)
Wafer B5, Center Die, LTO, Metal/n
+
Poly pMOSCAP
dV/dt > 0
dV/dt < 0
Figure 54: Wafer B5 (Center) - Metal/LTO/p
+
Poly MOSCAP
10 8 6 4 2 0 2 4 6 8 10
1.7596
1.7597
1.7598
1.7599
1.76
1.7601
1.7602
1.7603
1.7604
1.7605
x 10
11
Applied Voltage, V
A
(V)
C
a
p
a
c
it
a
n
c
e
,


C

(
F
)
Wafer B5, Center Die, LTO, Metal/p
+
Poly nMOSCAP
dV/dt > 0
dV/dt < 0
Figure 55: Wafer B5 (Center) - Metal/LTO/n
+
Poly MOSCAP
Akinwande, Gibby, Jain, Oh, Sun, Wong 70
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Table 43: Wafer B5 - Metal/LTO/Poly MOSCAPs
Device C
ox
(acc) (pF) C
inv
(pF) t
ox
(nm)
nMOSCAP 17.604 17.603 588.19
pMOSCAP 17.037 17.033 607.78
Average 17.3205 17.3108 597.985
0.4009 0.4031 13.8522
Assuming the theoretical 17.2575pF C
ox
value provided in Table 37 and the target LTO thick-
ness of 600nm, the average measured value of oxide capacitance, 17.3205pF, diers by 0.3651%,
while average measured t
ox
diers by 0.3358%. Thus, the LTO deposition process parameters seem
well-calibrated given the LTO MOSCAP results. Admittedly, two data points on a single wafer do
not constitute a representative sample of all dice, so conclusive statements cannot be made with
much condence, especially given the failure (open) of LTO MOSCAPs on all other wafers besides
B5. As before, this indicates the need to use P5000 etch procedures to the exclusion of Drytek.
6.1.4 Diodes
Measurement Methodology
Although there are four pn junction diode congurations with area and edge components, only
the poly-poly diodes gave acceptable IV characteristics. Other congurations didnt output enough
current for every die on every wafer. For poly diodes, voltage range of 10V to 10V is applied to
one electrode and the current from that electrode is measured to output the IV characteristics.
We obtained 8 results from Wafer B3, 4 from Wafers 1 and 2, and 1 result from B5.
Characterization Results
Figure 56 is a representative IV characteristic derived from the poly diode measurements.
The turn-on voltage and the breakdown voltage are rather conspicuous. The turn-on voltage
is extracted by extrapolating the linear part and taking the x-intercept point. Average values of
turn-on voltages and breakdown voltages for each wafer are given in Figure 57.
Note that there are only 4, 4, 8, 1 measurement results for wafer 1, 2, 3, 5 respectively. Turn-on
voltage is around 2 3V and the breakdown is near 5 6V.
Akinwande, Gibby, Jain, Oh, Sun, Wong 71
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 56: Representative poly-poly Diode IV Characteristic
Figure 57: Poly-poly Diodes Electrical Characteristics
Akinwande, Gibby, Jain, Oh, Sun, Wong 72
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Discussion
As forward bias is applied, the potential barrier for both electrons in n+ and holes in p+ is
lowered. Once turned on the carrier concentration increases exponentially with linearly increasing
bias. Therefore forward current is expected to increase exponentially with the applied voltage. At
reverse bias, the potential barrier is too high for any majority carrier to surmount. However p+
side electrons and n+ side holes can still wander into the depletion region and get swept to the
other side [5]. This is presented in Equation 41
I = I
0
_
e
qV
A
kT
1
_
(41)
From the fact that the breakdown voltage is relatively small and the process is very gradual, we
can say that the breakdown is due to tunneling. Other breakdown eects like avalanche breakdown
usually occurs at 30 100V depending on the doping of the lightly doped side. Also, at avalanche
breakdown the reverse current eectively goes o to innity very quickly [5].
Tunneling, namely the Zener process, is a phenomenon where a carrier has enough energy to
pass through a barrier to an empty state of the same energy (Figure 58).
Figure 58: Tunneling in a pn-Diode
One important thing is that the barrier thickness must be thin enough for the carrier to tunnel
through. This is only achieved when both sides of the pn diode is highly doped, which is just the
case for the n+ poly p+ poly diode. As reverse bias increases in magnitude, two things happen.
One, the carriers in the lled state increase and two, the barrier thickness gets even thinner. This
Akinwande, Gibby, Jain, Oh, Sun, Wong 73
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
tunneling phenomenon plays a signicant role to the breakdown process where the breakdown volt-
age is less than 6
E
G
q
6.7V [5].
6.2 Process Test Structures
6.2.1 Sheet Resistivity
Introduction
Resistivity, which is related to the free electron or hole concentration, is dened as in Equation
10, reproduced as Equation 42.
=
1
q (n
n
+p
p
)
cm (42)
Generally, only one of the two terms is important because n p or p n under most con-
ditions. The resistivity is thus a measure of the product of the mobility and the majority carrier
concentration. A measurement of thus provides n or p, provided the mobility is known [3].
The most common method of measuring the wafer resistivity is the four-point probe illustrated
in Figure 59.
Figure 59: Four-Point Probe Test Pad Conguration
Akinwande, Gibby, Jain, Oh, Sun, Wong 74
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
We basically seek to measure the sample resistance by measuring the current that ows for a
given applied voltage. This could be done with just two probes. However, in that case, contact resis-
tance associated with the probes and current spreading problems around the probes are important
and are not easily accounted for in the analysis. Using four probes allows us to force the current
through two pads and measure the voltage drop with the two inner probes using a high-impedance
voltmeter. Problems with probe contacts are thus eliminated in the voltage measurement since no
current ows through these contacts. In the 4-point probe structure shown in Figure 59 a current
IFORCE is forced through the I-1 FORCE and I-2 FORCE pads, resulting in a voltage VSENSE
across the V-1 SENSE and V-2 SENSE pads. The sheet resistivity can then be obtained using
Equation 43 where W and L are the dimensions of the thin-lm structure to be probed.
R
sheet
= R
measured
_
W
L
_
=
V
sense
I
force
_
W
L
_
(43)
Another common method for obtaining sheet resistance is by using the Van der Pauw technique,
illustrated in Figure 60.
Figure 60: Van der Pauw Test Pad Conguration
Van der Pauw shows that the resistivity can be measured for an arbitrary shape provided that
several conditions are met. The Van der Pauw structures consist of four contacts (labeled VDP-1,
VDP-2, VDP-3 and VDP-4 in counterclockwise sense) symmetrically arranged around an octagonal
Akinwande, Gibby, Jain, Oh, Sun, Wong 75
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
area. The sheet resistance can be obtained by forcing a current across two adjacent terminals and
measuring the resulting voltage developed across the other two adjacent terminals and subsequently
applying Equation 44 [8].
R
sheet
=

ln 2
R
measured
=

ln 2
V
12
I
43
(44)
Measurement Results
At least one die from wafers B1, B2, B3, and B5 has been measured for the sheet resistance
by both 4-point probe and Van der Pauw techniques. B4 was not evaluated because of poor metal
deposition. For each die, all the 16 structures (for 4-point probe) and 7 structures (for Van der
Pauw) have been measured. Wafers 2 and 3 had the most consistent numbers and generally showed
a larger number of working test structures. The average sheet resistance of wafers 2 and 3 are
presented in Table 44.
Table 44: Average Sheet Resistivity Measurements for Wafers 2 and 3
Wafer N
+
P
+
N
+
poly P
+
poly P-well 1 P-well 2 P-well 3 Metal
Wafer 2 6.3 26.5 7.8 8.1 412.5 155.8 6666.7 0.00046
Wafer 3 3.8 25.4 3.4 2.5 420.0 163.8 8750.0 0.00052
Typical measurement curves for 4-point probe and Van der Pauw are shown in Figures 61 and
60. The sheet resistivity is measured to be about 5/sq..
A chart of average sheet resistance measurement results for Wafers B2 and B3 by 4-point probe
is given in Figure 63
For the 4-point probe technique, wafers B2 and B3 give pretty consistent results and wafer B5
also gives comparable values. However, B1 data are not very good. The data shows us that for the
P
+
active, N
+
active, P
+
poly, N
+
poly, the sheet resistance by the 4-point probe method is around
5-20, and that of P-Well 1 (gate oxide and poly on top) and P-Well 2 (gate oxide with N
+
pinch)
is about 150-500. Sheet resistance of P-Well 3 (eld oxide on top) is very large, above 5000, and
that of metal is very small, around 0.1m. That is correct, since metal has small resistivity and
oxide has large resistivity. However, the sheet resistance measured by the Van der Pauw technique
is not consistent with that of 4-point probe.
Akinwande, Gibby, Jain, Oh, Sun, Wong 76
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 61: Representative (1m x 30m) 4-Point Probe IV
Figure 62: Representative (P-well with Oxide) Van de Pauw IV
Akinwande, Gibby, Jain, Oh, Sun, Wong 77
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 63: 4-Point Probe Sheet Resistance Wafer Comparison
Comparison with Simulation Results
The sheet resistance depends upon the junction depth and can be calculated from the dopant
prole. It can be solved as shown in Equation 9 and reproduced in Equation 45.

S
=
1
x
j
=
1
q
_
x
j
0
[n(x) N
B
(x)] [n(x)]dx
(45)
where q is the electronic charge, is the carrier mobility, N
B
is the background or impurity
concentration, and n(x) is the prole of the diused dopant.
In the case of the polysilicon sections, the value has to be calculated by numerical integration.
However, as the mobility of the polysilicon is highly varied, an approximate value of
1
2
that of
crystalline Silicon was used. Analytical, TSUPREM-IV simulation, and physical characterization
results are summarized in Table 45.
Table 45: Sheet Resistivity Analysis, Simulation, and Electrical Characterization Results
Material Analytical TSUPREM-IV Measured
nMOS Source 60.2 60 8.3
nMOS Poly 100.1 28 10
pMOS Source 39.6 52 30.8
pMOS Poly 367.7 249 10.8
Akinwande, Gibby, Jain, Oh, Sun, Wong 78
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
The measured sheet resistance is relatively small compared with simulation results. The dis-
crepancies are greatest for the polysilicon regions. This is to be expected since the actual mobility
and diusivity in the poly material is heavily fabrication-dependent, which cannot be predicted
either by calculation or by simulation.
6.2.2 Contact Chains
Methodology
A contact chain goes through active/poly regions to contact holes to metal and back to ac-
tive/poly regions, as in Figure 64. Since the resistance of aluminum is very small, the resistance of
a contact chain consists of the resistance of the diused region and the contacts.
Figure 64: Contact Chain Schematic Diagram
Contact chains are used to test the contact integrity. In one measurement, 20 to up to 1000
contacts are tested. Since these contacts are connected in series, one fault will make the whole
chain an open circuit. In this respect, contact chains can also be used to gure out the yield or the
reliability of the contacts.
Although contact chains are not a good structure to measure contact resistances, we can con-
rm a linear relationship in the resistance to the chain length, namely the number of contacts.
By applying a voltage to the ends of the chain and measuring the current, the resistance of the
contact chain can be evaluated. We obtain an IV plot by sweeping the voltage, and calculate the re-
sistance from the data of both active and poly regions for 4m x 4m and 2m x 2m contact areas.
Characterization Results
Both reliability and the straightforward linear dependency of the resistance to the number of
contact units were obtained from the poly contact chains. However, only negligible current on the
order of pA were observed from almost every contact chain on the active regions. The computed
resistance approached that of air, which suggests that the contact chain is poorly connected and
can be considered an open circuit.
Akinwande, Gibby, Jain, Oh, Sun, Wong 79
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
P+ poly contact chains gave nice clean IV plots as shown in Figure 65, where n+ poly contact
chains gave nonlinear plots shown in Figure 66. But as the number of contact units increase, the
current of the n+ poly contact chain becomes linear to applied voltage. Well discuss these obser-
vations in the following sections. Since the n+ poly contact chain for small contact unit number
has a resistance that falls o at high biases, we take the data point near zero bias as the resistance
of the total chain. The singularity of the resistance at zero bias is due to zero current; well ignore
this point hereafter.
Figure 65: 20 Contact (2m x 2m), p
+
Poly IV Characteristic
The resistance of one contact unit, which is composed of a metal, two contact holes and the
(poly) silicon region, is calculated and presented for wafers B1, B2 and B3 in Table 46. The metal
resistance is assumed to be small and will be neglected. The resistance given in Table 46 is basically:
2R
C
+R
poly
. Center dice of each wafer were measured.

Both the IV and contacts (#)-dependent resistance are nonlinear. This means that the re-
sistance of each chain unit is not uniform throughout the structure. So the recorded values may
diverge from the actual resistance of one contact chain unit.
Resistances are in units of , and blanks mean that the contact chain was broken, giving a high
Akinwande, Gibby, Jain, Oh, Sun, Wong 80
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 66: 20 Contact (2m x 2m), n
+
Poly IV Characteristic
Table 46: Contact Chains: Wafer-to-Wafer Variation
p
+
Poly n
+
Poly
Wafer 4m x 4m 2m x 2m 4m x 4m 2m x 2m
B1 224 Linear 453 Linear - - - -
B2 175.5 Linear 257.5 Linear 1.41k Nonlinear

6.42k Nonlinear

B3 183.5 Linear 274.5 Linear 4.49k Nonlinear

19.3k Nonlinear

Akinwande, Gibby, Jain, Oh, Sun, Wong 81

CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
resistance. N+ poly strangely has huge resistance values. Since the contacts and metal were made
at the same time for both n+ and p+, the cause should be R
poly
.
Wafer variations for p+ poly B2 and B3 are small compared to that of B1. Wafer B1 seems to
have higher p+ poly chain unit resistance. This can be due to thinner poly deposition and more
current crowding, or process variations. The n+ poly values seem to be varying from structure to
structure. Eects happening in the n+ poly contact chain will be discussed in the next subsection.
Now to nd out on-wafer variations, we choose wafer B3 which has the nest results, presented
in Table 47. Since the periphery of the wafer might have been subject to external damage or
non-uniformity in the process, we measured the second-most die of top, bottom (at), left, right.
Table 47: Contact Chains: Intra-Wafer (B3) Variation
p
+
Poly n
+
Poly
Die 4m x 4m 2m x 2m 4m x 4m 2m x 2m
Top - - 689 Linear - - 876k Nonlinear
Left - - 276 Linear - - 10.7k Nonlinear
Right - - 275.5 Linear - - 29.74k Nonlinear
Bottom 193 Linear 267.8 Linear 849.5 Nonlinear

579.9 Nonlinear

The 4m x 4m contacts show that they are not reliable. Resistance values fall as we move
from top to bottom. Since these are not the results of every die on every wafer, they can be due to
just contingent statistical variations. Poly deposition thickness can be thicker on the bottom and
thinner on the top. Also, etching of the poly might have been incomplete in some areas of the wafer.
Discussion
As mentioned before, the IV plot of the n
+
poly chains have a strong nonlinearity, while the
p
+
poly does not. But even in n
+
poly, as contact chain units increase, the voltage applied to each
unit decreases, making this nonlinearity disappear. When a high voltage is applied to a single unit,
the current goes up. It is thought that a high resistance parallel current path is turning on. It can
be pictured as multiple resistances in parallel competing with each other. A more detailed picture
of the cross section of the chain must be known to gure out the exact parallel path in concern.
One possibility is current crowding. The current density is nonuniform across a contact, and the
current is higher at the front edge of the planar metal contact. This is because the current doesnt
ow through the whole poly layer but relatively through the conductive top side, which has higher
doping and also the shortest path between contacts. As more voltage is applied along a contact,
current can start to ow through additional paths other than along the surface of the poly, since
the polysilicon layer is not thin. In thin layers, current crowding is inevitable. If more current is
Akinwande, Gibby, Jain, Oh, Sun, Wong 82
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
owing through the whole contact the resistance becomes lower, like Figure 66.
Then why would this eect occur only in the n
+
poly? This may due to the high resistance
measured in the n
+
poly chain. High conductivity in the p
+
poly chain would have less eect of
competing resistances. If it were that the contact resistances are roughly on the same scale for
both cases (contact resistances presented in next section), then the high resistance is mostly due to
the n
+
polysilicon layer, as referred already before. There can be many causes of high resistance
in polysilicon. The dose of the n
+
source/drain implant may have been too low. By TUSPREM4
simulations, if the dose were the same as the boron blanket implant (1E15cm
2
), the sheet resis-
tance increases by approximately a factor of 10.
The 4m x 4m case has lower resistance than the 2m x 2m case, explaining that larger area
collects more current since the polysilicon layer is not thin to make current crowding severe. But
weve obtained more results from the smaller 2m x 2m contact size than from the 4m x 4m,
which is counterintuitive. It can be thought that since the contact area is bigger there is a higher
probability for a lateral metal break (refer to the SEM picture section) or other faults. One break
will make the whole chain open.
There were no results from the active regions. The active regions are further down from the
top of the LTO where the metal is deposited. It is evident that the metal step coverage is poor,
and the deeper the step is, the harder for the metal to get down to the diusive regions. Quality
of the metal step coverage will be shown through SEM images to follow.
6.2.3 Contact Resistance
Contact Congurations
Kelvin contact structures are used to measure the contact resistances of various contacts. In
the process, there are four kinds of contacts introduced; contacts to N+ active, P+ active, N+ poly
and P+ poly. All of these are measured for four dierent contact areas; from 1.5m x 1.5m to
4m x 4m.
Testing Methodology
The Kelvin structure used for contact resistance extraction is presented in Figure 67
The resistance through the current path 2 to 4 is: 2R
C
+R
active/poly
+R
parasitic
; resistance of
the metal regions can be neglected. To get an isolated contact resistance, the voltage across the
contact only is required. Basically the Kelvin structure forces a current through pads 2 and 4 and
measures the voltage between 1 and 3. The contact resistance is calculated as in Equation 46
R
C
=
V
13
I
24
(46)
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CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 67: Kelvin Contact Resistance Schematic
Since there is very small current owing between pads 1 and 3, the voltage drop across the ac-
tive/poly region from pad to contact is negligible. For a more accurate measurement, we can
repeat the procedure above and get R

C
=
V
24
I
13
. The average of the two resistances will give a
contact resistance taking into account possible asymmetries of the structure [9].
Characterization Results
To compare contact size, 4m x 4m and 1.5m x 1.5m are measured for all contact gura-
tions. Among the data measured, only the center die is reported. There are several plot shapes
that occur frequently. We will classify them as Schottky, ohmic and completely linear. Some of the
results are in-between Schottky and ohmic form. For linear IV plots, the resistance extraction is
straightforward. On the other hand, extraction of resistance is more dicult for nonlinear plots.
For Schottky behavior contacts, the turn-on voltage and the dierential resistance (slope of the V I
plot) after turn-on are listed in Table 48, where

indicates near-perfect Schottky behavior.
Figures 68-70 present representative Schottky, Ohmic, and Completely Linear contact resistance
curves, respectively. Figure 68 describes a 1.5m x 1.5m p
+
active contact on the center die of
Wafer B1. Figure 69 describes a 4m x 4m n
+
poly contact on the center die of Wafer B3. Figure
70 describes a 1.5m x 1.5m p
+
poly contact on the center die of Wafer B2.
There are two kinds of Schottky contact plots that have been measured, one with small os-
cillation and one without it. The Schottky contacts that have oscillating noise have a dierential
Akinwande, Gibby, Jain, Oh, Sun, Wong 84
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Table 48: Kelvin Contact Resistance Results
Wafer Region 4m x 4m 1.5m x 1.5m
B1 n+ active Schottky R
d
= 18.2k, V
t
= 1.22V Schottky R
d
= 19.2k, V
t
= 0.55 V
p+ active In-between - Schottky

R
d
= 2.54k, V
t
= 0.36V
n+ poly Schottky R
d
= 17.4k, V
t
0.71V Schottky R
d
= 32.9k, V
t
= 0.97V
p+ poly - - Schottky

R
d
= 3.35k, V
t
= 0.2V
B2 n+ active Schottky R
d
= 14.2k, V
t
= 0.95V Schottky R
d
= 10.3k, V
B
= 1.10V
p+ active Linear R = 85 Ohmic -
n+ poly Schottky R
d
= 14.8k, V
t
= 0.82V Ohmic -
p+ poly - - Linear 685
B3 n+ active Schottky R
d
= 18.2k, V
t
= 1.22V Odd R
d
= 11.2k, V
B
= 1.48V
p+ active Linear 85 Ohmic -
n+ poly Ohmic - - -
p+ poly Linear 20 Linear 732
B5 n+ active - - Linear 262
p+ active Linear 58 Ohmic -
n+ poly - - Ohmic -
p+ poly Odd - Linear 770
Figure 68: Kelvin Contact Resistance - Representative Schottky
Akinwande, Gibby, Jain, Oh, Sun, Wong 85
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 69: Kelvin Contact Resistance - Representative Ohmic
Figure 70: Kelvin Contact Resistance Representative Completely Linear
Akinwande, Gibby, Jain, Oh, Sun, Wong 86
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
resistance around 17k and a turn-on voltage that ranges from 0.7 to 1.1V. The clean Schottky con-
tact behavior contacts have both a lower dierential resistance (around 3k) and turn-on voltage
(around 0.3V). The perfect Schottky contacts were only observed in B1 p+ diusive. For carriers
in the metal to get into the silicon, the barrier height is
B
=
M
, where
M
is the metal work
function and is the silicon electron anity. For carriers in the semiconductor to get into the metal
they must surmount a barrier whose height is V
bi
=
[
B
(E
C
E
F
)]
q
=
1
q
(
M

S
). From Fermi-level
pinning (discussed in next section), V
bi
=
2
3
E
G
(E
C
E
F
) for n-type and V
bi
=
1
3
E
G
(E
F
E
V
)
for p-type. The dierence in turn-on voltage for contacts to n+ and p+ can be explained by this
barrier height dierence.
Ohmic contacts have a dierential resistance of 10k around zero bias. As current increases
at high biases the resistance reduces to a few kilo-ohms (2.5k). An ohmic-like behavior shows
that there is no barrier from semiconductor to metal at zero bias. So even a small positive voltage
will result in large currents. Under negative bias, a small barrier for the majority carriers from the
metal to the semiconductor exists. Since the barrier is small, the barrier vanishes at few tenths of
a volt [5].
Linear plots have very small contact resistance below 1k, with an average of 85. Plots that
are linear indicate a contact resistance that is independent of the current.
Discussion
N+-type semiconductor regions that have doping dependent workfunctions smaller than the
metal workfunction will show a Schottky nature in the contacts. Contrarily, if the semiconductor
workfunction is smaller than the metal workfunction, the electrical nature of the MS contact will
be ohmic, and vice-versa for p+-type silicon. The workfunctions of n+ silicon, p+ silicon and
aluminum are roughly 4.05eV, 5.25eV, 4.1eV, respectively.
So by only looking at the workfunction dierences, both contacts to n+ and p+ silicon should
be rectifying. But in practice, surface states usually dominate the characteristics above. Due to
a large density of surface traps the Fermi-level gets pinned at the trap level. Experimentally, it is
found that the surface states show a pronounced peak at
1
3
E
G
. Thus, fabrication of an ohmic is
dicult since both material properties and practical technological issues are involved [10].
Choosing appropriate materials with the desired workfunctions wont work due to the Fermi-
level pinning. Another way is to dope the semiconductor heavily enough so that tunneling is
possible. Figure 71 shows the dependence of the contact behavior to level of doping.
Lastly, Figure 72 presents the V I curve for a 1.5m x 1.5m contact to n+ active on the center
die of Wafer B3. This can be either a Schottky contact with a sharp turn-on voltage or a linear
plot with a voltage barrier at transition from negative to positive bias. One possibility is that a
very thin native oxide grew on top of silicon before the contact holes were formed. This will make
a voltage barrier that will be overcome only at suciently large voltages where the carriers can
Akinwande, Gibby, Jain, Oh, Sun, Wong 87
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 71: MS Contacts - Doping Dependence
surmount the barrier.
6.2.4 Continuity and Isolation
In order to evaluate the integrity of the interconnects within a given layer, continuity and isolation
structures were fabricated and tested. For continuity, the test structure is a continuous line that
snakes back and forth. The lines are made of dierent materials (poly-Si or metal for example)
and are in either 2 or 4 m widths. One key structure is the metal line over the features of the
surface, from which quality of metal step coverage over sharp edges can be evaluated. These results
are discussed in the following section. The isolation test structure consists of two interpenetrating
combs of 30-300 m stripes of metal which cover various surface features. The spacing between the
lines varies between 2 to 4 m.
To test these structures, a voltage was applied across terminals A and B and the resulting
current was measured. For continuity measurements, a high resistance indicates the presence of an
unwanted open circuit in the line. This could be due to poor denition of the lines or poor material
quality. For wafer B2, the continuity measurement of the 2 m metal lines is shown in Figure 73.
The high current measured indicates low resistance in the line, and thus a working metal line. A
summary of all the continuity testing is found in Table 49.
Akinwande, Gibby, Jain, Oh, Sun, Wong 88
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 72: n
+
Active Contact - VI Characteristic
-20x10
-3
-10
0
10
20
C
u
r
r
e
n
t

(
A
)
-4 -2 0 2 4
Voltage (V)
200
150
100
50
0
R
e
s
i
s
t
a
n
c
e

(

)
Figure 73: Current vs. Applied Voltage of Metal Lines
Akinwande, Gibby, Jain, Oh, Sun, Wong 89
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Table 49: Continuity Testing Summary
Wafer 1 Wafer 2 Wafer 3 Wafer 5
Width (m): 2 4 2 4 2 4 2 4
N
+
Snake

P
+
Snake

P
+
Poly Snake
N
+
Poly Snake




N
+
Poly Snake over Active Steps




P
+
Poly Snake over Active Steps


Metal



Metal over Parallel N
+
and Poly Stripes Tilted at 5 Degrees
Metal over All Topography, Horizontal
Metal over All Topography, Vertical
P-well in Active Region

P-well in Field Region

*Wafer 4 was not tested due to poor metal quality
With the exception of the P+ snake, the N+ and P+ lines show inconsistent results from wafer
to wafer. This may be due to dierences in etching (for example, dierent electrode position during
etching). The results for wafers B1 and B3 showed dierences between the 2 and 4 m line widths,
thus possibly indicating the quality of the alignments of each masking layer. This is consistent
with observations during fabrication, where the fabrication test structures of wafer B2 showed an
alignment problem. For the metal lines, the continuity results are consistent with our observations
during fabrication and testing in that metal quality was poor and thus not expected to yield a high
percentage of working devices. For the larger metal lines, the metal itself showed no open circuits,
but once measured over features, the metal lines no longer appear continuous. This is conrmed in
the SEM images, found in section 6.3. Finally, the p-wells show continuity in both active and eld
regions for all of the wafers tested.
The isolation structures were tested similarly to the continuity structures to detect any unde-
sirable short circuits, which could due to stringers caused by inadequate etching, or the presence
of a particle that would cause the metal combs to come into contact. In the case of isolation, if a
large resistance (small current) is measured, then the structure is adequately isolated.
In our isolation testing, we found that the majority of the structures were well isolated from
one another. In testing the metal lines and the metal over active and poly stripes, all resulted
in very low current values (on the order of pico amperes). One unexpected result was ohmic or
conducting behavior in the P+ active region for the 4 m line spacing in all the wafers we tested.
This could indicate that one etch step in the process is inadequate. However, all 2 m spacings
for the same region yielded isolated structures. On wafer B5, the N+ active region yielded a low
resistance. This may indicate an etching problem that was isolated to this one wafer.
Akinwande, Gibby, Jain, Oh, Sun, Wong 90
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
6.3 SEM Test Structures
SEM images were taken of wafers B2 and B5. The wafer was carefully cleaved to isolate the center
die, then cleaved again to reveal the SEM cross-section structures on each die. The sample was
then mounted at a 45
o
angle and inserted into the microscope. The 45
o
orientation oers two
advantages. First, images of the sample surface can be taken simultaneously without the need to
image an additional sample. Secondly, when oriented at 90
o
, the electron interaction with the edge
of the sample can obscure the contrast from the structure itself. By tilting the sample to 45
o
, we
can minimize this eect to get the best images possible.
In Figure 74, the cross-section of a 20 m width transistor is imaged. In the gure, the alu-
minum contact, the bright feature on the left, and the gate electrode can be clearly seen. The
thin bright line below the gate electrode is the gate oxide. In this image, two distinct layers on
top of the gate electrode can be seen. The layer directly on top of the gate appears to have the
same degree of contrast to that of the gate oxide. It reasonable that some thermal oxide could
have grown on top of the polysilicon gate, as during the LTO densication step [1], there is 30min
reow which is carried out in steam at a temperature of 950
o
C. In addition, this steam reow
is bracketed by dry oxidations. Under these conditions, thermal oxidation of the silicon would
denitely be reasonable. Oxide growth would occur in all areas of exposed silicon. There is evi-
dence of oxide (a layer of lighter color) in the region between the gate and aluminum contact as well.
Figure 74: Cross-Section of 20 m Gate Width Transistor
Akinwande, Gibby, Jain, Oh, Sun, Wong 91
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
A magnied image of the gate electrode and gate oxide is shown in Figure 75. The thicker,
darker gate electrode layer shows a fracture surface consistent with that of silicon. The gate oxide
is very uniform across the entire image. Since the cleaved edge is oriented at 45
o
in the SEM,
the thicknesses of the layers can not be determined directly from the scale bar (thicknesses from
image must be multiplied by

2). From this estimation, the gate oxide is found to be very close
to the 40 nm predicted by analytical calculations and simulations. However, the polysilicon gate is
approximately 380 nm, far from the 500 nm that was deposited. If thermal oxide was indeed grown
during the LTO reow, then a decreased gate thickness would be reasonable, as the underlying
silicon would be consumed during oxidation.
Figure 75: Magnied Cross-Section of 20 m Gate Length Transistor
A large fabrication problem that was encountered during processing was the poor quality of the
aluminum metallization. As this was a critical step in forming the contacts to the devices, it was
essential that aluminum depositions be well done. Unfortunately this was not the case. Figure 76
shows the surface of the width series transistors. The poor quality of the aluminum is apparent
with the presence of pits and voids on the surface. The aluminum became a problem for other
structures on the die as well. A surface view of the contact chains is shown in Figure 77, with a
magnied image of the region in between the chain links in Figure 78. A continuity test structure,
a metal line over all topographical features, is shown in Figure 79. Magnied images of this metal
line are found in Figures 80 and 81.
For the metal continuity line, there are distinct regions of metal discontinuity. For example, on
the left side of Figure 79 the aluminum appears as an island, completely isolated from the other
end of the metal line. In the middle of the metal line, Figure 81 there is a section of patchy
Akinwande, Gibby, Jain, Oh, Sun, Wong 92
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 76: Surface of Width Series Transistors
Figure 77: Surface of Contact Chains
Akinwande, Gibby, Jain, Oh, Sun, Wong 93
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 78: Magnied Image of Link within Contact Chains
Figure 79: Surface Image of Continuity Structure: Metal over All Topography
Akinwande, Gibby, Jain, Oh, Sun, Wong 94
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
Figure 80: Magnied Image of Continuity Structure End
Figure 81: Magnied Image of Continuity Structure Middle
Akinwande, Gibby, Jain, Oh, Sun, Wong 95
CIS/CMOS-II Modeling/Fabrication/Characterization 6 CHARACTERIZATION
metal, where the metal uniformity is poor. The regions were there is little or no metal seem to
correspond to regions of higher topography. If we consider the lithography step, we recall that
the wafer was coated with photoresist to dene the metal lines. Reviewing the process run sheet
[1] reveals that for the aluminum lithography, the program on the automated photoresist coater
(program 7) was designed to coat the wafer with 1 m of resist. This was the same program used
at the beginning of the process, where there were no topographical features yet, just blanket oxide.
By the end of the processing, features such as the 500 nm poly gate had been patterned onto the
wafer. If we consider the thermal oxide formed on top of the poly gate, its eective thickness would
be even greater than 500 nm. So, if 1 m of resist was coated, but would have been spun to leave
a at surface, then regions with higher surface features (such as the poly gate) would have been
coated with less resist. Thus, during etching, it may have been possible for the etching to have
gone through the photoresist and start to etch the aluminum. Coupled with the fact that visual
observations of the wafers showed areas with little to no aluminum coverage, it is not surprising
that metal lines over topographical features failed the continuity testing.
Finally, out of all the devices that were tested, the smallest working transistor was the 1.5 by
1.5 m device, which was also the smallest transistor fabricated on each die. A cross-section of this
device is shown in gure 82. Our process successfully patterned this device, the dimensions of which
are roughly twice the minimum feature size possible using conventional lithography techniques in
the Stanford Nanofabrication Facility.
Figure 82: Cross-Section of Minimum Dimension Device
Akinwande, Gibby, Jain, Oh, Sun, Wong 96
CIS/CMOS-II Modeling/Fabrication/Characterization 7 DISCUSSION
7 Discussion
7.1 Finding The Fault Wafer
As mentioned in Sections 6.1.3 and 6.2.1, Wafer B1 exhibited particularly unusual behavior. Fig-
ure 47 indicated a reversal in the p
+
/FOX/n-Substrate CV curve to indicate nMOS behavior.
This could be the result of an additional p-type or an omitted n-type substrate implant. How-
ever, MOSFET results do not corroborate this hypothesis. Rather, transistor results suggest some
failure in Wafer B2 based on a much larger V
t
range relative to B1 and B3. Given the lack of
sucient unequivocal evidence supporting either hypothesis, particularly suboptimal Al/Si alloy
deposition/coverage, and the prevalence of unexpected device and process characterization results,
a conclusive statement regarding the identity of the fault wafer (between B1 and B2) and its cor-
responding fault cannot be made condently.
7.2 pMOSFET Results
For devices with matching threshold voltages (specically, PMOS1 and PMOS2), simulated results
coincided remarkably well with fabricated devices. In comparing Figures 4 and 5 with 21 and 24,
one can see the similarity, remembering that the simulated gures are two-dimensional and must
be multiplied by gate width (100 m in both cases) to mimic the real device characteristics. The
notable dierence is in the non-zero slope of the PMOS2 curve, caused by channel length modula-
tion or possibly DIBL. The increase in drain current with increasing drain voltage was a common
problem seen in many devices, even with a V
g
of 0 V.
Also, when comparing simulated subthreshold slopes with those of fabricated devices, we nd
the measured values are far worse than those expected. In particular, leakage current under V
g
= 0V
and V
d
= 0.2V bias conditions could be as high as 1E-10 A for long-channel devices, where the
simulated result was around 1E-14 A for a 100 m gate width device.
Of particular concern was the wide range of observed threshold voltages. Even on the better
wafers, the standard deviation was slightly less than one volt, which equates to a six-sigma variation
of almost six volts!
A possible explanation for these problems is hinted at in the channel mobility calculations.
While PMOS2 shows a realistic
P
(105 cm
2
/Vs) for a surface channel device, the value of 216
cm
2
/Vs measured for PMOS1 was much larger than even the low-eld surface mobility (160
cm
2
/Vs). However, when using a buried channel model, the calculated value (209 cm
2
/Vs) ap-
proaches the measured value.
It is therefore reasonable to hypothesize that some of the pMOS devices have unintentionally in-
troduced buried channels. This could be caused by the introduction of p-type dopantsspecically
Boronto the surface of the semiconductor. Improper management of thermal budget, a low-
quality gate oxide, or an uncontrolled gate deposition that resulted in a columnar crystal structure
could all assist in the gate dopant diusing through the gate oxide.
Akinwande, Gibby, Jain, Oh, Sun, Wong 97
CIS/CMOS-II Modeling/Fabrication/Characterization 7 DISCUSSION
In small quantities, Boron would compensate the substrate doping altering the threshold voltage.
This would also reduce the drain/channel barrier height, increasing leakage current. In addition,
the eectively reduced substrate doping would cause the drain/channel depletion region to reach
further into the channel at a given drain bias, leading to enhanced DIBL eects. In these quan-
tities, the additional introduction of dopants would reduce mobility from the expected value due
to increased impurity scattering. In larger quantities, the introduced dopant could cause a buried
channel eect, allowing increased hole mobility.
Diusion of Boron through the gate oxide can explain the positive shift in threshold voltage.
However, the negative shifts observed in threshold voltageespecially on wafer B2, where V
t
could
be as large as -14 Vneed another explanation. In general, this could be caused by an increase
in gate capacitance, or an increase in surface doping. A change in Q
f
or
MS
could also cause
this, though they are less likely, since the former is only a small eect the a change in the latter
without a new gate material. While CV measurements could answer the question about reduced
gate capacitance, the low quality of our metalization process prevented reliable gate capacitance
measurements. (See Section 6.3) SEM images, however, indicate a reduction in gate polysilicon
thickness to 380 nm, as opposed to the expected 500 nm. As previously suggested, this reduction
was likely caused by the thermal oxidation of the polysilicon gate during LTO deposition. Because
Boron preferentially segregates into oxide layers, it is possible that this high-temperature growth
step removed Boron from the gate electrode. The overall concentration of Boron in the gate would
then be reduced, increasing the severity of gate depletion eects. This would be evidenced by a
reduction in gate capacitance, leading to a negative shift in threshold voltage.
7.3 Comparison of Wafers B2 and B5: Gate Etch
During testing, it was found that although working pMOS devices were found on every wafer,
working nMOS devices were only found on wafer B5. This was an interesting result, and looking
back at the process, the only dierence between wafer B5 and wafers B1-B4 was the polysilicon
gate etch. For wafers B1-B4, the Drytek plasma etcher was used, while for B5, the Applied Mate-
rials Precision 5000 (P5000) etcher was used. The P5000 is a magnetically-enhanced reactive ion
etch (MERIE) system which has four dedicated chambers and is software controlled. There are two
main dierences between the Drytek and P5000. The P5000 is equipped with endpoint detection so
etch rates and breakthrough points are easily determined. For the Drytek, completion of etching
is done by visual inspection, is a far more inaccurate technique, and there is wide variability in
etch rates between each of the six electrodes in the Drytek. This can lead to the overetch of some
wafers, and underetching (and hence short circuits) of other wafers. The second dierence between
the two system is etch prole. The P5000 can produce better proles while the Drytek tends to
produce more sloped proles.
In investigating how the processing aected nMOS dierently from pMOS, it is important
Akinwande, Gibby, Jain, Oh, Sun, Wong 98
CIS/CMOS-II Modeling/Fabrication/Characterization 7 DISCUSSION
to compare nMOS vs. pMOS. In nMOS the shallow junction dopant was Boron, while for pMOS it
was Arsenic. Boron is well known to have a high diusivity, thus resulting in larger junction depths
for pMOS (1.26 m) than for nMOS (0.59 m) (see Section 2.3 for more details). The smaller
nMOS junction (both in terms of depth and in the lateral dimension) is then more susceptible to
gate alignment and denition problems.
SEM images of the cross-sections of wafers B2 (Figure 83) and B5 (Figure 85) show the etch
proles of the polysilicon gate. In both cases, the etch prole is slightly sloped and no undercutting
is observed. There are no signicant dierences between the etch proles of the Drytek and P5000
wafers. This leaves us with the role of endpoint detection. It is very likely that in the Drytek
case, there was overetching during the gate etch. Underetching is less likely because this would
have caused a short circuit, which would have been detected during the electrical measurements.
If overetching did occur, then the nMOS shallow junction regions would have been damaged, and
the source/drain regions could have become disconnected from the channel. This may have been
the reason for lack of nMOS results.
Figure 83: Cross-Section of Wafer B2
Returning to the SEM images however, does not show signicant evidence of overetching. A
continuous layer of thermal oxide appears to extend from under the gate all the way to under the
aluminum contact. If overetching did occur, it may be expected that this thermal oxide layer gets
interrupted near the edge of the gate. In the image, the substrate surface dips slightly to the right,
but this is consistent with the consumption of silicon during oxidation (see Section 6.3). However,
it could be that overetching does not produce enough contrast in the SEM or that the current
images of the SEM test structures are not truly representative of the nMOS devices.
Akinwande, Gibby, Jain, Oh, Sun, Wong 99
CIS/CMOS-II Modeling/Fabrication/Characterization 7 DISCUSSION
Figure 84: Cross-Section of Wafer B5
Figure 85: Cross-Section of Wafer B5, 20 m Gate Length
Akinwande, Gibby, Jain, Oh, Sun, Wong 100
CIS/CMOS-II Modeling/Fabrication/Characterization 7 DISCUSSION
7.4 Suggested Process Improvements
7.4.1 Wafer B1 Sheet Resistivity
Sheet resistance data obtained with the four-point technique was observed to be much worse in
general for Wafer B1 as compared to Wafer B2 or Wafer B3. This suggests a wafer-wide problem
on Wafer B1 resulting in high resistance values. A graph comparing similar structures on the bad
wafer (Wafer B1) and the good wafer (Wafer B2) is shown in Figure 86.
Figure 86: B1/B2 Sheet Resistance Comparison
Since the resistivity data on Wafer B1 is orders of magnitude higher than Wafers B2, B3, or
B5, it can be concluded that there is either a metal discontinuity or a native lm of oxide on the
contact pads of these structures. The latter reason is unlikely because the probes were observed to
make good connection with the contact pads. It is therefore reasonable to blame the higher sheet
resistance on Wafer B1 as the result of poor metallic continuity. This discontinuity maybe a result
of diculty achieving uniform aluminum etches above a non-planar LTO layer.
Ideally, the LTO should planarize the surface but in practice the deposited LTO thickness is
sensitive to gas ow transport and therefore regions in the wafer center and wafer periphery have
dierent thicknesses of LTO. This leads to a non-planar surface and the non-planarity can propa-
gate to subsequent higher layers. The consequence of a non-planar LTO for Al etch is that certain
regions may experience Al over-etch and other regions may suer from Al under-etch. This could
potentially lead to an absence of Al (open circuit), and high sheet resistance data.
Indeed the LTO deposition was observed in the clean room to be non-uniform, even though
care was taken during deposition to rotate the wafers to achieve uniform deposition. Nonetheless,
some degree of non-uniformity still persists.
Akinwande, Gibby, Jain, Oh, Sun, Wong 101
CIS/CMOS-II Modeling/Fabrication/Characterization 7 DISCUSSION
To achieve better planarity, one could perform chemical mechanical polishing (CMP) after LTO
deposition. This would lead to a much more planar surface and also give the EE410 students a feel
for the precision of CMP techniques. Using CMP after LTO deposition would signicantly improve
the EE410 CIS/CMOS-II process and lead to more working and more consistent wafers.
7.4.2 General Process Improvements
The large number of non-working devices calls for other process improvements in the EE410
CIS/CMOS-II process ow. They are:
Metallization: Aluminum
While most testing showed that the devices had been well fabricated, due to the poor quality
of the aluminum (large number of pits and voids) contacting to the devices became very
dicult. Replacement of the Gryphon deposition is proposed.
Metallization: Photoresist
As discussed in Section 6.3, a thicker layer of photoresist may be helpful in avoiding unwanted
etching of the aluminum metal lines. Currently the same photoresist thickness is being used
on the bare silicon wafer and at the end of the process when topographical features have
already been patterned.
Polysilicon Gate Etch: P5000
The fact that the only working nMOS devices would be found on wafer 5 is attributed to
the fact that the gate was etched using the P5000 etcher. This is a far better system to use,
as the proles can be improved over the Drytek, and enables the use of essential endpoint
detection. See Section 7.3 for more details.
Akinwande, Gibby, Jain, Oh, Sun, Wong 102
CIS/CMOS-II Modeling/Fabrication/Characterization 8 CONCLUSIONS AND COMMENTS
8 Conclusions and Comments
Over the course of ten weeks, the EE410 CIS/CMOS-II chip was simulated, fabricated, tested
and characterized. Analytical calculations of eight chip cross-sections were compared with simula-
tions from TSUPREM-IV software. Output from TSUPREM-IV was then used to model transistor
characteristics using MEDICI software. Upon completion of six weeks of fabrication, the fabrica-
tion, process, device and SEM test structures of CIS/CMOS-II were evaluated. Those results, and
comparisons with the calculations and simulations have been discussed in this report.
Analytical calculations based on theoretical models were used to predict device parameters,
such as dopant proles, junction depths and threshold voltages. These predictions were then com-
pared with output from simulations from TSUPREM-IV. In general, the analytical calculations and
simulations outputs were in agreement. While TSUPREM-IV failed in predicting junction depths,
it gave a much more accurate picture of diusion as it could include eects such as concentration-
dependent diusivity, oxidation-enhanced diusivity, dopant segregation and surface reection.
Transient-enhanced diusion was modeled in both the analytical calculations and the numerical
simulations.
MEDICI simulations of pMOS transistors were completed for 100 m and 20 m channel lengths.
Output from the 1-D simulations were used, with estimations made for the second dimension. This
were compared with the electrical measurements, despite the omission of short channel eects and
drain-induced barrier lowering (DIBL).
Electrical characterization was hampered by the failure of several devices. For nMOS, working
devices could only be found on wafer 5, and after some a unexplainable catastrophic failure, fur-
ther testing on these same transistors could not be completed. Threshold voltages for the nMOS
devices were 0.67 V and 0.30 V for the 100 x 100 m and 100 x 1.5 m devices respectively. Short
channel and narrow-width eects were observed. The minimum sized working transistor was the
smallest transistor fabricated on the chip, which was 1.5 x 1.0 m. Failures for the nMOS devices
is attributed to shortingbetween the gate and drain, the gate and source and both the source and
drain to the gate.
Working pMOS devices were found at all possible gate lengths and widths, even down to the
smallest transistors, though not all devices functioned properly. The major problem encountered
with pMOS devices was the lack of control over threshold voltage and DIBL. These eects can
be explained when considering the high diusivity of boron dopant atoms in silicon. Migration
of boron to the device channel or segregation to the growing LTO can cause the large shifts in
threshold voltage and other poor performance characteristics of our pMOS devices.
The process test structures gave some limited insights into the device. Sheet resistances mea-
surements, conducted by both 4-Point Probe and Van der Pauw methods, more most consistent
on wafers 2 and 3, using the 4-Point Probe method. The contact chains showed problems with the
fabrication, most likely due to dierences in poly deposition and etching. Metal step coverage was
also an issue, as it was for continuity testing. Structures, however, were found to be well isolated
Akinwande, Gibby, Jain, Oh, Sun, Wong 103
CIS/CMOS-II Modeling/Fabrication/Characterization 8 CONCLUSIONS AND COMMENTS
from one another. Contact resistance results showed a mixture of Schottky, ohmic and linear be-
havior.
SEM imaging provided more information about the fabrication process. Metal deposition and
subsequent step coverage was the largest issue. Overetching of the polysilicon gate in the Drytek
(vs. P5000 etcher) likely contributed to the failure of the nMOS devices in wafers 1-4.
Despite the fabrication issues, a variety of devices were successfully fabricated and characterized.
Suggestions made for process improvements will hopefully be implemented for future generations
of EE410.
Akinwande, Gibby, Jain, Oh, Sun, Wong 104
CIS/CMOS-II Modeling/Fabrication/Characterization 9 APPENDICES
9 Appendices
9.1 Appendix A: CIS/CMOS-II Process Flow by Cross-Section
Akinwande, Gibby, Jain, Oh, Sun, Wong 105
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Akinwande, Gibby, Jain, Oh, Sun, Wong 106
CIS/CMOS-II Modeling/Fabrication/Characterization 9 APPENDICES
9.2 Appendix B: Analytical Calculations (Handwritten Notes)
Akinwande, Gibby, Jain, Oh, Sun, Wong 107
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.
Akinwande, Gibby, Jain, Oh, Sun, Wong 108
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Akinwande, Gibby, Jain, Oh, Sun, Wong 120
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Akinwande, Gibby, Jain, Oh, Sun, Wong 133
CIS/CMOS-II Modeling/Fabrication/Characterization 9 APPENDICES
9.3 Appendix C: MATLAB Simulation Code
9.3.1 nMOS Channel
% Jinendra Raja Jain (jrjain)
% EE410 CIS/CMOS-II Process: NMOS Channel Region
% Filename: NMOS_Channel.m
% Parameters
x = [-0.888E-4:0.01E-4:2E-4];
% Blanket Phosphorus
P_Q = 1.75E12;
P_Rp = 0.127E-4;
P_DelRp = 0.0461E-4;
P_Dt = 5.9680E-10;
% Deep Boron
DB_Q = 5E12;
DB_Rp = 0.7005E-4;
DB_DelRp = 0.107E-4;
DB_Dt = 5.8879E-10;
% Shallow Boron
SB_Q = 1.4E12;
SB_Rp = 0.4025E-4;
SB_DelRp = 0.0628E-4;
SB_Dt = 5.8879E-10;
% N-Source/Drain Arsenic
As_Q = 5E15;
As_Rp = -0.1853E-4;
As_DelRp = 0.0261E-4;
As_Dt = 1.9271E-11;
% Blanket BF2
BF2_Q = 1E15;
BF2_Rp = -0.1799E-4;
BF2_DelRp = 0.0353E-4;
BF2_Dt = 5.3614E-10;
% Gaussian Profile Evolutions
Substrate_P_Concen = 8E14;
P_Concen = P_Q/sqrt(2*pi*(P_DelRp^2 + 2*P_Dt))*exp(-(x-P_Rp).^2/(2*(P_DelRp^2
+ 2*P_Dt)));
Akinwande, Gibby, Jain, Oh, Sun, Wong 134
CIS/CMOS-II Modeling/Fabrication/Characterization 9 APPENDICES
DB_Concen = DB_Q/sqrt(2*pi*(DB_DelRp^2 + 2*DB_Dt))*exp(-(x-DB_Rp).^2/(2*(DB_DelRp^2
+ 2*DB_Dt)));
SB_Concen = SB_Q/sqrt(2*pi*(SB_DelRp^2 + 2*SB_Dt))*exp(-(x-SB_Rp).^2/(2*(SB_DelRp^2
+ 2*SB_Dt)));
As_Concen = As_Q/sqrt(2*pi*(As_DelRp^2 + 2*As_Dt))*exp(-(x-As_Rp).^2/(2*(As_DelRp^2
+ 2*As_Dt)));
BF2_Concen = BF2_Q/sqrt(2*pi*(BF2_DelRp^2 + 2*BF2_Dt))*exp(-(x-BF2_Rp).^2/
(2*(BF2_DelRp^2 + 2*BF2_Dt)));
% N-Type and P-Type Consolidation
N_Doping = Substrate_P_Concen + P_Concen + As_Concen;
P_Doping = DB_Concen + SB_Concen; + BF2_Concen;
semilogy(x*1E4, N_Doping, x*1E4, P_Doping, --);
vline(-0.8880, r:, LTO);
vline(-0.2266, r:, Poly-Si);
vline(0.2455, r:, SiO_2);
vline(0.2763, r:, Si);
vline(1.7420, r:, 1.7420\mum)
title(NMOS-Channel Impurity Concentration vs. Distance);
xlabel(Distance, \it{x} \rm (\mum));
ylabel(Concentration (cm^{-3}));
h = legend(N-Type Dopant, P-Type Dopant);
9.3.2 nMOS Source
% Jinendra Raja Jain (jrjain)
% EE410 CIS/CMOS-II Process: NMOS Source/Drain Region
% Filename: NMOS_Source.m
% Parameters
x = [-0.6966E-4:0.01E-4:2E-4];
% Blanket Phosphorus
P_Q = 1.75E12;
P_Rp = 0.127E-4;
P_DelRp = 0.0461E-4;
P_Dt = 5.9680E-10;
% Deep Boron
DB_Q = 5E12;
DB_Rp = 0.7005E-4;
DB_DelRp = 0.107E-4;
DB_Dt = 5.8879E-10;
Akinwande, Gibby, Jain, Oh, Sun, Wong 135
CIS/CMOS-II Modeling/Fabrication/Characterization 9 APPENDICES
% Shallow Boron
SB_Q = 1.4E12;
SB_Rp = 0.4025E-4;
SB_DelRp = 0.0628E-4;
SB_Dt = 5.8879E-10;
% N-Source/Drain Arsenic
As_Q = 5E15;
As_Rp = 0.3147E-4;
As_DelRp = 0.0261E-4;
As_Dt = 1.9271E-11;
% Blanket BF2
BF2_Q = 1E15;
BF2_Rp = 0.3201E-4;
BF2_DelRp = 0.0353E-4;
BF2_Dt = 5.3614E-10;
% Gaussian Profile Evolutions
Substrate_P_Concen = 8E14;
P_Concen = P_Q/sqrt(2*pi*(P_DelRp^2 + 2*P_Dt))*exp(-(x-P_Rp).^2/(2*(P_DelRp^2
+ 2*P_Dt)));
DB_Concen = DB_Q/sqrt(2*pi*(DB_DelRp^2 + 2*DB_Dt))*exp(-(x-DB_Rp).^2/(2*(DB_DelRp^2
+ 2*DB_Dt)));
SB_Concen = SB_Q/sqrt(2*pi*(SB_DelRp^2 + 2*SB_Dt))*exp(-(x-SB_Rp).^2/(2*(SB_DelRp^2
+ 2*SB_Dt)));
As_Concen = As_Q/sqrt(2*pi*(As_DelRp^2 + 2*As_Dt))*exp(-(x-As_Rp).^2/(2*(As_DelRp^2
+ 2*As_Dt)));
BF2_Concen = BF2_Q/sqrt(2*pi*(BF2_DelRp^2 + 2*BF2_Dt))*exp(-(x-BF2_Rp).^2/
(2*(BF2_DelRp^2 + 2*BF2_Dt)));
% N-Type and P-Type Consolidation
N_Doping = Substrate_P_Concen + P_Concen + As_Concen;
P_Doping = DB_Concen + SB_Concen; + BF2_Concen;
semilogy(x*1E4, N_Doping, x*1E4, P_Doping, --);
vline(-0.6966, r:, Al);
vline(0.3034, r:, Si);
vline(0.5934, r:, 0.5934\mum)
vline(1.7434, r:, 1.7434\mum)
title(NMOS-Source/Drain Impurity Concentration vs. Distance);
xlabel(Distance, \it{x} \rm (\mum));
ylabel(Concentration (cm^{-3}));
h = legend(N-Type Dopant, P-Type Dopant);
Akinwande, Gibby, Jain, Oh, Sun, Wong 136
CIS/CMOS-II Modeling/Fabrication/Characterization 9 APPENDICES
9.3.3 pMOS Channel
% Jinendra Raja Jain (jrjain)
% EE410 CIS/CMOS-II Process: PMOS Channel Region
% Filename: PMOS_Channel.m
% Parameters
x = [-0.8880E-4:0.01E-4:2E-4];
% Blanket Phosphorus
P_Q = 1.75E12;
P_Rp = 0.127E-4;
P_DelRp = 0.0461E-4;
P_Dt = 3.2273E-10;
% Blanket BF2
BF2_Q = 1E15;
BF2_Rp = -0.1799E-4;
BF2_DelRp = 0.0353E-4;
BF2_Dt = 2.1596E-10;
% Gaussian Profile Evolutions
Substrate_P_Concen = 8E14;
P_Concen = P_Q/sqrt(2*pi*(P_DelRp^2 + 2*P_Dt))*exp(-(x-P_Rp).^2/(2*(P_DelRp^2
+ 2*P_Dt)));
BF2_Concen = BF2_Q/sqrt(2*pi*(BF2_DelRp^2 + 2*BF2_Dt))*exp(-(x-BF2_Rp).^2/
(2*(BF2_DelRp^2 + 2*BF2_Dt)));
% N-Type and P-Type Consolidation
N_Doping = Substrate_P_Concen + P_Concen;
P_Doping = BF2_Concen;
semilogy(x*1E4, N_Doping, x*1E4, P_Doping, --);
vline(-0.8880, r:, LTO);
vline(-0.2266, r:, Poly-Si);
vline(0.2455, r:, SiO_2);
vline(0.2763, r:, Si);
title(PMOS-Channel Impurity Concentration vs. Distance);
xlabel(Distance, \it{x} \rm (\mum));
ylabel(Concentration (cm^{-3}));
h = legend(N-Type Dopant, P-Type Dopant);
9.3.4 pMOS Source
% Jinendra Raja Jain (jrjain)
% EE410 CIS/CMOS-II Process: PMOS Source/Drain Region
Akinwande, Gibby, Jain, Oh, Sun, Wong 137
CIS/CMOS-II Modeling/Fabrication/Characterization 9 APPENDICES
% Filename: PMOS_Source.m
% Parameters
x = [-0.6966E-4:0.01E-4:2E-4];
% Blanket Phosphorus
P_Q = 1.75E12;
P_Rp = 0.127E-4;
P_DelRp = 0.0461E-4;
P_Dt = 3.2273E-10;
% Blanket BF2
BF2_Q = 1E15;
BF2_Rp = 0.3201E-4;
BF2_DelRp = 0.0353E-4;
BF2_Dt = 2.1596E-10;
% Gaussian Profile Evolutions
Substrate_P_Concen = 8E14;
P_Concen = P_Q/sqrt(2*pi*(P_DelRp^2 + 2*P_Dt))*exp(-(x-P_Rp).^2/(2*(P_DelRp^2
+ 2*P_Dt)));
BF2_Concen = BF2_Q/sqrt(2*pi*(BF2_DelRp^2 + 2*BF2_Dt))*exp(-(x-BF2_Rp).^2/
(2*(BF2_DelRp^2 + 2*BF2_Dt)));
% N-Type and P-Type Consolidation
N_Doping = Substrate_P_Concen + P_Concen;
P_Doping = BF2_Concen;
semilogy(x*1E4, N_Doping, x*1E4, P_Doping, --);
vline(-0.6966, r:, Al);
vline(0.3034, r:, Si);
vline(1.2634, r:, 1.2634\mum);
title(PMOS-Source/Drain Impurity Concentration vs. Distance);
xlabel(Distance, \it{x} \rm (\mum));
ylabel(Concentration (cm^{-3}));
h = legend(N-Type Dopant, P-Type Dopant);
9.3.5 nMOS Metal
% Jinendra Raja Jain (jrjain)
% EE410 CIS/CMOS-II Process: NMOS Metal Region
% Filename: NMOS_Metal.m
% Parameters
x = [-1.8775E-4:0.01E-4:2E-4];
Akinwande, Gibby, Jain, Oh, Sun, Wong 138
CIS/CMOS-II Modeling/Fabrication/Characterization 9 APPENDICES
% Blanket Phosphorus
P_Q = 1.75E12;
P_Rp = 0.127E-4;
P_DelRp = 0.0461E-4;
P_Dt = 5.9680E-10;
% Deep Boron
DB_Q = 5E12;
DB_Rp = 0.1624E-4;
DB_DelRp = 0.107E-4;
DB_Dt = 5.8879E-10;
% Shallow Boron
SB_Q = 1.4E12;
SB_Rp = -0.1356E-4;
SB_DelRp = 0.0628E-4;
SB_Dt = 5.8879E-10;
% N-Source/Drain Arsenic
As_Q = 5E15;
As_Rp = -0.1863E-4;
As_DelRp = 0.0261E-4;
As_Dt = 1.9271E-11;
% Blanket BF2
BF2_Q = 1E15;
BF2_Rp = -0.1809E-4;
BF2_DelRp = 0.0353E-4;
BF2_Dt = 5.3614E-10;
% Gaussian Profile Evolutions
Substrate_P_Concen = 8E14;
P_Concen = P_Q/sqrt(2*pi*(P_DelRp^2 + 2*P_Dt))*exp(-(x-P_Rp).^2/(2*(P_DelRp^2
+ 2*P_Dt)));
DB_Concen = DB_Q/sqrt(2*pi*(DB_DelRp^2 + 2*DB_Dt))*exp(-(x-DB_Rp).^2/(2*(DB_DelRp^2
+ 2*DB_Dt)));
SB_Concen = SB_Q/sqrt(2*pi*(SB_DelRp^2 + 2*SB_Dt))*exp(-(x-SB_Rp).^2/(2*(SB_DelRp^2
+ 2*SB_Dt)));
As_Concen = As_Q/sqrt(2*pi*(As_DelRp^2 + 2*As_Dt))*exp(-(x-As_Rp).^2/(2*(As_DelRp^2
+ 2*As_Dt)));
BF2_Concen = BF2_Q/sqrt(2*pi*(BF2_DelRp^2 + 2*BF2_Dt))*exp(-(x-BF2_Rp).^2/
(2*(BF2_DelRp^2 + 2*BF2_Dt)));
Akinwande, Gibby, Jain, Oh, Sun, Wong 139
CIS/CMOS-II Modeling/Fabrication/Characterization 9 APPENDICES
% N-Type and P-Type Consolidation
N_Doping = Substrate_P_Concen + P_Concen + As_Concen;
P_Doping = DB_Concen + SB_Concen; + BF2_Concen;
semilogy(x*1E4, N_Doping, x*1E4, P_Doping, --);
vline(-1.8775, r:, Al);
vline(-0.8775, r:, SiO_2);
vline(0.2813, r:, Si);
vline(1.1725, r:, 1.1725\mum)
title(NMOS-Metal Impurity Concentration vs. Distance);
xlabel(Distance, \it{x} \rm (\mum));
ylabel(Concentration (cm^{-3}));
h = legend(N-Type Dopant, P-Type Dopant);
9.3.6 nMOS Poly
% Jinendra Raja Jain (jrjain)
% EE410 CIS/CMOS-II Process: NMOS Polysilicon Region
% Filename: NMOS_Poly.m
% Parameters
x = [-1.3889E-4:0.01E-4:2E-4];
% Blanket Phosphorus
P_Q = 1.75E12;
P_Rp = 0.127E-4;
P_DelRp = 0.0461E-4;
P_Dt = 5.9680E-10;
% Deep Boron
DB_Q = 5E12;
DB_Rp = 0.1624E-4;
DB_DelRp = 0.107E-4;
DB_Dt = 5.8879E-10;
% Shallow Boron
SB_Q = 1.4E12;
SB_Rp = -0.1356E-4;
SB_DelRp = 0.0628E-4;
SB_Dt = 5.8879E-10;
% N-Source/Drain Arsenic
As_Q = 5E15;
As_Rp = -0.6863E-4;
As_DelRp = 0.0261E-4;
Akinwande, Gibby, Jain, Oh, Sun, Wong 140
CIS/CMOS-II Modeling/Fabrication/Characterization 9 APPENDICES
As_Dt = 1.9271E-11;
% Blanket BF2
BF2_Q = 1E15;
BF2_Rp = -0.6809E-4;
BF2_DelRp = 0.0353E-4;
BF2_Dt = 5.3614E-10;
% Gaussian Profile Evolutions
Substrate_P_Concen = 8E14;
P_Concen = P_Q/sqrt(2*pi*(P_DelRp^2 + 2*P_Dt))*exp(-(x-P_Rp).^2/(2*(P_DelRp^2
+ 2*P_Dt)));
DB_Concen = DB_Q/sqrt(2*pi*(DB_DelRp^2 + 2*DB_Dt))*exp(-(x-DB_Rp).^2/(2*(DB_DelRp^2
+ 2*DB_Dt)));
SB_Concen = SB_Q/sqrt(2*pi*(SB_DelRp^2 + 2*SB_Dt))*exp(-(x-SB_Rp).^2/(2*(SB_DelRp^2
+ 2*SB_Dt)));
As_Concen = As_Q/sqrt(2*pi*(As_DelRp^2 + 2*As_Dt))*exp(-(x-As_Rp).^2/(2*(As_DelRp^2
+ 2*As_Dt)));
BF2_Concen = BF2_Q/sqrt(2*pi*(BF2_DelRp^2 + 2*BF2_Dt))*exp(-(x-BF2_Rp).^2/
(2*(BF2_DelRp^2 + 2*BF2_Dt)));
% N-Type and P-Type Consolidation
N_Doping = Substrate_P_Concen + P_Concen + As_Concen;
P_Doping = DB_Concen + SB_Concen; + BF2_Concen;
semilogy(x*1E4, N_Doping, x*1E4, P_Doping, --);
vline(-1.3889, r:, LTO);
vline(-0.7276, r:, Poly-Si);
vline(-0.2555, r:, SiO_2);
vline(0.2630, r:, Si);
vline(1.1811, r:, 1.1811\mum)
title(NMOS-Poly Impurity Concentration vs. Distance);
xlabel(Distance, \it{x} \rm (\mum));
ylabel(Concentration (cm^{-3}));
h = legend(N-Type Dopant, P-Type Dopant);
9.3.7 pMOS Metal
% Jinendra Raja Jain (jrjain)
% EE410 CIS/CMOS-II Process: PMOS Metal Region
% Filename: PMOS_Metal.m
% Parameters
x = [-1.8775E-4:0.01E-4:2E-4];
Akinwande, Gibby, Jain, Oh, Sun, Wong 141
CIS/CMOS-II Modeling/Fabrication/Characterization 9 APPENDICES
% Blanket Phosphorus
P_Q = 1.75E12;
P_Rp = 0.127E-4;
P_DelRp = 0.0461E-4;
P_Dt = 3.2273E-10;
% Blanket BF2
BF2_Q = 1E15;
BF2_Rp = -0.1809E-4;
BF2_DelRp = 0.0353E-4;
BF2_Dt = 2.1596E-10;
% Gaussian Profile Evolutions
Substrate_P_Concen = 8E14;
P_Concen = P_Q/sqrt(2*pi*(P_DelRp^2 + 2*P_Dt))*exp(-(x-P_Rp).^2/(2*(P_DelRp^2
+ 2*P_Dt)));
BF2_Concen = BF2_Q/sqrt(2*pi*(BF2_DelRp^2 + 2*BF2_Dt))*exp(-(x-BF2_Rp).^2/
(2*(BF2_DelRp^2 + 2*BF2_Dt)));
% N-Type and P-Type Consolidation
N_Doping = Substrate_P_Concen + P_Concen;
P_Doping = BF2_Concen;
semilogy(x*1E4, N_Doping, x*1E4, P_Doping, --);
vline(-1.8775, r:, Al);
vline(-0.8775, r:, SiO_2);
vline(0.2813, r:, Si);
title(PMOS-Metal Impurity Concentration vs. Distance);
xlabel(Distance, \it{x} \rm (\mum));
ylabel(Concentration (cm^{-3}));
h = legend(N-Type Dopant, P-Type Dopant);
9.3.8 pMOS Poly
% Jinendra Raja Jain (jrjain)
% EE410 CIS/CMOS-II Process: PMOS Poly Region
% Filename: PMOS_Poly.m
% Parameters
x = [-1.3889E-4:0.01E-4:2E-4];
% Blanket Phosphorus
P_Q = 1.75E12;
P_Rp = 0.127E-4;
P_DelRp = 0.0461E-4;
Akinwande, Gibby, Jain, Oh, Sun, Wong 142
CIS/CMOS-II Modeling/Fabrication/Characterization 9 APPENDICES
P_Dt = 3.2273E-10;
% Blanket BF2
BF2_Q = 1E15;
BF2_Rp = -0.6809E-4;
BF2_DelRp = 0.0353E-4;
BF2_Dt = 2.1596E-10;
% Gaussian Profile Evolutions
Substrate_P_Concen = 8E14;
P_Concen = P_Q/sqrt(2*pi*(P_DelRp^2 + 2*P_Dt))*exp(-(x-P_Rp).^2/(2*(P_DelRp^2
+ 2*P_Dt)));
BF2_Concen = BF2_Q/sqrt(2*pi*(BF2_DelRp^2 + 2*BF2_Dt))*exp(-(x-BF2_Rp).^2/
(2*(BF2_DelRp^2 + 2*BF2_Dt)));
% N-Type and P-Type Consolidation
N_Doping = Substrate_P_Concen + P_Concen;
P_Doping = BF2_Concen;
semilogy(x*1E4, N_Doping, x*1E4, P_Doping, --);
vline(-1.3889, r:, LTO);
vline(-0.7276, r:, Poly-Si);
vline(-0.2555, r:, SiO_2);
vline(0.2630, r:, Si);
title(PMOS-Poly Impurity Concentration vs. Distance);
xlabel(Distance, \it{x} \rm (\mum));
ylabel(Concentration (cm^{-3}));
h = legend(N-Type Dopant, P-Type Dopant);
Akinwande, Gibby, Jain, Oh, Sun, Wong 143
CIS/CMOS-II Modeling/Fabrication/Characterization 9 APPENDICES
9.4 Appendix D: TSUPREM-IV Simulation Code
9.4.1 Substrate
$ Jinendra Raja Jain (jrjain)
$ EE410 CIS/CMOS-II Process: Starting Substrate with Field Oxidation
$ Filename: Substrate.inp
$ Dopant Diffusion Model
METHOD PD.FULL
$ Wafer Initialization
INITIALIZE <100> Material=Silicon Phosphorus=8e14 Width=1.5 Dx=.005
$ Wafer Scribing
$ Standard Photoresist Strip
$ Standard Pre-Diffusion Clean
$ Phosphorus Blanket Substrate Implant
IMPLANT Phosphorus Dose=1.75e12 Energy=100 Tilt=7 Gaussian
$ Standard Pre-Diffusion Clean
$ Field Oxidation (Target Thickness = 500nm)
DIFFUSION Time=35 Temperature=800 T.Final=1000 Argon
DIFFUSION Time=10 Temperature=1000 DryO2
DIFFUSION Time=100 Temperature=1000 Steam
DIFFUSION Time=10 Temperature=1000 DryO2
DIFFUSION Time=35 Temperature=1000 T.Final=800 Argon
$ Ouput Results
OPTION Device=postscript Plot.Out="PS_Files/Substrate.ps"
PRINT Layers
SELECT Z=Log10(Active(Phosphorus))
PLOT.1D Bottom=14 Top=21 Right=2
SAVEFILE Out.File=Struct_Files/Substrate.str
9.4.2 Active
$ Jinendra Raja Jain (jrjain)
$ EE410 CIS/CMOS-II Process: Active Region
$ Filename: Active.inp
$ Dopant Diffusion Model
METHOD PD.FULL
Akinwande, Gibby, Jain, Oh, Sun, Wong 144
CIS/CMOS-II Modeling/Fabrication/Characterization 9 APPENDICES
$ Wafer Initialization
INITIALIZE In.File=Struct_Files/Substrate.str
$ Photolithography #1 - Active Area
$ SiO2 Etch in 6:1 BOE (Buffered (HF) Oxide Etch)
ETCH Oxide All
$ Standard Photoresist Strip
$ Standard Pre-Diffusion Clean
$ Sacrificial Oxidation (Target Thickness = 40nm)
DIFFUSION Time=20 Temperature=800 T.Final=900 Argon
DIFFUSION Time=5 Temperature=900 DryO2
DIFFUSION Time=12 Temperature=900 Steam
DIFFUSION Time=5 Temperature=900 DryO2
DIFFUSION Time=15 Temperature=900 T.Final=800 Argon
$ Output Results
PRINT Layers
SAVEFILE Out.File=Struct_Files/Active.str
9.4.3 Field
$ Jinendra Raja Jain (jrjain)
$ EE410 CIS/CMOS-II Process: Field Region
$ Filename: Field.inp
$ Dopant Diffusion Model
METHOD PD.FULL
$ Wafer Initialization
INITIALIZE In.File=Struct_Files/Substrate.str
$ Photolithography #1 - Active Area
$ Standard Photoresist Strip
$ Standard Pre-Diffusion Clean
$ Sacrificial Oxidation (Target Thickness = 40nm)
DIFFUSION Time=20 Temperature=800 T.Final=900 Argon
DIFFUSION Time=5 Temperature=900 DryO2
DIFFUSION Time=12 Temperature=900 Steam
DIFFUSION Time=5 Temperature=900 DryO2
DIFFUSION Time=15 Temperature=900 T.Final=800 Argon
Akinwande, Gibby, Jain, Oh, Sun, Wong 145
CIS/CMOS-II Modeling/Fabrication/Characterization 9 APPENDICES
$ Output Results
PRINT Layers
SAVEFILE Out.File=Struct_Files/Field.str
9.4.4 nMOS Active
$ Jinendra Raja Jain (jrjain)
$ EE410 CIS/CMOS-II Process: NMOS Active Region
$ Filename: NMOS_Active.inp
$ Dopant Diffusion Model
METHOD PD.FULL
$ Wafer Initialization
INITIALIZE In.File=Struct_Files/Active.str
$ Photolithography #2 - P-Well
$ P-Well Double Implant
IMPLANT Boron Dose=5e12 Energy=180 Tilt=7 Gaussian
IMPLANT Boron Dose=1.4e12 Energy=50 Tilt=7 Gaussian
$ Standard Photoresist Strip
$ Standard Pre-Diffusion Clean with 50:1 HF Dip
$ P-Well Drive-In
DIFFUSION Time=30 Temperature=800 T.Final=1000 Argon
DIFFUSION Time=60 Temperature=1000 Argon
DIFFUSION Time=20 Temperature=1000 T.Final=800 Argon
$ Standard Pre-Diffusion Clean
$ Sacrificial Oxide Strip (Etch 60nm (60nm includes 50% overetch))
Etch Oxide Old.Dry Thickness=.06
$ Gate Oxidation (Target Thickness = 40nm)
DIFFUSION Time=20 Temperature=800 T.Final=900 Argon
DIFFUSION Time=5 Temperature=900 DryO2
DIFFUSION Time=12 Temperature=900 Steam
DIFFUSION Time=5 Temperature=900 DryO2
DIFFUSION Time=15 Temperature=900 T.Final=800 Argon
$ Polysilicon Deposition (Target Thickness = 500nm)
DEPOSITION Polysilicon Thickness=.5
Akinwande, Gibby, Jain, Oh, Sun, Wong 146
CIS/CMOS-II Modeling/Fabrication/Characterization 9 APPENDICES
$ Photolithography #3 - Polysilicon
$ Output Results
PRINT Layers
SAVEFILE Out.File=Struct_Files/NMOS_Active.str
9.4.5 pMOS Active
$ Jinendra Raja Jain (jrjain)
$ EE410 CIS/CMOS-II Process: PMOS Active Region
$ Filename: P_Active.inp
$ Dopant Diffusion Model
METHOD PD.Full
$ Wafer Initialization
INITIALIZE In.File=Struct_Files/Active.str
$ Photolithography #2 - P-Well
$ Standard Photoresist Strip
$ Standard Pre-Diffusion Clean with 50:1 HF Dip
$ P-Well Drive-In
DIFFUSION Time=30 Temperature=800 T.Final=1000 Argon
DIFFUSION Time=60 Temperature=1000 Argon
DIFFUSION Time=20 Temperature=1000 T.Final=800 Argon
$ Standard Pre-Diffusion Clean
$ Sacrificial Oxide Strip (Etch 60nm (60nm includes 50% overetch))
Etch Oxide Old.Dry Thickness=.06
$ Gate Oxidation (Target Thickness = 40nm)
DIFFUSION Time=20 Temperature=800 T.Final=900 Argon
DIFFUSION Time=5 Temperature=900 DryO2
DIFFUSION Time=12 Temperature=900 Steam
DIFFUSION Time=5 Temperature=900 DryO2
DIFFUSION Time=15 Temperature=900 T.Final=800 Argon
$ Polysilicon Deposition (Target Thickness = 500nm)
DEPOSITION Polysilicon Thickness=.5
$ Photolithography #3 - Polysilicon
$ Output Results
Akinwande, Gibby, Jain, Oh, Sun, Wong 147
CIS/CMOS-II Modeling/Fabrication/Characterization 9 APPENDICES
PRINT Layers
SAVEFILE Out.File=Struct_Files/PMOS_Active.str
9.4.6 nMOS Field
$ Jinendra Raja Jain (jrjain)
$ EE410 CIS/CMOS-II Process: NMOS Field Region
$ Filename: NMOS_Field.inp
$ Dopant Diffusion Model
METHOD PD.FULL
$ Wafer Initialization
INITIALIZE In.File=Struct_Files/Field.str
$ Photolithography #2 - P-Well
$ P-Well Double Implant
IMPLANT Boron Dose=5e12 Energy=180 Tilt=7 Gaussian
IMPLANT Boron Dose=1.4e12 Energy=50 Tilt=7 Gaussian
$ Standard Photoresist Strip
$ Standard Pre-Diffusion Clean with 50:1 HF Dip
$ P-Well Drive-In
DIFFUSION Time=30 Temperature=800 T.Final=1000 Argon
DIFFUSION Time=60 Temperature=1000 Argon
DIFFUSION Time=20 Temperature=1000 T.Final=800 Argon
$ Standard Pre-Diffusion Clean
$ Sacrificial Oxide Strip (Etch 60nm (60nm includes 50% overetch))
Etch Oxide Old.Dry Thickness=.06
$ Gate Oxidation (Target Thickness = 40nm)
DIFFUSION Time=20 Temperature=800 T.Final=900 Argon
DIFFUSION Time=5 Temperature=900 DryO2
DIFFUSION Time=12 Temperature=900 Steam
DIFFUSION Time=5 Temperature=900 DryO2
DIFFUSION Time=15 Temperature=900 T.Final=800 Argon
$ Polysilicon Deposition (Target Thickness = 500nm)
DEPOSITION Polysilicon Thickness=.5
$ Photolithography #3 - Polysilicon
Akinwande, Gibby, Jain, Oh, Sun, Wong 148
CIS/CMOS-II Modeling/Fabrication/Characterization 9 APPENDICES
$ Output Results
PRINT Layers
SAVEFILE Out.File=Struct_Files/NMOS_Field.str
9.4.7 pMOS Field
$ Jinendra Raja Jain (jrjain)
$ EE410 CIS/CMOS-II Process: PMOS Field Region
$ Filename: P_Field.inp
$ Dopant Diffusion Model
METHOD PD.FULL
$ Wafer Initialization
INITIALIZE In.File=Struct_Files/Field.str
$ Photolithography #2 - P-Well
$ Standard Photoresist Strip
$ Standard Pre-Diffusion Clean with 50:1 HF Dip
$ P-Well Drive-In
DIFFUSION Time=30 Temperature=800 T.Final=1000 Argon
DIFFUSION Time=60 Temperature=1000 Argon
DIFFUSION Time=20 Temperature=1000 T.Final=800 Argon
$ Standard Pre-Diffusion Clean
$ Sacrificial Oxide Strip (Etch 60nm (60nm includes 50% overetch))
Etch Oxide Old.Dry Thickness=.06
$ Gate Oxidation (Target Thickness = 40nm)
DIFFUSION Time=20 Temperature=800 T.Final=900 Argon
DIFFUSION Time=5 Temperature=900 DryO2
DIFFUSION Time=12 Temperature=900 Steam
DIFFUSION Time=5 Temperature=900 DryO2
DIFFUSION Time=15 Temperature=900 T.Final=800 Argon
$ Polysilicon Deposition (Target Thickness = 500nm)
DEPOSITION Polysilicon Thickness=.5
$ Photolithography #3 - Polysilicon
$ Output Results
PRINT Layers
Akinwande, Gibby, Jain, Oh, Sun, Wong 149
CIS/CMOS-II Modeling/Fabrication/Characterization 9 APPENDICES
SAVEFILE Out.File=Struct_Files/PMOS_Field.str
9.4.8 nMOS Channel
$ Jinendra Raja Jain (jrjain)
$ EE410 CIS/CMOS-II Process: NMOS Channel Region
$ Filename: NMOS_Channel.inp
$ Dopant Diffusion Model
METHOD PD.FULL
$ Wafer Initialization
INITIALIZE In.File=Struct_Files/NMOS_Active.str
$ Standard Photoresist Strip
$ Photolithography #4 - N-Select
$ N-Source/Drain Implant
IMPLANT Arsenic Dose=5e15 Energy=100 Tilt=7 Gaussian
$ Matrix Photoresist Strip
$ Standard Photoresist Strip
$ Standard Pre-Diffusion Clean
$ Boron Blanket Implant
IMPLANT BF2 Dose=1e15 Energy=80 Tilt=7 Gaussian
$ Standard Pre-Diffusion Clean
$ LTO Deposition (Undoped Target Thickness = 50nm, Phosphorus-Doped (8%)
$ Target Thickness = 550nm)
DEPOSITION Oxide Thickness=.6
$ Standard Pre-Diffusion Clean
$ LTO Densification
DIFFUSION Time=30 Temperature=800 T.Final=950 Argon
DIFFUSION Time=5 Temperature=950 DryO2
DIFFUSION Time=30 Temperature=950 Steam
DIFFUSION Time=5 Temperature=950 DryO2
DIFFUSION Time=20 Temperature=950 T.Final=800 Argon
$ Photolithography #5 - Contact Holes
$ Ash Photoresist
$ Standard Photoresist Strip
Akinwande, Gibby, Jain, Oh, Sun, Wong 150
CIS/CMOS-II Modeling/Fabrication/Characterization 9 APPENDICES
$ Standard Pre-Diffusion Clean
$ Aluminum/Silicon Alloy Deposition (Target Thickness = 10000A)
DEPOSITION Aluminum THICKNESS=1
$ Photolithography #6 - Metal
$ Dry Aluminum Etch
ETCH Aluminum All
$ Silicon Freckle Etch
$ PRX-127 Photoresist Strip
$ PRS-1000 Metal Cleanu
$ Anneal and Alloy (FGA Anneal with 10% H2 in N2)
$ Output Results
OPTION Device=postscript Plot.Out="PS_Files/NMOS_Channel.ps"
SELECT Z=Doping
PRINT Layers
SELECT Z=Log10(Boron) Title="NMOS Channel Impurity Concentration"
+ Label = "Log(Concentration) (cm-3)"
PLOT.1D Line.Type=1 Color=1 Symbol=1 Left=-2 Right=2 Top=21
SELECT Z=Log10(Phosphorus)
PLOT.1D !Axes !Clear Line.Type=2 Color=2 Symbol=2
SELECT Z=Log10(Arsenic)
PLOT.1D !Axes !Clear Line.Type=3 Color=3 Symbol=3
LABEL X=1 Y=20 LABEL="Boron" Color=1 Symbol=1
LABEL X=1 Y=19.5 LABEL="Phosphorus" Color=2 Symbol=2
LABEL X=1 Y=19 LABEL="Arsenic" Color=3 Symbol=3
ELECTRICAL Resistance
ELECTRICAL Threshold NMOS V="-20 20 0.01" Qss=5e10
9.4.9 nMOS Source
$ Jinendra Raja Jain (jrjain)
$ EE410 CIS/CMOS-II Process: NMOS Source/Drain Region
$ Filename: NMOS_Source.inp
$ Dopant Diffusion Model
METHOD PD.FULL
$ Wafer Initialization
INITIALIZE In.File=Struct_Files/NMOS_Active.str
$ Polysilicon Plasma Etch
Akinwande, Gibby, Jain, Oh, Sun, Wong 151
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Etch Polysilicon All
$ Standard Photoresist Strip
$ Photolithography #4 - N-Select
$ N-Source/Drain Implant
IMPLANT Arsenic Dose=5e15 Energy=100 Tilt=7 Gaussian
$ Matrix Photoresist Strip
$ Standard Photoresist Strip
$ Standard Pre-Diffusion Clean
$ Boron Blanket Implant
IMPLANT BF2 Dose=1e15 Energy=80 Tilt=7 Gaussian
$ Standard Pre-Diffusion Clean
$ LTO Deposition (Undoped Target Thickness = 50nm, Phosphorus-Doped (8%)
$ Target Thickness = 550nm)
DEPOSITION Oxide Thickness=.6
$ Standard Pre-Diffusion Clean
$ LTO Densification
DIFFUSION Time=30 Temperature=800 T.Final=950 Argon
DIFFUSION Time=5 Temperature=950 DryO2
DIFFUSION Time=30 Temperature=950 Steam
DIFFUSION Time=5 Temperature=950 DryO2
DIFFUSION Time=20 Temperature=950 T.Final=800 Argon
$ Photolithography #5 - Contact Holes
$ SiO2 RIE in AMT 8100
ETCH Oxide All
$ Silicon Etch (Contact Holes)
$ Polymer Removal
$ Ash Photoresist
$ Standard Photoresist Strip
$ Standard Pre-Diffusion Clean
$ Aluminum/Silicon Alloy Deposition (Target Thickness = 10000A)
DEPOSITION Aluminum THICKNESS=1
Akinwande, Gibby, Jain, Oh, Sun, Wong 152
CIS/CMOS-II Modeling/Fabrication/Characterization 9 APPENDICES
$ Photolithography #6 - Metal
$ PRX-127 Photoresist Strip
$ PRS-1000 Metal Clean
$ Anneal and Alloy (FGA Anneal with 10% H2 in N2)
$ Output Results
OPTION Device=postscript Plot.Out="PS_Files/NMOS_Source.ps"
SELECT Z=Doping
PRINT Layers
SELECT Z=Log10(Boron) Title="NMOS Source/Drain Impurity Concentration"
+ Label = "Log(Concentration) (cm-3)"
PLOT.1D Line.Type=1 Color=1 Symbol=1 Left=-2 Right=2 Top=21
SELECT Z=Log10(Phosphorus)
PLOT.1D !Axes !Clear Line.Type=2 Color=2 Symbol=2
SELECT Z=Log10(Arsenic)
PLOT.1D !Axes !Clear Line.Type=3 Color=3 Symbol=3
LABEL X=1 Y=20 LABEL="Boron" Color=1 Symbol=1
LABEL X=1 Y=19.5 LABEL="Phosphorus" Color=2 Symbol=2
LABEL X=1 Y=19 LABEL="Arsenic" Color=3 Symbol=3
ELECTRICAL Resistance
9.4.10 pMOS Channel
$ Jinendra Raja Jain (jrjain)
$ EE410 CIS/CMOS-II Process: PMOS Channel Region
$ Filename: PMOS_Channel.inp
$ Dopant Diffusion Model
METHOD PD.FULL
$ Wafer Initialization
INITIALIZE In.File=Struct_Files/PMOS_Active.str
$ Standard Photoresist Strip
$ Photolithography #4 - N-Select
$ Matrix Photoresist Strip
$ Standard Photoresist Strip
$ Standard Pre-Diffusion Clean
$ Boron Blanket Implant
IMPLANT BF2 Dose=1e15 Energy=80 Tilt=7 Gaussian
$ Standard Pre-Diffusion Clean
$ LTO Deposition (Undoped Target Thickness = 50nm, Phosphorus-Doped (8%)
Akinwande, Gibby, Jain, Oh, Sun, Wong 153
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$ Target Thickness = 550nm)
DEPOSITION Oxide Thickness=.6
$ Standard Pre-Diffusion Clean
$ LTO Densification
DIFFUSION Time=30 Temperature=800 T.Final=950 Argon
DIFFUSION Time=5 Temperature=950 DryO2
DIFFUSION Time=30 Temperature=950 Steam
DIFFUSION Time=5 Temperature=950 DryO2
DIFFUSION Time=20 Temperature=950 T.Final=800 Argon
$ Photolithography #5 - Contact Holes
$ Ash Photoresist
$ Standard Photoresist Strip
$ Standard Pre-Diffusion Clean
$ Aluminum/Silicon Alloy Deposition (Target Thickness = 10000A)
DEPOSITION Aluminum THICKNESS=1
$ Photolithography #6 - Metal
$ Dry Aluminum Etch
ETCH Aluminum All
$ Silicon Freckle Etch
$ PRX-127 Photoresist Strip
$ PRS-1000 Metal Clean
$ Anneal and Alloy (FGA Anneal with 10% H2 in N2)
$ Output Results
OPTION Device=postscript Plot.Out="PS_Files/PMOS_Channel.ps"
SELECT Z=Doping
PRINT Layers
SELECT Z=Log10(Boron) Title="PMOS Channel Impurity Concentration"
+ Label = "Log(Concentration) (cm-3)"
PLOT.1D Line.Type=1 Color=1 Symbol=1 Left=-2 Right=2 Top=21
SELECT Z=Log10(Phosphorus)
PLOT.1D !Axes !Clear Line.Type=2 Color=2 Symbol=2
SELECT Z=Log10(Arsenic)
PLOT.1D !Axes !Clear Line.Type=3 Color=3 Symbol=3
LABEL X=1 Y=20 LABEL="Boron" Color=1 Symbol=1
LABEL X=1 Y=19.5 LABEL="Phosphorus" Color=2 Symbol=2
LABEL X=1 Y=19 LABEL="Arsenic" Color=3 Symbol=3
Akinwande, Gibby, Jain, Oh, Sun, Wong 154
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ELECTRICAL Resistance
ELECTRICAL Threshold PMOS V="-20 20 0.01" Qss=5e10
9.4.11 pMOS Source
$ Jinendra Raja Jain (jrjain)
$ EE410 CIS/CMOS-II Process: PMOS Source/Drain Region
$ Filename: PMOS_Source.inp
$ Dopant Diffusion Model
METHOD PD.FULL
$ Wafer Initialization
INITIALIZE In.File=Struct_Files/PMOS_Active.str
$ Polysilicon Plasma Etch
Etch Polysilicon All
$ Standard Photoresist Strip
$ Photolithography #4 - N-Select
$ Matrix Photoresist Strip
$ Standard Photoresist Strip
$ Standard Pre-Diffusion Clean
$ Boron Blanket Implant
IMPLANT BF2 Dose=1e15 Energy=80 Tilt=7 Gaussian
$ Standard Pre-Diffusion Clean
$ LTO Deposition (Undoped Target Thickness = 50nm, Phosphorus-Doped (8%)
$ Target Thickness = 550nm)
DEPOSITION Oxide Thickness=.6
$ Standard Pre-Diffusion Clean
$ LTO Densification
DIFFUSION Time=30 Temperature=800 T.Final=950 Argon
DIFFUSION Time=5 Temperature=950 DryO2
DIFFUSION Time=30 Temperature=950 Steam
DIFFUSION Time=5 Temperature=950 DryO2
DIFFUSION Time=20 Temperature=950 T.Final=800 Argon
$ Photolithography #5 - Contact Holes
$ SiO2 RIE in AMT 8100
Akinwande, Gibby, Jain, Oh, Sun, Wong 155
CIS/CMOS-II Modeling/Fabrication/Characterization 9 APPENDICES
ETCH Oxide All
$ Silicon Etch (Contact Holes)
$ Polymer Removal
$ Ash Photoresist
$ Standard Photoresist Strip
$ Standard Pre-Diffusion Clean
$ Aluminum/Silicon Alloy Deposition (Target Thickness = 10000A)
DEPOSITION Aluminum THICKNESS=1
$ Photolithography #6 - Metal
$ PRX-127 Photoresist Strip
$ PRS-1000 Metal Clean
$ Anneal and Alloy (FGA Anneal with 10% H2 in N2)
$ Output Results
OPTION Device=postscript Plot.Out="PS_Files/PMOS_Source.ps"
SELECT Z=Doping
PRINT Layers
SELECT Z=Log10(Boron) Title="PMOS Source/Drain Impurity Concentration"
+ Label = "Log(Concentration) (cm-3)"
PLOT.1D Line.Type=1 Color=1 Symbol=1 Left=-2 Right=2 Top=21
SELECT Z=Log10(Phosphorus)
PLOT.1D !Axes !Clear Line.Type=2 Color=2 Symbol=2
SELECT Z=Log10(Arsenic)
PLOT.1D !Axes !Clear Line.Type=3 Color=3 Symbol=3
LABEL X=1 Y=20 LABEL="Boron" Color=1 Symbol=1
LABEL X=1 Y=19.5 LABEL="Phosphorus" Color=2 Symbol=2
LABEL X=1 Y=19 LABEL="Arsenic" Color=3 Symbol=3
ELECTRICAL Resistance
9.4.12 nMOS Metal
$ Jinendra Raja Jain (jrjain)
$ EE410 CIS/CMOS-II Process: NMOS Metal Region
$ Filename: NMOS_Metal.inp
$ Dopant Diffusion Model
METHOD PD.FULL
$ Wafer Initialization
INITIALIZE In.File=Struct_Files/NMOS_Field.str
$ Polysilicon Plasma Etch
Akinwande, Gibby, Jain, Oh, Sun, Wong 156
CIS/CMOS-II Modeling/Fabrication/Characterization 9 APPENDICES
Etch Polysilicon All
$ Standard Photoresist Strip
$ Photolithography #4 - N-Select
$ N-Source/Drain Implant
IMPLANT Arsenic Dose=5e15 Energy=100 Tilt=7 Gaussian
$ Matrix Photoresist Strip
$ Standard Photoresist Strip
$ Standard Pre-Diffusion Clean
$ Boron Blanket Implant
IMPLANT BF2 Dose=1e15 Energy=80 Tilt=7 Gaussian
$ Standard Pre-Diffusion Clean
$ LTO Deposition (Undoped Target Thickness = 50nm, Phosphorus-Doped (8%)
$ Target Thickness = 550nm)
DEPOSITION Oxide Thickness=.6
$ Standard Pre-Diffusion Clean
$ LTO Densification
DIFFUSION Time=30 Temperature=800 T.Final=950 Argon
DIFFUSION Time=5 Temperature=950 DryO2
DIFFUSION Time=30 Temperature=950 Steam
DIFFUSION Time=5 Temperature=950 DryO2
DIFFUSION Time=20 Temperature=950 T.Final=800 Argon
$ Photolithography #5 - Contact Holes
$ Ash Photoresist
$ Standard Photoresist Strip
$ Standard Pre-Diffusion Clean
$ Aluminum/Silicon Alloy Deposition (Target Thickness = 10000A)
DEPOSITION Aluminum THICKNESS=1
$ Photolithography #6 - Metal
$ PRX-127 Photoresist Strip
$ PRS-1000 Metal Clean
$ Anneal and Alloy (FGA Anneal with 10% H2 in N2)
$ Output Results
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OPTION Device=postscript Plot.Out="PS_Files/NMOS_Metal.ps"
SELECT Z=Doping
PRINT Layers
SELECT Z=Log10(Boron) Title="NMOS Metal Impurity Concentration"
+ Label = "Log(Concentration) (cm-3)"
PLOT.1D Line.Type=1 Color=1 Symbol=1 Left=-2 Right=2 Top=21
SELECT Z=Log10(Phosphorus)
PLOT.1D !Axes !Clear Line.Type=2 Color=2 Symbol=2
SELECT Z=Log10(Arsenic)
PLOT.1D !Axes !Clear Line.Type=3 Color=3 Symbol=3
LABEL X=1 Y=20 LABEL="Boron" Color=1 Symbol=1
LABEL X=1 Y=19.5 LABEL="Phosphorus" Color=2 Symbol=2
LABEL X=1 Y=19 LABEL="Arsenic" Color=3 Symbol=3
ELECTRICAL Resistance
ELECTRICAL Threshold NMOS V="-30 30 0.01" Qss=5e10
9.4.13 nMOS Poly
$ Jinendra Raja Jain (jrjain)
$ EE410 CIS/CMOS-II Process: NMOS Poly Region
$ Filename: NMOS_Poly.inp
$ Dopant Diffusion Model
METHOD PD.FULL
$ Wafer Initialization
INITIALIZE In.File=Struct_Files/NMOS_Field.str
$ Standard Photoresist Strip
$ Photolithography #4 - N-Select
$ N-Source/Drain Implant
IMPLANT Arsenic Dose=5e15 Energy=100 Tilt=7 Gaussian
$ Matrix Photoresist Strip
$ Standard Photoresist Strip
$ Standard Pre-Diffusion Clean
$ Boron Blanket Implant
IMPLANT BF2 Dose=1e15 Energy=80 Tilt=7 Gaussian
$ Standard Pre-Diffusion Clean
$ LTO Deposition (Undoped Target Thickness = 50nm, Phosphorus-Doped (8%)
$ Target Thickness = 550nm)
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DEPOSITION Oxide Thickness=.6
$ Standard Pre-Diffusion Clean
$ LTO Densification
DIFFUSION Time=30 Temperature=800 T.Final=950 Argon
DIFFUSION Time=5 Temperature=950 DryO2
DIFFUSION Time=30 Temperature=950 Steam
DIFFUSION Time=5 Temperature=950 DryO2
DIFFUSION Time=20 Temperature=950 T.Final=800 Argon
$ Photolithography #5 - Contact Holes
$ Ash Photoresist
$ Standard Photoresist Strip
$ Standard Pre-Diffusion Clean
$ Aluminum/Silicon Alloy Deposition (Target Thickness = 10000A)
DEPOSITION Aluminum THICKNESS=1
$ Photolithography #6 - Metal
$ Dry Aluminum Etch
ETCH Aluminum All
$ Silicon Freckle Etch
$ PRX-127 Photoresist Strip
$ PRS-1000 Metal Clean
$ Anneal and Alloy (FGA Anneal with 10% H2 in N2)
$ Output Results
OPTION Device=postscript Plot.Out="PS_Files/NMOS_Poly.ps"
SELECT Z=Doping
PRINT Layers
SELECT Z=Log10(Boron) Title="NMOS Poly Impurity Concentration"
+ Label = "Log(Concentration) (cm-3)"
PLOT.1D Line.Type=1 Color=1 Symbol=1 Left=-2 Right=2 Top=21
SELECT Z=Log10(Phosphorus)
PLOT.1D !Axes !Clear Line.Type=2 Color=2 Symbol=2
SELECT Z=Log10(Arsenic)
PLOT.1D !Axes !Clear Line.Type=3 Color=3 Symbol=3
LABEL X=1 Y=20 LABEL="Boron" Color=1 Symbol=1
LABEL X=1 Y=19.5 LABEL="Phosphorus" Color=2 Symbol=2
LABEL X=1 Y=19 LABEL="Arsenic" Color=3 Symbol=3
ELECTRICAL Resistance
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ELECTRICAL Threshold NMOS V="-30 30 0.01" Qss=5e10
9.4.14 pMOS Metal
$ Jinendra Raja Jain (jrjain)
$ EE410 CIS/CMOS-II Process: PMOS Metal Region
$ Filename: PMOS_Metal.inp
$ Dopant Diffusion Model
METHOD PD.FULL
$ Wafer Initialization
INITIALIZE In.File=Struct_Files/PMOS_Field.str
$ Polysilicon Plasma Etch
Etch Polysilicon All
$ Standard Photoresist Strip
$ Photolithography #4 - N-Select
$ Matrix Photoresist Strip
$ Standard Photoresist Strip
$ Standard Pre-Diffusion Clean
$ Boron Blanket Implant
IMPLANT BF2 Dose=1e15 Energy=80 Tilt=7 Gaussian
$ Standard Pre-Diffusion Clean
$ LTO Deposition (Undoped Target Thickness = 50nm, Phosphorus-Doped (8%)
$ Target Thickness = 550nm)
DEPOSITION Oxide Thickness=.6
$ Standard Pre-Diffusion Clean
$ LTO Densification
DIFFUSION Time=30 Temperature=800 T.Final=950 Argon
DIFFUSION Time=5 Temperature=950 DryO2
DIFFUSION Time=30 Temperature=950 Steam
DIFFUSION Time=5 Temperature=950 DryO2
DIFFUSION Time=20 Temperature=950 T.Final=800 Argon
$ Photolithography #5 - Contact Holes
$ Ash Photoresist
$ Standard Photoresist Strip
$ Standard Pre-Diffusion Clean
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$ Aluminum/Silicon Alloy Deposition (Target Thickness = 10000A)
DEPOSITION Aluminum THICKNESS=1
$ Photolithography #6 - Metal
$ PRX-127 Photoresist Strip
$ PRS-1000 Metal Clean
$ Anneal and Alloy (FGA Anneal with 10% H2 in N2)
$ Output Results
OPTION Device=postscript Plot.Out="PS_Files/PMOS_Metal.ps"
SELECT Z=Doping
PRINT Layers
SELECT Z=Log10(Boron) Title="PMOS Metal Impurity Concentration"
+ Label = "Log(Concentration) (cm-3)"
PLOT.1D Line.Type=1 Color=1 Symbol=1 Left=-2 Right=2 Top=21
SELECT Z=Log10(Phosphorus)
PLOT.1D !Axes !Clear Line.Type=2 Color=2 Symbol=2
SELECT Z=Log10(Arsenic)
PLOT.1D !Axes !Clear Line.Type=3 Color=3 Symbol=3
LABEL X=1 Y=20 LABEL="Boron" Color=1 Symbol=1
LABEL X=1 Y=19.5 LABEL="Phosphorus" Color=2 Symbol=2
LABEL X=1 Y=19 LABEL="Arsenic" Color=3 Symbol=3
ELECTRICAL Resistance
ELECTRICAL Threshold PMOS V="-50 50 0.01" Qss=5e10
9.4.15 pMOS Poly
$ Jinendra Raja Jain (jrjain)
$ EE410 CIS/CMOS-II Process: PMOS Poly Region
$ Filename: PMOS_Poly.inp
$ Dopant Diffusion Model
METHOD PD.FULL
$ Wafer Initialization
INITIALIZE In.File=Struct_Files/PMOS_Field.str
$ Standard Photoresist Strip
$ Photolithography #4 - N-Select
$ Matrix Photoresist Strip
$ Standard Photoresist Strip
$ Standard Pre-Diffusion Clean
$ Boron Blanket Implant
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IMPLANT BF2 Dose=1e15 Energy=80 Tilt=7 Gaussian
$ Standard Pre-Diffusion Clean
$ LTO Deposition (Undoped Target Thickness = 50nm, Phosphorus-Doped (8%)
$ Target Thickness = 550nm)
DEPOSITION Oxide Thickness=.6
$ Standard Pre-Diffusion Clean
$ LTO Densification
DIFFUSION Time=30 Temperature=800 T.Final=950 Argon
DIFFUSION Time=5 Temperature=950 DryO2
DIFFUSION Time=30 Temperature=950 Steam
DIFFUSION Time=5 Temperature=950 DryO2
DIFFUSION Time=20 Temperature=950 T.Final=800 Argon
$ Photolithography #5 - Contact Holes
$ Ash Photoresist
$ Standard Photoresist Strip
$ Standard Pre-Diffusion Clean
$ Aluminum/Silicon Alloy Deposition (Target Thickness = 10000A)
DEPOSITION Aluminum THICKNESS=1
$ Photolithography #6 - Metal
$ Dry Aluminum Etch
ETCH Aluminum All
$ Silicon Freckle Etch
$ PRX-127 Photoresist Strip
$ PRS-1000 Metal Clean
$ Anneal and Alloy (FGA Anneal with 10% H2 in N2)
$ Output Results
OPTION Device=postscript Plot.Out="PS_Files/PMOS_Poly.ps"
SELECT Z=Doping
PRINT Layers
SELECT Z=Log10(Boron) Title="PMOS Poly Impurity Concentration"
+ Label = "Log(Concentration) (cm-3)"
PLOT.1D Line.Type=1 Color=1 Symbol=1 Left=-2 Right=2 Top=21
SELECT Z=Log10(Phosphorus)
PLOT.1D !Axes !Clear Line.Type=2 Color=2 Symbol=2
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SELECT Z=Log10(Arsenic)
PLOT.1D !Axes !Clear Line.Type=3 Color=3 Symbol=3
LABEL X=1 Y=20 LABEL="Boron" Color=1 Symbol=1
LABEL X=1 Y=19.5 LABEL="Phosphorus" Color=2 Symbol=2
LABEL X=1 Y=19 LABEL="Arsenic" Color=3 Symbol=3
ELECTRICAL Resistance
ELECTRICAL Threshold PMOS V="-30 30 0.01" Qss=5e10
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9.5 Appendix E: MEDICI Simulation Code
Presented below are the three MEDICI input les used to extract pMOSFET parameters for
the 20 m length transistor. In order to model the 100 m transistor, identical les were used,
except certain parameters were modied, as specied in the rst input le.
TITLE EE410 PMOS Transistor Simulations, 20 um Transistor
COMMENT Specify a rectangular mesh
MESH SMOOTH=1
X.MESH WIDTH=28 H1=1
$ Gate Length +8um
Y.MESH N=1 L=0
Y.MESH N=2 L=0.500
Y.MESH N=4 L=0.540
Y.MESH DEPTH=1.54 H1=0.05
Y.MESH DEPTH=5.54 H1=0.5
COMMENT Eliminate some unnecessary substrate nodes
ELIMIN COLUMNS Y.MIN=2.5
ELIMIN ROWS Y.MIN=3.5
COMMENT Specify oxide and silicon regions
REGION SILICON IY.MIN=4 NAME=BODY
REGION OXIDE IY.MAX=4
REGION POLYSILI X.MIN=4 X.MAX=24 IY.MAX=2 NAME=GATE
$x.max=gate+4
COMMENT Electrode definition
ELECTR NAME=Gate TOP X.MIN=4 X.MAX=24
$ X.MAX=gate+4
ELECTR NAME=Substrate BOTTOM
ELECTR NAME=Source X.MIN=1 X.MAX=3 IY.MAX=4
ELECTR NAME=Drain X.MIN=25 X.MAX=27 IY.MAX=4
$ X.MIN=GATE+5
$ X.MAX=GATE+7
COMMENT Specify impurity profiles and fixed charge\\
+ background substrate doping \\
PROFILE N-TYPE N.PEAK=1E15 UNIFORM Y.MIN=0.540\\
+ OUT.FILE=DPdopproDS.out REGION=BODY\\
PROFILE N-TYPE N.PEAK=4.43E16 Y.CHAR=0.13 Y.MIN=0.54 REGION=BODY\\
COMMENT Source Implant\\
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PROFILE IN.FILE=psourcets.out 1d.ascii n.column=3 y.column=2
+ p.column=4 x.min=0.0 width=4 xy.rat=.75 y.offset=0.54
+ REGION=BODY
$PROFILE P-TYPE N.PEAK=3E19 Y.JUNCTION=0.4 X.MIN=0.0 WIDTH=4 Y.MIN=0.065
$ + XY.RAT=.75
COMMENT Drain Implant
PROFILE IN.FILE=psourcets.out 1d.ascii n.column=3 y.column=2
+ p.column=4 x.min=24 width=4 xy.rat=.75 y.offset=0.54
+ REGION=BODY
$ x.min=gate+4
$ PROFILE P-TYPE N.PEAK=3E19 Y.JUNCTION=0.4 X.MIN=104 WIDTH=4
$ + XY.RAT=.75 Y.MIN=0.065
COMMENT Gate profile
PROFILE IN.FILE=pchants.out 1d.ascii n.column=3 y.column=2 p.column=4
+ X.MIN=4 REGION=GATE X.MAX=24 xy.rat=0.01 y.offset=0.54
$ X.MAX=GATE+4
$ PROFILE P-TYPE N.PEAK=5E18 Y.CHAR=0.01
PLOT.2D GRID TITLE="Initial Grid-PMOS 100 um" FILL SCALE $ +
DEVICE=postscript PLOT.OUT=NoHaloInGri.eps
COMMENT Regrid on doping REGRID DOPING LOG IGNORE=OXIDE
RATIO=2 SMOOTH=1 + IN.FILE=DPdopproDS.out PLOT.2D GRID
TITLE="Doping Regrid-PMOS 100 um" FILL SCALE $ +
DEVICE=postscript PLOT.OUT=NoHaloDopRe.eps
COMMENT Specify contact parameters
CONTACT NAME=Gate
CONTACT NAME=Source
CONTACT NAME=Drain
CONTACT NAME=Substrate
COMMENT Specify physical models to use
MODELS CONMOB FLDMOB SRFMOB2
COMMENT Symbolic factorization, solve, regrid on potential
SYMB CARRIERS=2
METHOD ICCG DAMPED
SOLVE
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REGRID POTEN IGNORE=OXIDE RATIO=.2 MAX=1 SMOOTH=1 +
IN.FILE=DPdopproDS.out + OUT.FILE=DPmeshsolnMS.out PLOT.2D
GRID TITLE="Potential Regrid-PMOS" FILL SCALE $ +
DEVICE=postscript PLOT.OUT=NoHaloPotRe.eps
COMMENT Solve using the refined grid, save solution for later use
SYMB CARRIERS=2
SOLVE OUT.FILE=DPinitS
COMMENT Extract init channel length to aid in refining structure
EXTRACT MOS.PARA
COMMENT Impurity profile plots PLOT.1D DOPING X.START=.0
X.END=28 Y.START=0.541 Y.END=0.541 + Y.LOG POINTS
BOT=1E15 TOP=1E21 COLOR=2 + TITLE="Channel Impurity
Profile-PMOS 100" $x.end=gate+8 $ + DEVICE=postscript
PLOT.OUT=NoHaloChDop.eps LABEL LABEL="Y = 0.0001 um" PLOT.1D
DOPING X.START=2 X.END=2 Y.START=0 Y.END=2.5 + Y.LOG
POINTS BOT=1E15 TOP=1E22 COLOR=2 + TITLE="SOURCE Impurity
Profile" $ + DEVICE=postscript PLOT.OUT=NoHaloLDDDop.eps
LABEL LABEL="X = 2 um" PLOT.1D DONORS X.START=14 X.END=14
Y.START=0 Y.END=2.5 + Y.LOG POINTS BOT=1E14 TOP=1E22
COLOR=2 + TITLE="Gate Impurity Profile" $ +
DEVICE=postscript PLOT.OUT=NoHaloGatDop.eps LABEL LABEL="X = 14
um-middle Channel Vertical Profile" PLOT.1D ACCEPTOR X.START=54
X.END=14 Y.START=0 Y.END=2.5 + POINTS COLOR=4 UNCHANGE
PLOT.2D BOUND TITLE="Impurity Contours-100 um PMOS" FILL SCALE
$ + DEVICE=postscript PLOT.OUT=NoHaloImpCon.eps CONTOUR
DOPING LOG MIN=16 MAX=20 DEL=.5 COLOR=2 CONTOUR DOPING LOG
MIN=-16 MAX=-15 DEL=.5 COLOR=1 LINE=2
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TITLE EE410 PMOS Transistor Simulations, 20 um Transistor
COMMENT Calculate Gate Characteristics
COMMENT Read in simulation mesh
MESH IN.FILE=DPmeshsolnMS.out
COMMENT Read in saved solution
LOAD IN.FILE=DPinitS
COMMENT Use Newtons method for the solution
SYMB NEWTON CARRIERS=1 HOLES
COMMENT Setup log file for IV data for a low Vd
LOG OUT.FILE=DPgaLowVd.out
COMMENT Solve for Vds=-0.01 and then ramp gate
SOLVE V(Drain)=-.2
SOLVE V(Gate)=0 ELEC=Gate VSTEP=-.1 NSTEP=51
COMMENT Extract parameter Vth for device refinement
EXTRACT MOS.PARA
COMMENT Plot Ids vs. Vgs
PLOT.1D Y.AXIS=I(Drain) X.AXIS=V(Gate) POINTS COLOR=2
+ TITLE="Gate Characteristics--Low Vds"
LABEL LABEL="Vds = -0.2v" X=-1.6 Y=-0.7E-6
COMMENT Setup log file for IV data for a high Vds
LOG OUT.FILE=DPgaHighVd.out
COMMENT Solve for Vds=-4 and then ramp gate
SOLVE V(Drain)=-4
SOLVE V(Gate)=0 ELEC=Gate VSTEP=-.1 NSTEP=51
COMMENT Extract parameter Vth just for fun
EXTRACT MOS.PARA
COMMENT Plot Ids vs. Vgs for high Vds
PLOT.1D Y.AXIS=I(Drain) X.AXIS=V(Gate) POINTS COLOR=2
+ TITLE="Gate Characteristics--High Vds"
LABEL LABEL="Vds = -1.2v" X=-1.6 Y=-0.7E-4
COMMENT Plot Results simultaneously
PLOT.1D IN.FILE=DPgaHighVd.out Y.AXIS=I(Drain) X.AXIS=V(Gate)
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+ POINTS COLOR=4 LINE.TYP=2 SYMBOL=1
+ TITLE="Subthreshold Behavior" Y.LOGARI
LABEL LABEL="Vds = -4.0v" COLOR=4 SYMBOL=1
PLOT.1D IN.FILE=DPgaLowVd.out Y.AXIS=I(Drain) X.AXIS=V(Gate)
+ POINTS COLOR=2 LINE.TYP=1 SYMBOL=2 Y.LOGARI UNCHANGE
LABEL LABEL="Vds = -0.2v" X=-3 COLOR=2 SYMBOL=2
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TITLE EE410 PMOS Transistor Simulatrions, 20 um Transistor
COMMENT Calculate Drain Characteristics
COMMENT Read in simulation mesh
MESH IN.FILE=DPmeshsolnMS.out
COMMENT Read in initial solution
LOAD IN.FILE=DPinitS
COMMENT Do a Poisson solve only to bias the gate
SYMB CARRIERS=1 HOLES
METHOD ICCG DAMPED
SOLVE V(Gate)=0.0
COMMENT Now solve for new gate voltage
SYMB NEWTON CARRIERS=1 HOLES
LOG OUT.FILE=DPdrainIV00.out
SOLVE V(Drain)=0.0 ELEC=Drain VSTEP=-0.1 NSTEP=52
SYMB CARRIERS=1 HOLES
METHOD ICCG DAMPED
SOLVE V(Gate)=-0.5
COMMENT Use Newtons method and solve for holes
SYMB NEWTON CARRIERS=1 HOLES
COMMENT Setup log file for IV data
LOG OUT.FILE=DPdrainIV05.out
COMMENT Ramp the drain
SOLVE V(Drain)=0.0 ELEC=Drain VSTEP=-0.1 NSTEP=52
SYMB CARRIERS=1 HOLES
METHOD ICCG DAMPED
SOLVE V(Gate)=-1.0
COMMENT Now solve for new gate voltage
SYMB NEWTON CARRIERS=1 HOLES
LOG OUT.FILE=DPdrainIV10.out
SOLVE V(Drain)=0.0 ELEC=Drain VSTEP=-0.1 NSTEP=52
SYMB CARRIERS=1 HOLES
METHOD ICCG DAMPED
SOLVE V(Gate)=-1.5
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COMMENT Now solve for new gate voltage
SYMB NEWTON CARRIERS=1 HOLES
LOG OUT.FILE=DPdrainIV15.out
SOLVE V(Drain)=0.0 ELEC=Drain VSTEP=-0.1 NSTEP=52
COMMENT Reset gate bias for next run
SYMB CARRIERS=1 HOLES
METHOD ICCG DAMPED
SOLVE V(Gate)=-2
COMMENT Now solve for new gate voltage
SYMB NEWTON CARRIERS=1 HOLES
LOG OUT.FILE=DPdrainIV20.out
SOLVE V(Drain)=0.0 ELEC=Drain VSTEP=-0.1 NSTEP=52
SYMB CARRIERS=1 HOLES
METHOD ICCG DAMPED
SOLVE V(Gate)=-2.5
COMMENT Now solve for new gate voltage
SYMB NEWTON CARRIERS=1 HOLES
LOG OUT.FILE=DPdrainIV25.out
SOLVE V(Drain)=0.0 ELEC=Drain VSTEP=-0.1 NSTEP=52
COMMENT Repeat for each gate voltage value
SYMB CARRIERS=1 HOLES
METHOD ICCG DAMPED
SOLVE V(Gate)=-3
SYMB NEWTON CARRIERS=1 HOLES
LOG OUT.FILE=DPdrainIV30.out
SOLVE V(Drain)=0.0 ELEC=Drain VSTEP=-0.1 NSTEP=52
SYMB CARRIERS=1 HOLES
METHOD ICCG DAMPED
SOLVE V(Gate)=-3.5
COMMENT Now solve for new gate voltage
SYMB NEWTON CARRIERS=1 HOLES
LOG OUT.FILE=DPdrainIV35.out
SOLVE V(Drain)=0.0 ELEC=Drain VSTEP=-0.1 NSTEP=52
SYMB CARRIERS=1 HOLES
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METHOD ICCG DAMPED
SOLVE V(Gate)=-4
SYMB NEWTON CARRIERS=1 HOLES
LOG OUT.FILE=DPdrainIV40.out
SOLVE V(Drain)=0.0 ELEC=Drain VSTEP=-0.1 NSTEP=52
SYMB CARRIERS=1 HOLES
METHOD ICCG DAMPED
SOLVE V(Gate)=-4.5
SYMB NEWTON CARRIERS=1 HOLES
LOG OUT.FILE=DPdrainIV45.out
SOLVE V(Drain)=0.0 ELEC=Drain VSTEP=-0.1 NSTEP=52
COMMENT Plot Ids vs. Vds Curves
PLOT.1D Y.AXIS=I(Drain) X.AXIS=V(Drain) LINE.TYP=1
+ SYMBOL=1 POINTS COLOR=1
+ TITLE="Drain Output Characteristics"
LABEL LABEL="Vg=-4.5" X=-1 Y=-3.3E-6 COLOR=1 SYMBOL=1
PLOT.1D IN.FILE=DPdrainIV40.out Y.AXIS=I(Drain) X.AXIS=V(Drain)
+ LINE.TYP=2 SYMBOL=2 POINTS COLOR=2 UNCHANGE
PLOT.1D IN.FILE=DPdrainIV35.out Y.AXIS=I(Drain) X.AXIS=V(Drain)
+ LINE.TYP=3 SYMBOL=3 POINTS COLOR=3 UNCHANGE
LABEL LABEL="Vg=-3.5" X=-1 Y=-3.1E-6 COLOR=3 SYMBOL=3
PLOT.1D IN.FILE=DPdrainIV30.out Y.AXIS=I(Drain) X.AXIS=V(Drain)
+ LINE.TYP=4 SYMBOL=4 POINTS COLOR=4 UNCHANGE
PLOT.1D IN.FILE=DPdrainIV25.out Y.AXIS=I(Drain) X.AXIS=V(Drain)
+ LINE.TYP=5 SYMBOL=5 POINTS COLOR=5 UNCHANGE
LABEL LABEL="Vg=-2.5" X=-1 Y=-2.9e-6 COLOR=5 SYMBOL=5
PLOT.1D IN.FILE=DPdrainIV20.out Y.AXIS=I(Drain) X.AXIS=V(Drain)
+ LINE.TYP=6 SYMBOL=6 POINTS COLOR=6 UNCHANGE
PLOT.1D IN.FILE=DPdrainIV15.out Y.AXIS=I(Drain) X.AXIS=V(Drain)
+ LINE.TYP=7 SYMBOL=7 POINTS COLOR=7 UNCHANGE
LABEL LABEL="Vg=-1.5" X=-1 Y=-2.7e-6 COLOR=7 SYMBOL=7
PLOT.1D IN.FILE=DPdrainIV10.out Y.AXIS=I(Drain) X.AXIS=V(Drain)
+ LINE.TYP=8 SYMBOL=8 POINTS COLOR=8 UNCHANGE
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PLOT.1D IN.FILE=DPdrainIV05.out Y.AXIS=I(Drain) X.AXIS=V(Drain)
+ LINE.TYP=9 SYMBOL=9 POINTS COLOR=4 UNCHANGE
LABEL LABEL="Vg=-0.5" X=-1 Y=-2.5e-6 COLOR=9 SYMBOL=9
PLOT.1D IN.FILE=DPdrainIV00.out Y.AXIS=I(Drain) X.AXIS=V(Drain)
+ LINE.TYP=10 SYMBOL=10 POINTS COLOR=10 UNCHANGE
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9.6 Appendix F: Individual Group Member Contributions
Table 51 presents the contributions made by each group member during the testing/characterization
phase of the project.
Table 51: Individual Group Member Contributions - Testing/Characterization
Member Contributions
Deji Akinwande nMOSFETs, Sheet Resistivity
Aaron Gibby pMOSFETs, Parasitics, Continuity, Isolation
Jinendra Raja Jain MOSCAPs, Diodes, Contact Chains, Contact Resistance
Saeroonter Oh MOSCAPs, Diodes, Contact Chains, Contact Resistance
Shiyu Sun nMOSFETs, Sheet Resistivity
Gloria Wong pMOSFETs, Parasitics, Continuity, Isolation
Table 52 presents the contributions made by each group member during the report-writing
phase of the project.
Table 52: Individual Group Member Contributions - Report
Member Contributions
Deji Akinwande Secs. 6.1.1, 6.2.1
Aaron Gibby Secs. 5, 6.1.2, 7.2, 8, 9
Jinendra Raja Jain Management/compilation/editing, Secs. 1, 2, 3, 4, 6.1.3, 6.1.4, 7.1, 9
Saeroonter Oh Secs. 6.2.2, 6.2.3, 6.1.4
Shiyu Sun Secs. 6.2.1
Gloria Wong Secs. 1, 6.1.2, 6.2.4, 6.3, 7.3, 7.4, 8
Akinwande, Gibby, Jain, Oh, Sun, Wong 173
CIS/CMOS-II Modeling/Fabrication/Characterization REFERENCES
References
[1] K. Saraswat, EE410 CMOS Process Schedule, Stanford University, Stanford, CA, Winter 2004-05.
[2] K. Saraswat, EE410 TSUPREM-IV simulation handout, Stanford University, Stanford, CA, Winter
2004-05.
[3] Plummer, Deal, and Grin, Silicon VLSI Technology: Fundamentals, Practice and Modeling, Upper
Saddle River, NJ, USA: Prentice Hall, 2000.
[4] Synopsys, TSUPREM-4: Two-Dimensional Process Simulation Program - User Manual (ver. 2002.4),
Feb. 2003.
[5] Pierret, Robert F., Semiconductor Device Fundamentals, Reading, MA, USA: Addison-Wesley, 1996.
[6] Sun and Plummer, IEEE TED, 27, 1980: p. 1497.
[7] S. Simon Wong, EE316 Course notes, Stanford University, Stanford, CA, Winter 2003-04.
[8] K. Saraswat, EE410 CIS/CMOS-II Instruction Manual, Stanford University, Stanford, CA, Winter
2004-05.
[9] Walton, A.J., Microelectronic Test Structures
[10] J. Harris, EE216 Course Notes, Stanford University, Stanford, CA, Fall 2004-05.
* This report was prepared using L
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