IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 60, NO.

5, MAY 2011 1515

Linearizing Dual-Slope Digital Converter

Suitable for a Thermistor
N. Madhu Mohan, Member, IEEE, V. Jagadeesh Kumar, Member, IEEE, and P. Sankaran

Abstract—To measure temperature using a thermistor as the drastically reduced sensitivity. This drawback was sought to be
sensing element, linearization to compensate for the inverse expo- overcome by the use of a reciprocal time generator to obtain a
nential nature of the resistance–temperature characteristic of the digital output proportional to the temperature [4]. The linearity
thermistor is required. A linearizing dual-slope digital converter
(LDSDC) that accepts a thermistor sensor as input and provides was further improved by employing a four-constant fit for the
a digital output that is directly proportional to the temperature relationship governing the temperature and the resistance of
being sensed is presented here. A logarithmic amplifier at the input the thermistor [5], though at the cost of increased complexity
of the LDSDC compensates for the exponential characteristics. as four simultaneous nonlinear equations had to be solved to
The conversion logic of the underlying dual-slope converter is obtain the constants.
suitably modified to implement the required inversion and offset
correction and thus obtain linearization over a wide range of input Bosson’s three-constant law was also approximated to de-
temperature. The efficacy of the proposed LDSDC is established velop a linear temperature–time period converter, incorporat-
through simulation studies and its practicality demonstrated with ing a thermistor [6]. The circuit provided excellent linearity
experimental results obtained on a prototype unit built and tested. (∼0.02%) but over a very narrow range of 10 K, the reason
Analysis of the proffered method to identify possible sources of being that such a small variation was one of the essential
errors is also presented.
assumptions on which the approximation of the thermistor
Index Terms—Direct digital converter, dual-slope converter, lin- characteristic was based. An established technique for the
earization, logarithmic amplifier, resistance-to-digital converter, linearization of the output of a thermistor involved the use of
thermistor.
different kinds of multivibrators [7], [8] where differing degrees
of linearity were obtained over limited ranges of temperatures.
I. I NTRODUCTION
An improvement on this method using an astable multivibrator

I N ANY control or instrumentation process, the temperature

is an important parameter to be measured. Due to its com-
pactness, high sensitivity, accuracy, ruggedness, biocompatibil-
has also been reported [9], which provided acceptable levels
of linearization over a greatly increased temperature range of
0–85◦ C. The output of a thermistor was also sought to be
ity, as well as low time constant and low cost, the thermistor linearized by including it as part of a logarithmic amplifier
is a popular choice for sensing the temperature. However, the network [10].
advantages that the thermistor offers for the measurement of A modified form of a relaxation-oscillator-based temperature
temperature are eclipsed by the highly nonlinear relationship to frequency converter has been implemented using a delay net-
between the resistance Rθ of the thermistor and the temperature work [11], with promising results. An innovative approach to
θ it is subjected to. The precise nature of this relationship solving the thermistor linearization problem has been by using
as well as the means to linearize it has been a matter of the inverse exponential nature of the voltage–time relationship
study for a long time. Though the exponential nature of the of a charging RC network, which is based on a modified square
resistance–temperature relationship of a thermistor was known wave generator [12]. Though these methods achieve desirable
as far back as 1946 [1], with Bosson et al. formulating the three- levels of linearity over limited temperature ranges, none of
constant fit for the lnRθ versus 1/θ curve of the thermistor the methods reported so far achieves linearity over the entire
in 1950 [2], the problem of linearizing this relationship has dynamic range of operation of a thermistor, preserving its high
persisted. sensitivity.
Of the different methods that have been tried in linearizing With the advent of digital technology and the easy avail-
the temperature–resistance relationship of a thermistor, the ability of faster and economically viable processing power,
simplest has been to include a resistor in series and/or in software has come to be increasingly used in the linearization of
parallel with the thermistor [3]. But this technique achieves transducer outputs, making use of ‘look-up tables’ and ‘maps’
linearity only over a small range, that too at the expense of [13], [14]. New techniques like artificial neural networks and
evolutionary algorithms have been proposed to iteratively lin-
Manuscript received June 18, 2010; revised October 31, 2010; accepted earize the output of thermistor based circuits [15], [16]. The
November 1, 2010. Date of publication December 13, 2010; date of current downside of such methods has been the increasing reliance on
version April 6, 2011. The Associate Editor coordinating the review process
for this paper was Dr. Theodore Laopoulos. brute computing power to find the ‘best’ polynomial fit for the
The authors are with the Department of Electrical Engineering, Indian Insti- temperature–resistance relationship of a thermistor.
tute of Technology Madras, Chennai 600036, India (e-mail: vjk@iitm.ac.in). Except for the software-based techniques, the outputs of most
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. of these linearizing circuits are analog in nature and need to be
Digital Object Identifier 10.1109/TIM.2010.2092875 converted to a digital form before being interfaced to digital

0018-9456/$26.00 © 2010 IEEE

1516 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 60, NO. 5, MAY 2011

amplifier as shown in Fig. 1. In such a condition, the output vlog

of the logarithmic amplifier is

vlog = ln(Rθ ) − ln(RA ). (4)

A comparison of (3) and (4) indicates that the value of resistor

RA must be equal to A, one of the constants of the thermistor as
given in (1). With this condition, the output of the logarithmic
amplifier is

vlog = ln(Rθ ) − ln(A). (5)

The output of the logarithmic amplifier is given as input to a

Fig. 1. Schematic of the proposed dual-slope LDSDC suitable for a dual-slope analog-to-digital converter (DSADC). The hardware
thermistor. of the DSADC, again shown in block schematic form in Fig. 1,
is the same as a conventional DSADC but the conversion logic
instruments. It would evidently make for a simpler and more is suitably modified to obtain inversion and offset subtraction
robust system if the analog-to-digital converter becomes an as required to implement (3).
integral part of the linearizing circuit, so that the final output As in any typical DSADC, the ADC part of the LDSDC also
is linear as well as digitally compatible. A linearizing dual- contains an RC integrator (realized with opamp and resistor R
slope digital converter (LDSDC) which offers such novelties and feedback capacitor C as indicated in Fig. 1), a comparator
has been presented earlier and its efficacy validated through and a timing and logic unit (TLU). The logic of the TLU is
simulation [17]. This paper details the experimental validation designed to perform two integrations by suitably controlling the
of the LDSDC suitable for a thermistor. A rigorous analysis of input to the integrator through a single-pole three-way analog
the scheme to identify and quantify various sources of errors is switch S. While two of the inputs of S are tied to individual
also presented. reference voltages (+VR and −VR ) of equal magnitude but
opposite polarity, the third input is tied to vlog , the output
voltage of the logarithmic amplifier. Switch S is controlled
II. LDSDC S UITABLE FOR T HERMISTORS
by the control lines A0 and A1 emanating from the TLU.
The equation that relates the resistance Rθ of a thermistor to If A1 A0 = ‘01’, then position 1 is selected on S and the dc
its temperature θ as derived by Bosson et al. [2] is reference voltage +VR is applied as input to the integrator. If
β
A1 A0 is “10”, then position 2 is set on S, so that the input to the
Rθ = Ae θ+γ . (1) integrator is −VR . If A1 A0 = ‘11’, then position 3 is selected
and the output of the logarithmic amplifier vlog is chosen as the
Here, A, β, and γ are constants specific to a particular type input to the integrator. A1 A0 = ‘00’ is forbidden. The integra-
of thermistor. To obtain an output directly proportional to tor output voi is fed to a comparator, whose output vc serves as
temperature, the following operations are needed in the order the input to the TLU. If the integrator output voi ≥ 0, then the
given below. output of the comparator vc will be “1” (logic high); otherwise,
(i) First step is to apply natural logarithm to (1) and re- vc will be zero. The timing inside the TLU is accomplished
arrange to get with either an N-bit (for binary output LDSDC) or N-digit (for
a binary coded decimal output LDSDC) presettable up/down
β timer counter, driven by a clock of period Tc (frequency fc ).
= ln Rθ − ln A. (2)
θ+γ Before the process of converting vlog can begin, it needs
to be ensured that the output of the integrator is at zero.
(ii) The second and final step is to invert and manipulate (2)
Therefore, as in any typical DSADC, an auto-zero phase is
to obtain:
necessary whenever a conversion command is issued afresh. If a
β new conversion succeeds a previous conversion, the integrator
θ= − γ. (3)
ln Rθ − ln A output will be zero at the end of the previous conversion and
hence, an auto-zero phase can be dispensed with. Thus, the
In the proposed scheme, whose block schematic is shown in LDSDC can be operated either in a controlled (start-stop) or in a
Fig. 1, (3) is implemented with a logarithmic amplifier to obtain continuous conversion mode. In the former, an auto-zero phase
ln Rθ − ln A and a suitably modified dual-slope converter to precedes every conversion cycle while in the latter, the auto-
perform the required tasks of inversion and offset subtraction. zero phase is invoked only once at the start of the measurement
In a typical logarithmic amplifier, such as the LOG112 [18], cycle.
the output is obtained as a logarithm of the ratio of two currents.
In the present application, the two currents are derived from
A. Auto-Zero Phase
a single dc reference voltage. The thermistor is connected as
one of the current determining resistors while a fixed value When a convert command is given afresh asynchronously,
resistor RA dictates the second input current of the logarithmic the initial state of the circuit in Fig. 1 may be such that the
MOHAN et al.: LINEARIZING DUAL-SLOPE DIGITAL CONVERTER SUITABLE FOR A THERMISTOR 1517

This state is maintained for a preset fixed period of time T1 ,

where T1 = N1 Tc . Here, N1 is a preselected integer and Tc is
the period of the TLU clock. Typically, this is accomplished
by preloading the register, i.e. NT LU , of the timer counter with
N1 , setting the mode to “count down” and ascertaining whether
NT LU has reached zero. Sensing that NT LU has reached
zero, the TLU logic sets A1 A0 to be “11”, switching the output
of the logarithmic amplifier vlog , as input to R. Simultaneously,
the register NT LU of the timer counter is loaded with a preset
value of (Nf s − Nk ) and its mode set to “count up”. Here, Nf s
is the full-scale count of the timer counter and the counter rolls
over to zero after reaching Nf s (Nf s + 1 ⇒ “00000”). Nk is a
constant, dependent on the thermistor characteristic. Since the
logarithmic amplifier has been so designed that its output is
always positive, voi starts to ramp down with a slope vlog /RC,
Fig. 2. Voltage waveforms at the output of the integrator (voi ) and the
comparator (vc ) of the LDSDC. and reaches zero after a time period denoted by T2 . The output
of the integrator reaching zero is marked by a change of state
of the comparator from high to low, which indicates to the TLU
output of the integrator voi is negative which implies that the the end of the conversion phase and thereby, the measurement
output of the comparator vc will be low. The condition vc cycle. At the end of time period T2 , the TLU outputs N2 , the
being low is sensed by the TLU and the control logic for this contents of the timer counter (NT LU ) at that instant. During
condition ensures that the control lines A1 A0 to the switch S the period T2 , the counter counts Nk clock periods to reach zero
are set at “10”, so that the negative reference voltage −VR and then counts up to N2 . Hence, T2 = (Nk + N2 )Tc . Making
is connected to the fixed resistance R. As a result, a constant use of the fact that the total charge acquired by the capacitor C
current ic = VR /R starts flowing through the capacitor C and over the conversion phase is zero, we get:
the output of the integrator ramps up toward zero. voi reaching
zero is indicated to the TLU by vc changing state from low to VR vlog
T1 = T2 . (6)
high, marking the end of the auto-zero phase. RC RC
On the other hand, if the circuit were to come up in a state
Substituting the values of T1 = N1 Tc and T2 = (Nk + N2 )Tc
where the integrator output is positive, this would be indicated
in (6), we obtain:
to the TLU by the comparator output vc being high. Such
a state would cause the TLU logic to set the control lines VR N1 Tc = vlog (Nk + N2 )Tc . (7)
A1 A0 to “01”, so that the resistance R is connected to the
positive reference voltage +VR causing a current −VR /R to Using the value of vlog from (5) in (7) and rearranging,
flow through the capacitor, discharging it. As a result, the output results in
of the integrator would now ramp down toward zero. When voi
reaches zero, vc changes state from high to low, signaling the V R N1
N2 = − Nk . (8)
end of the auto-zero phase to the TLU, which then initiates ln Rθ − ln A
the appropriate sequence for the conversion phase. Thus, a
A comparison of (3) and (8) indicates that if we choose
transition of the comparator state, either from low to high or
VR N1 = β and Nk = γ, then
from high to low, indicates the end of the auto-zero phase. The
broken lines in the waveform diagram of Fig. 2 indicate the N2 = θ. (9)
integrator and comparator outputs during the auto-zero phase.
Thus, the output count N2 directly provides the temperature
being sensed by the thermistor. It should be noted here that
B. Conversion Phase
while applying the logarithm to the resistance of the thermistor
Once the output of the integrator voi reaches zero, either at is achieved with the help of a logarithmic amplifier, the inver-
the end of an auto-zero phase in the start-stop mode or at the end sion and offset correction required for linearizing the thermistor
of a previous conversion in the continuous conversion mode, a characteristics is realized simply by exchanging the integration
conversion phase is initiated. At this point, the logic of con- sequences in a DSADC and preloading the timer counter of
version of the proposed LDSDC differs significantly from the the DSADC with a preset value. In (9), θ, an analog quantity,
logic employed in a conventional DSADC. In a conventional is measured using N2 a digital number, thus θ will only be
DSADC, the first integration is performed with the integrator measured as an integer and the fractional part of θ will not
input tied to the input voltage to be converted. Here, the first appear in the output. This problem can be easily solved by
integration is performed with the integrator input tied to the making the full-scale count (Nf s ) corresponding to the full-
negative reference voltage −VR by setting the control lines scale θ to be 10k θ, thus realizing k decimal digits in the output.
A1 A0 to be “10”. As a result, voi ramps up with a positive For example, in the prototype developed, the value of T1 and
slope given by VR /RC as shown by the solid line in Fig. 2. Tc are chosen such the N2 is 10 000 for θ = 100 ◦ C, resulting
1518 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 60, NO. 5, MAY 2011

in a resolution of 0.01 ◦ C. The possible sources of errors was employed and the compensated offset was found to be
in the proposed LDSDC are discussed next and experimental <0.3 mV, resulting in an error of < 0.015 ◦ C.
validation of the scheme is given in the sequel.
C. Influence of the Stability of the Fixed Time Interval T1
III. E RROR A NALYSIS OF THE LDSDC
As in a conventional DSADC, the integrator in the proposed
A glance at (8) and (9) might seem to indicate that the circuit is connected to the reference voltage −VR for a fixed
stability of the measured temperature θ depends only on the duration T1 . If the time period T1 is in error by an amount ΔT1 ,
fixed quantities VR , N1 , RA , and Nk . But a deeper analysis then (6) gets modified as
of the process which led to the formulation of the above VR vlog
expressions would show that the success of (9) depends on a (T1 + ΔT1 ) = T2 (12)
RC RC
few assumptions that can deviate from the ideal, in a practical
implementation of the scheme. Some of these assumptions are resulting in the final expression
that the reference voltage VR and the time period T1 (= N1 Tc )  
ΔT1 ΔT1
are constant and stable, that the change in resistance of the N2 = θ 1 ± ± Nk . (13)
T1 T1
thermistor is due only to the temperature that it seeks to measure
and that the opamp, comparator, and switch used in Fig. 1 are Equation (13) indicates that an error in the first integration
ideal. In this section, we investigate whether these assumptions period also results in a gain error and an offset.
are justified and if not, to determine the extent to which (9) and
thereby, the circuit performance is affected.
D. Error Due to Self-Heating of the Thermistor
When discussing the operation of the circuit, it was assumed
A. Stability of the Reference Voltage VR
that the change in resistance of the thermistor was solely due
Any variation in the magnitude of the reference voltage does to the temperature that the device was seeking to measure.
not affect vlog as both the currents Iθ and IA given to the This assumption is not entirely valid, because the measurement
logarithmic amplifier (indicated in Fig. 1) are derived from the of the thermistor resistance is accomplished by electrically
same reference voltage. However, the proposed LDSDC suit- exciting it with a voltage VR . As a result, there is a small amount
able for the thermistor is essentially a voltage–time converter, of local heating due to the VR2 /Rθ effect, which could degrade
wherein the unknown voltage vlog is compared with a standard the performance of the circuit, unless carefully designed for.
reference voltage VR . Therefore, any uncertainty or instability Self-heating is normally specified by the dissipation constant,
in VR is bound to affect the measurement of temperature θ. which indicates the amount of power required to raise the
If the reference voltage changes to (VR ± ΔVR ), then (8) gets temperature of the thermistor by 1 K. A thermistor excited by
modified as a constant voltage source could introduce significant errors due
  to self-heating, when its resistance decreases at higher tempera-
ΔVR ΔVR
N2 = θ 1 ± ± Nk . (10) tures. For example, the NTCS0603E3223FMT thermistor from
VR VR
Vishay Electronics, which has a dissipation constant of 3 mW/K
A comparison of (9) and (10) shows that a deviation in [19], if excited by a 1.5 V source, would introduce an error as
the reference voltage introduces a gain error and an offset in large as 1 ◦ C when measuring a temperature of 120 ◦ C. Hence,
the output, both of which can be easily compensated. In the in the prototype, the excitation voltage was kept as 100 mV,
prototype unit developed, the reference voltage was kept as 1 V resulting in the elevation of the thermistor temperature due to
± 5 mV, resulting in a full-scale error of ±0.5 ◦ C. self-heating to be < 0.01 ◦ C. The error due to self-heating can
be minimized by limiting the current through the thermistor or
by choosing a thermistor with a large dissipation constant, if
B. Effect of Offset at the Output of the Logarithmic Amplifier the former choice cannot be availed of for reasons of sensitivity.
A practical logarithmic amplifier [18] may have an offset In the proposed method, the reference voltage +VR powers the
voltage. If ΔVL is the offset voltage at the output of the thermistor and its magnitude must be chosen such that this error
logarithmic amplifier, then (9) gets modified as becomes negligible.
   2 
ΔVL ΔVL
N2 = θ ∓ (θ + Nk ) ± ∓ . . . . (11) E. Influence of Delays Caused by the Comparator and Switch
vlog vlog
During the discussion on the operation of the circuit, it has
Equation (11) indicates that an offset at the output of the been assumed that the comparator would change states instanta-
logarithmic amplifier introduces gain error and an offset that neously when the integrator output changes polarity. Similarly,
are nonlinear in nature. Variation of vlog by as little as 5 mV it was assumed that the switch would respond immediately
is sufficient to cause the measured temperature to be in error when its control lines, A1 A0 change. In actual practice, both
by more than 0.5 ◦ C. Hence, care must be taken to ensure the comparator as well as the switch would take a finite amount
that the offset at the output of the logarithmic amplifier is of time to respond to changes in their control inputs. If the
properly nulled. In the prototype unit, an offset-nulling circuit delay due to the comparator is denoted by τc and that caused
MOHAN et al.: LINEARIZING DUAL-SLOPE DIGITAL CONVERTER SUITABLE FOR A THERMISTOR 1519

by the switch as τs , then the effect of such delay would be Hence, a mismatch in the ON resistances of switch S results in
that the voltage vlog , instead of being switched to the fixed a gain error and an offset at the output.
resistance for a time period T1 , would now be connected for
a period (T1 + τc + τs ). This situation is similar to the one
depicted in (13). If the total delay caused by the comparator and H. Influence of Other Factors
switch is very small when compared to the fixed time period
In deriving (9), it was assumed that VR N1 = β and Nk = γ.
T1 , the errors caused by such delays can be considered to be
While it is possible to precisely set VR N1 = β by trimming VR ,
negligible. For comparators like the LM311 which was used
it may not be possible to make Nk exactly equal to γ as Nk can
in the prototype or the switch HCF4052, the maximum delay
only be an integer, while γ can, in general, have a decimal part.
would be 200 and 60 ns, respectively, which are very small
This rounding-off error will be in addition to the quantization
in comparison to the normal value of 100 ms used for T1 and
error of the underlying DSADC of the LDSDC.
hence, the error introduced by these delays will be negligible.

F. Error Caused by Offset Voltages of the OPAMP and IV. E XPERIMENTAL R ESULTS
Comparator
To verify the proposed technique, the circuit schematic given
The offset voltage of the opamp used in the integrator has the in Fig. 1 was simulated using Orcad PSpice and its performance
effect of adding to or subtracting from the total charge gained studied under various conditions [17]. The results of the simu-
by the feedback capacitor during T1 , depending on the polarity lation proved the efficacy of the proposed scheme. To verify the
of the offset voltage. Its action is therefore similar to that of the practicality of the proffered method, a prototype unit was built
change in the reference voltage VR described in Section III-A. and tested.
For high-accuracy measurements, it is therefore necessary that The circuit of the proposed LDSDC for a thermistor, shown
opamps with low-input offset voltages be used or appropriate in Fig. 1, was set up on a prototyping board in the laboratory.
steps taken to trim the offset voltages using external circuitry. It was powered by the AEE01AA36, a 5-V dc/dc converter
Without proper compensation, the measured temperatures can from Messrs Astec Power. The reference voltages of ±1 V and
be in error by as much as 1.25 ◦ C, particularly when operating ±100 mV were derived using the LM385 1.2-V reference
with low reference voltages. The offset of the opamp used in diodes and precision resistances. The LOG112 from Messrs
the prototype unit was the OP97 with an offset voltage less than Texas Instruments was chosen for use as the logarithmic am-
25 μV, resulting in negligible error in the measurement. plifier not only for the high accuracy and precision it provides
Offset voltage present in the comparator will simply shift over a wide dynamic range but also for its low offset voltage
the baseline, shown in Fig. 2, depending on the polarity and and temperature drift. More importantly, the LOG112 provides
magnitude of the offset. As long as this offset is small and does an output scaling amplifier, which simplifies the task of com-
not change during the conversion phase, it will not affect the pensating the offset of the logarithmic amplifier. With its low
operation of the LDSDC. offset voltage and bias currents, the OP97 was an easy choice
for use in the integrator. The comparator was built using the
LM311 while the HCF4052 was used as the switch to connect
G. Effect of the Switch Resistance
the resistance R to the various voltages. Power supplies includ-
In the discussion so far, it has been assumed that the switch ing the derived ones were bypassed to ground with 10- and
used for connecting the resistance R to the different reference 0.1-μF capacitances. All ground lines were connected to one
voltages and vlog has no effect on the circuit operation other single point, whose potential was continuously monitored and
than to introduce a delay τs , as discussed in Section III-E. It found to be within ±50 μV of power supply ground.
was assumed that the switch does not introduce any additional The thermistor used in the prototype was the
resistance into the circuit. This assumption is not quite valid in NTCS0603E3223FMT from the SMD0603 series of glass-
practice. Typical switch ON resistance RON can be a few ohms encapsulated NTC thermistors manufactured by Messrs
to a few hundred ohms. If the ON resistances of the switch S are Vishay Electronics. The calibration sources used for testing
the same in positions 2 and 3, then the changed resistor value the prototype unit were the MP40R [20] and MTC650 [21]
at the input of the integrator (R + RON ) appears on both sides temperature calibrators from Messrs Nagman Instruments,
of (6), and hence gets cancelled without affecting the output. If India, which are certified to be within ±0.6 ◦ C. The TLU was
the ON resistances of switch S are different in positions 2 and 3 built on a Virtual Instrument platform, around the USB-6251
resulting in, for example, the total resistance as (R + RON ) in [22] DAQ hardware and LabVIEW software from Messrs
position 2 and (R + RON )(1 ± α) in position 3, then (6) gets National Instruments. The USB-6251 was interfaced to the
modified as circuit through the BNC2120 accessory. The output of the
comparator was made TTL-compatible and connected to one
VR vlog
T1 = T2 (14) of the digital I/O lines of the USB-6251, which was configured
(R + RON )C (R + RON )(1 ± α)C as an input line. A pair of the digital I/O lines of the DAQ was
resulting in configured as output lines and was used as the control lines A1
and A0 for the switch S. One of the 32-bit general-purpose
N2 = θ(1 ± α) ± αNk . (15) timer counters of the USB-6251 having a resolution of 50 ns
1520 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 60, NO. 5, MAY 2011

Fig. 3. Performance characteristics of the prototype LDSDC suitable for a

thermistor in the range 0–120 ◦ C.

Fig. 4. Performance characteristics of the prototype LDSDC suitable for a

thermistor in the range 30–50 ◦ C.
was used to generate a highly stable and precise pulse train for
the fixed time duration T1 and for the measurement of T2 . The V. C ONCLUSION
logic for the auto-zero and conversion phases was implemented A LDSDC that incorporates as input, a thermistor having an
using a program written in LabVIEW. For proper functioning inverse exponential resistance–temperature characteristic and
of the LDSDC, the voltage swing (VR T1 /RC) of the integrator provides a digital output directly proportional to the tempera-
at the end of the first integration period T1 should be lower ture being sensed, is presented here. The effects on the proposed
than the positive supply voltage of the integrator. Since method due to the use of practical circuit elements, possessing
VR T1 = −βTc , value of RC must be adjusted to ensure the nonideal characteristics are analyzed, and the possible sources
integrator output is less than its supply voltage. The prototype of errors identified and also quantified. It is shown here that
was designed to accommodate a set of R and C values that are most of the nonideal characteristics of circuit elements such
suitable for different thermistors from different manufacturers. as offset of opamp, finite ON resistance of analog switch, and
Apart from the choice of R and C, it is also necessary to delays of switch and comparator lead to a gain error and/or
change the value of Nk depending on the thermistor chosen for offset in the output. Since gain error and offset can be easily
measurement of temperature. A suitable VI was developed to nulled, acceptable levels of accuracy and linearity over a wide
accommodate all the above required choices. The developed range (0–120 ◦ C) are achieved with the proposed LDSDC. The
VI facilitated configuring not only R, C, and Nk , but also proposed LDSDC was simulated to study its performance under
allowed a user to change the values of first integration time controlled conditions with various nonidealities incorporated
T1 , clock period TC , and reference voltage VR . During the in the model employed for simulation. The LDSDC was then
entire process, the reference voltages as well as the output of prototyped and its response studied. It was found that the circuit
the logarithmic amplifier were continuously monitored using functioned as expected and produced results which justify its
highly accurate multimeters from Messrs Keithley (Model use with thermistors for the accurate and reliable measurement
2100) and Hewlett-Packard (34401A). The waveforms of the of temperature, with a maximum error of ±0.3 ◦ C, over the
voltages at critical points of the circuit were also monitored range from 0 to 120 ◦ C.
using the DL750P Scopecorder from Messrs Yokogawa, Japan.
The temperature was varied in steps of 5 ◦ C in the range R EFERENCES
0–120 ◦ C and N2 was obtained using the virtual instrument. [1] J. A. Becker, C. B. Green, and G. L. Pearson, “Properties and uses
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random errors, if any, present in the experimental setup. It was Eng., vol. 65, no. 11, pp. 711–725, Nov. 1946.
[2] G. Bosson, F. Guttman, and L. M. Simmons, “Relationship between tem-
found that there were negligible differences between the ten perature and resistance of a thermistor,” J. Appl. Phys., vol. 21, no. 12,
readings obtained from the prototype unit. This is mainly due to pp. 1267–1268, Dec. 1950.
the 50-ns clock of the timer counter and the stable dc reference [3] J. M. Diamond, “Linearization of resistance thermometers and other trans-
ducers,” Rev. Sci. Instrum., vol. 41, no. 1, pp. 53–60, Jan. 1970.
voltage. The measured temperature is plotted in Fig. 3. The [4] S. Kaliyugavaradan, P. Sankaran, and V. G. K. Murti, “Application of
percentage error in each measurement is also calculated and reciprocal time generation technique to digital temperature measure-
plotted in the same figure. It is seen that the maximum error ment,” IEEE Trans. Instrum. Meas., vol. 43, no. 1, pp. 99–100, Feb. 1994.
[5] S. Kaliyugavaradhan, P. Sankaran, and V. G. K. Murti, “A new com-
over the entire range was found to be less than ±0.2%. The pensation scheme for thermistors and its implementation for response
experiment was repeated for temperatures in the range from 30 linearisation over a wide temperature range,” IEEE Trans. Instrum. Meas.,
to 50 ◦ C, with smaller increments of 1 ◦ C to check the reso- vol. 42, no. 5, pp. 952–956, Oct. 1993.
[6] I. Y. Yankov, C. I. Gigov, and E. A. Yankov, “Linear temperature-to-time
lution of the system. The results which are displayed in Fig. 4 period converters using standard thermistors,” Meas. Sci. Technol., vol. 1,
indicate an even better performance, with a maximum error of no. 11, pp. 1168–1171, Nov. 1990.
less than ±0.1%. As the figures illustrate, the performance of [7] D. K. Stankovic and J. Elazar, “Thermistor multivibrator as the
temperature-to-frequency converter and as a bridge for temperature mea-
the proposed circuit closely matches the results predicted by surement,” IEEE Trans. Instrum. Meas., vol. IM-26, no. 1, pp. 41–46,
simulation. Mar. 1977.
MOHAN et al.: LINEARIZING DUAL-SLOPE DIGITAL CONVERTER SUITABLE FOR A THERMISTOR 1521

[8] Z. P. Nenova and T. G. Nenov, “Linearisation circuit of the thermistor V. Jagadeesh Kumar (M’96) was born in Madras,
connection,” IEEE Trans. Instrum. Meas., vol. 58, no. 2, pp. 441–449, India, on July 21, 1956. He received the B.E. degree
Feb. 2009. in electronics and telecommunication engineering
[9] A. A. Khan and R. Sengupta, “A linear temperature to frequency con- from the University of Madras, Madras, in 1978, and
verter using a thermistor,” IEEE Trans. Instrum. Meas., vol. IM-30, no. 4, the M.Tech. and Ph.D. degrees in electrical engineer-
pp. 296–299, Dec. 1981. ing from the Indian Institute of Technology (I.I.T.),
[10] A. A. Khan, “An improved linear temperature/voltage converter Madras, in 1980 and 1986, respectively.
using thermistor in logarithmic network,” IEEE Trans. Instrum. Meas., He is presently the Head of the Department of
vol. IM-34, pt. 2, no. 5, pp. 635–638, Dec. 1985. Electrical Engineering, I.I.T., Madras. He was a
[11] A. A. Khan and R. Sengupta, “A linear thermistor-based temperature-to- BOYSCAST Fellow at the King’s College, London,
frequency converter using a delay network,” IEEE Trans. Instrum. Meas., during 1987-88 and a DAAD Fellow at the Technical
vol. IM-34, no. 1, pp. 85–86, Mar. 1985. University of Braunschweig, Germany, during 1997. He worked as a Visiting
[12] R. N. Sengupta, “A widely linear temperature to frequency converter using Scientist at the Technical University of Aachen, Germany, during 1999. He
a thermistor in a pulse generator,” IEEE Trans. Instrum. Meas., vol. 37, taught for a term at the Asian Institute of Technology, Bangkok, in the summer
no. 1, pp. 62–65, Mar. 1988. of 1999. He holds six patents and has published more than 40 papers in
[13] R. Cordella, “A heuristic thermistor model,” IEEE Trans. Circuits Syst., international journals and presented more than 60 papers at various confer-
vol. CAS-29, no. 4, pp. 272–276, Apr. 1982. ences. His teaching and research interests are in the areas of measurements,
[14] D. Ghosh and D. Patranabis, “Software based linearisation of thermis- instrumentation, and signal processing.
tor type nonlinearity,” Proc. Inst. Elect. Eng. G—Circuits Devices Syst.,
vol. 139, no. 3, pp. 339–342, Jun. 1992.
[15] G. Zatorre-Navarro, N. Medrano-Marques, and S. Celma-Pueyo, “Analy- P. Sankaran was born in Pudukkottai,
sis and simulation of a mixed-mode neuron architecture for sensor con- Tamizhnadu, India, on September 2, 1939. He
ditioning,” IEEE Trans. Neural Netw., vol. 17, no. 5, pp. 1332–1335, received the B.E. degree in electrical engineering
Sep. 2006. and the M.Sc. (Engg.) degree in electrical machine
[16] A. Abudhahir and S. Baskar, “An evolutionary optimized nonlinear func- design from the University of Madras, Madras,
tion to improve the linearity of transducer characteristics,” Meas. Sci. India, in 1960 and 1961, respectively, and the Ph.D.
Technol., vol. 19, no. 4, pp. 72–76, Apr. 2008. degree in electrical engineering from the Indian
[17] N. M. Mohan, V. J. Kumar, P. Sankaran, G. Venmathi, and M. Vani, Institute of Technology (I.I.T.) Madras, in 1972.
“Linearising dual slope digital converter suitable for a thermistor,” in He was a Senior Fellow of the Technical Teachers’
Proc. IEEE I 2 MTC, Austin, TX, 2010, pp. 131–135. Training Program of the Government of India from
[18] Texas Instrum., “Data Sheet - LOG112,” Precision Logarithmic 1961 to 1963. In July 1963, he joined the Electrical
and Log Ratio Amplifiers, Dallas, TX2010. [Online]. Available: Engineering Department of I.I.T. Madras, where he retired as a Professor.
http://tinyurl.com/mxyqp5 He was a Professor of Engineering Technology at Multimedia University,
[19] Vishay Electron., “Data Sheet - NTCS0603E3223MT,” SMD0603- Malaysia, between 2000 and 2002. During the periods 1967–69, 1974–75,
Glass Protected NTC Thermistors, Malvern, PA. [Online]. Available: 1981, and 1989–90, he was in Germany at the Technical Universities of
http://tinyurl.com/o7jcop Stuttgart and Braunschweig as a DAAD Fellow and as a Humboldt Fellow. His
[20] Nagman Instrum. Electron., “Data Sheet - MP40R,” Sub-Zero and teaching and research interests are in the areas of electrical networks, machines,
Medium Temperature Calibrator, Chennai, India. [Online]. Available: and measurements and instrumentation.
http://tinyurl.com/najrjd
[21] Nagman Instrum. Electron., “Data Sheet - MTC650,” Micropro-
cessor Based Universal Temperature Calibrator, Chennai, India. [Online].
Available: http://tinyurl.com/q3985s
[22] National Instrum., “USB-6251 - User Manual,” 16-Bit, 8-Channel,
1.25 MSa/s Data Acquisition Device, Schaumburg, IL. [Online].
Available: http://tinyurl.com/rd2hqq

N. Madhu Mohan (S’99–M’10) was born in

Coimbatore, India, on March 21, 1970. He received
his Bachelor’s degree in electronics and communi-
cation engineering from the University of Calicut,
Kerala, India, in 1991. He received his Master of
Science (By Research) and Ph.D. degrees from
the Indian Institute of Technology Madras, Madras,
India in 2003 and 2010, respectively.
He is currently an Assistant Professor at the
Amrita School of Engineering, Coimbatore, India.
His interests are in the area of measurements, bio-
medical instrumentation, and virtual instrumentation.