Theory Exam Question Booklet

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NTA LEVEL 5 END SEMESTER EXAMINATIONS – Month: JULY Year: 2025

Time: 2Hrs30Min Max. Marks: 100 No. of Pages used:
Module Code: ECT 05206 Module Name: INDUSTRIAL ELECTRONICS

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PART – A (2 Marks)

No Questions Answer key with marking scheme

1 Differentiate between SCS and SCR. SCS: Works like an SCR but can be turned off using a
gate signal.

(2 marks)
2 What do you understand about A switching diode is an electronic component
switching diode. commonly used to control the flow of electrical current
(2 marks)
3 Draw diagram for Single-Phase Full
Converters.

(2 mark)
4 List application of dual converter. Applications:
 Four-quadrant DC motor drives
 Reversible power supplies
  Industrial automation
(2mark)

5 What is logic gates -Logic gates are electronic devices that perform basic
logical functions and are the building blocks of digital
circuits.
(2 mark)

6 Draw the logic symbol and construct the 3-input OR gate:

truth table for the three input OR gate.

INPUT OUTPUT
A B C A+B+C
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1

- (2 mark)
7 Why NAND and NOR gates known as In Boolean Algebra, the NAND and NOR gates are called
Universal gates? universal gates because any digital circuit can be
implemented by using any one of these two i.e. any logic
gate can be created using NAND or NOR gates only.
Every logic gate has a representation symbol
(2 markS )
8 State Demorgans’ theorem. First law
“The complement of the sum of variables is equal to the
products of their variables.
Second law
The complement product of variables is equal to the sum
of their components.

(2 mark)
9 Define register. When do we use shift Register is a group of flip flops used to store binary
register? data.
Shift register is used to shifting the data from one flip
flop to another
 (2marks)

10 Draw the logic diagram for master slave

flip flop.

(2marks)
11 What do understand by term toggling In T or JK flip flop, if the input is direct connected to
used in flip flop. the logic high level (+5V), the flip flop is toggled at the
negative edge of each clock input. The process is called
toggling.
(2 marks)
12 What is parity generator -is a combinational logic circuit that generate the parity
bit in the transmitter
(2marks)
13 What is DAC? - Digital-to-Analog Converter, a device (usually a
single chip) that converts digital data into analog
signals.

(2mark)
14 Draw the block diagram for ADC.

(2marks )
15 There are three kinds of PLDs based There are three kinds of PLDs based on the type of
on the type of array . array , which has programmable feature.
 Programmable Read Only Memory
 Programmable Array Logic
 Programmable Logic Array

( 2marks)
16 What is digital signal. Digital Signals – have only two states. For digital
computers, we refer to binary states, 0 and 1. “1” can be
on, “0” can be off.
Examples:
⚫ Light switch can be either on or off
⚫ Door to a room is either open or closed

(2marks)
17 What is IC555? The 555 is a monolithic timing circuit that can
produce accurate & highly stable time delays or
oscillation.
(2marks)

18 Define A Voltage Controlled Oscillator A Voltage Controlled Oscillator is an Oscillator

circuit in which the frequency of oscillations can be
controlled by an externally applied voltage.
(2marks)
19 Define A voltage regulator - A voltage regulator is a voltage stabilizer that is
designed to automatically stabilize a constant voltage
level.
(2marks)
20 Timer basically operates in one of two The timer basically operates in one of two modes:
modes name them. either
(i) Monostable (one - shot) multivibrator or
(ii) (ii) Astable (free running) multivibrator

(2marks)

PART – B (4 Marks)

No Questions Answer key with marking scheme

21 Give short notes on MOSFET. A MOSFET is a voltage-controlled switch with three
terminals: Gate (G), Drain (D), and Source (S).
Working Principle:
• A voltage applied at the Gate ( V GS) controls the
 conduction between the Drain and Source.
 ON State: When V GS exceeds the threshold voltage (
V th), the MOSFET conducts current.
 OFF State: When V GS is below V th , the MOSFET
does not conduct.
Types of MOSFETs:
 n-channel MOSFET: Requires a positive V GS to turn
ON.
 p-channel MOSFET: Requires a negative V GS to
turn ON.

(4 marks)

22 Mention applications of PWM: i) Power converters (buck, boost, inverters)

ii) Motor speed control (DC motors, servo motors)
iii) LED dimming control
iv) Audio signal processing

( 4marks)
23 Briefly explain application of dc to dc APPLICATION OF DC TO DC CONVERTER
converter. 1. Renewable energy applications: The DC/DC
converter topologies employed for renewable energy
applications need to draw continuous and smooth input
current so ripple reduction can be achieved. It should
also be able to integrate with different types of power
sources. Non-isolated interleaved high voltage gain
topologies are typically employed for interfacing
renewables and microgrids [4].
2. Medical devices: Isolated DC/DC converters are
crucial in applications where safety is a critical
aspect. This is essential for separating the output from
dangerous voltages on the input side. However, non-
isolated converter topologies can be employed for
applications like the power supply of an x-ray system.
3. Vehicles: In the case of vehicles, the main DC/DC
converter changes power from the onboard high
voltage battery into lower DC voltages used to power
lights, wipers, and window controls [5]. This is true
for both electric vehicles and hybrid electric vehicles.
Isolation is crucial in cases where separation of
 control systems is essential from high voltage
domains. Buck-boost converters are utilized for step-
up or step-down, and charge-pump converters are used
for voltage inversion.
4. Smart lighting: Several lighting applications require
LED backlight driver solutions that possess
high efficiency, direct current control, voltage
protection, PWM-based control, and simple design.
The DC/DC converter topologies that serve as
effective drivers include linear regulators, charge
pumps, and other conventional switching converters.

( 4marks)
24 Give notes on general Working Semiconductor switching devices operate based on the
principle of controlling current and voltage using
Principles of Semiconductor Switching
semiconductor materials. Their operation is categorized into
Devices? two main states:
i. ON State (Conducting Mode)
• The device allows current to flow when a
triggering signal (gate or base signal) is
applied.
• Example: In an SCR, a small gate pulse enables
the device to conduct fully.
ii. OFF State (Non-Conducting Mode)
• The device blocks current flow when the
control signal is removed.
• Example: A MOSFET stops conducting when
the gate-source voltage is below the threshold.

iii. Switching Speed

 The ability of the device to transition between ON
and OFF states rapidly is crucial for efficiency.
 MOSFETs are faster compared to IGBTs but are
limited in power-handling capacity.
iv. Losses in Switching
 Conduction Losses – When the device is ON.
 Switching Losses – During the transition between
ON and OFF states.

(4marks)
25 What are the theorem and postulates Postulates
of boolean algebra A+0=A
A+1=A
A+ A=¿1
A.0=0
A.1=A
A. A = 0
Theorem
 A+A=A
A.A=A
A( A+ AB ¿=AB
A+AB=A
A+ A B=A+B
(4marks)
26 Give short notes about decoder A decoder is similar to Demultiplexers with one exception
that these is an data input.
It contains less no. of input lines and more number of
output lines.
Hence n inputs is converted into 2n❑output.

(4 mark)
27 Write short notes on adder with the
help of logic diagram.
 (4marks)
28 Briefly explain about 3 to decoder 3 to 8 Decoder
with truth table and logic diagram if  A 3 to 8 decoder has three inputs (A, B, C) and eight
necessary. outputs (D0 to D7).
 Based on the 3 inputs one of the eight outputs is
selected.
 The truth table for 3 to 8 decoder is shown in the
below table.
 From the truth table, it is seen that only one of eight
outputs (D0 to D7) is selected based on three select
inputs.
 From the truth table, the logic expressions for outputs
can be written as follows:
Truth table of 3 to 8 decoder:
A B C D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

(4marks)
29 What are differences between Ring Difference between Ring Counter & Johnson Counter?
Counter & Johnson Counter? Ring Counter:
This counter is developed by modifying a shift register. The
 true output of the last flip-flop is fed back directly to the data
input of the first flip-flop, thus generating a sequence of
pulses. For example, for a D Flip-Flop shift register, the Q
output of the last flip-flop is connected to the D input of the
first flip-flop. These counters are used in digital system to
generate control pulses.
Johnson Counter
Johnson counter is a reverse of Ring Counter . In other
words, feedback from the last flip-flop is fed inversely to the
data input of the first flip-flop. For example, for a D Flip-
Flop shift register, the ~Q output of the last flip-flop is fed to
the D input of the first flip-flop. These can be used as Divide
by n counters as well.

(4
marks)
30 Mention four (4) application of i. Used in time
counter ii. Used in digital clock
iii. Used in object counter
iv. Used for frequency counter
v. Used to measure time period
vi. Used for frequency dividers.

(1 mark each)
31 . By using diagram and truth table T-flip flop contain two input ( T and c/k) and two output (Q
explain T-flip flop and Qn)
This is also called as toggle flip flop or divide by 2 counter
Working : no change T=0, Qn= Qn−1
Toggle T=1, Qn= Qn−1)

(4 marks)
32 List 4 application of shift register
 microprocessor
ii. Used to store binary data
iii. Used as data format changer
iv. Used for temporary data storage and bit manipulation
v. Used to introduce time delay
vi. Used to convert serial data into parallel data
vii. Used in sequence generator
(1 mark each)
33 Find output voltage and
current for a binary weighted resistor
DAC of 4 bits where :
R = 10 k Ohms, R f = 5 k Ohms and V R
= 10 Volts. Applied binary word is
1101.

(4 marks)
34 Write disadvantage of Binary  Disadvantages
Weighted Resistor.  Requires large range of resistors
(2000:1 for 12-bit DAC)
with necessary high precision for low
resistors.
 Also for smaller values of resistors, the
loading effect may occur
 Requires low switch resistances in
transistors
 Can be expensive. Therefore, usually
limited to 8-bit
(4 marks)
35 Given Vref=5V, Vs=3.127V, find a 4-
bits ADC.

(4marks)
36 With the help of graph write short  There are 3 sampling methods:
notes on 3 sampling methods.  Ideal - an impulse at each sampling instant.
 Natural - a pulse of short width with varying
amplitude.
 Flattop - sample and hold, like natural
but with single amplitude value.
 The process is referred to as pulse amplitude
modulation PAM and the outcome is a signal with
analog (non integer) values

(4 marks)
37 Write (4) Limitations of Linear Limitations of Linear Voltage Regulator s
Voltage Regulators 1. The required input step down transformer is bulky
and expensive
2. Due to low line frequency (50Hz), large values of
filter capacitors are required
3. The efficiency is very low
4. Input must be greater than the output voltage
5. As the is the difference between input and output
voltage, more is the power dissipation
6. 6. For higher input voltages, efficiency decreases
 (4 marks)

38 Briefly explain three classification of 1. Astable Multivibrator (free running multivibrator): Has two
Multivibrator states which are both unstable states (quasi-stable state)
2. Monostable multivibrators (One-shot multivibrators): Has
one stable state and one unstable state
3. Bistable multivibrators: (Both two states are stable states)

(4marks)
39 Name four (4)the important The important features of the 555 timer are :
features of the 555 timer (i) It operates on +4.5v to +18 v supply voltages
(ii) (ii) It has an adjustable duty cycle
(iii) (iii) Timing is from microseconds to hours
(iv) (iv) It has a current o/p
(v) (v) It has two basic operating modes: Monostable and
Astable
(vi) (vi) Sinking or sourcing 200 mA of load current.
(vii) (vii) It has very high temperature stability as it is designed
to operate in the temperature range of -55 ° C to 125° C.
(viii) (viii)The output of a 555 timer can drive a transistor-
transistor logic (TTL) due to its high current output.
(ix) (ix) The maximum power dissipation per package is
600mW

(4marks)
40 IC 555 is the combination of for
The 555 timer combines
different circuit. Name them.

1. A relaxation oscillator,

2. Two comparators,

3. R-S flip-flop,

4. And a discharge transistor.

(4 marks)

PART C (12 Marks)

No Questions Answer key with marking scheme
41 Describe the following terms A MOSFET is a voltage-controlled switch with three
MOSFET, IGBT< SCR and GTO, terminals: Gate (G), Drain (D), and Source (S).
Working Principle:
• A voltage applied at the Gate ( V GS) controls the
conduction between the Drain and Source.
• ON State: When V GS exceeds the threshold voltage (
V th ), the MOSFET conducts current.
• OFF State: When V GS is below V th, the MOSFET does
not conduct.
Types of MOSFETs:
• n-channel MOSFET: Requires a positive V GS to turn
ON.
• p-channel MOSFET: Requires a negative V GS to turn
ON.
• An IGBT is a hybrid of BJT and MOSFET, designed
for high-power applications. It has three terminals:
Gate, Collector, and Emitter.
Working Principle:
• ON State: A voltage applied at the Gate ( V ¿) above
the threshold allows current to flow from Collector to
Emitter.
• OFF State: When V ¿ is removed, it stops conduction.
• Combines MOSFET's high input impedance (low
power driving) and BJT’s high current-carrying
capacity (low conduction losses).
• A Thyristor (SCR) is a four-layer (PNPN) device that
acts as a latching switch, remaining ON after being
triggered.
• Working Principle:
• ON State: A small Gate current triggers conduction
between Anode and Cathode.
OFF State: The device turns OFF only when the anode
current drops below a holding current value

A GTO is a thyristor that can be turned OFF using a negative

Gate current.
Working Principle:
• Similar to an SCR, but a negative gate pulse forces it
to turn OFF.
 • Used in high-power applications where fast switching
is needed.

(12 marks)
42 Explain Types of Dual Converters. i.

−R f
Gain= =−4.7
R1
Vo (Peak-to-peak) = Gain x V i n = 4.7 x 2=9.4 V

But a.c. voltmeter measures r.m.s. value

V o (Peak−¿− peak ) 9.4
V o (Peak)= = =4.7V
2 2
V o (Peak ) 4.7
V o (r .m . s) = = =3.3234 V .
√2 √2
i. Advantages of IC
a. Miniaturization and hence increased
density
b. Cost reduction due to batch processing i.e. Mass
production
c. Highly reliable due to elimination of soldered joints
d. Improved functional performance (since it is possible
to fabricate even complex circuits for better
characteristics)
e. Increased operating speeds Low power consumption
Less weight
f. Low supply voltage Simple to use
g. . Versatile

. (12 marks)
43 Explain about subtractor with  This is also called difference amplifier
diagram and derivations.  Differential amplifier is a circuit that amplifies the
difference between two applied input signals.
 Consider the diagram of subtractor in the next slide;
The differential voltage at the input terminals of
the Op-Amp is zero; hence “a” and “b” are at the
same potential marked ‘V3’.
. Applying KCL at nodes ‘a’ and ‘b’

 Since the RHS of the two equations are equal, then

the LHS of the equations must be equal too.
 (12 marks)

44 Write notes about a Block Diagram Block Diagram Representation of Opamp

Representation of Opamp It consists of four cascaded blocks:
1 s t Input Stage 2 n d Intermediate Stage 3 r d Level Shifting Stage
4 t h Output Stage
.

(4marks)

It consists of four cascaded blocks:

1 s t Input Stage:
 The function of differential amplifier is to amplify
the difference between the two input signals
 Requires two input terminals
 This stage requires high input impedance to avoid
loading on the sources.
 Requires low output impedance
2 n d Intermediate Stage
 The output of the input stage drives the next stage
which is intermediate stage.
 Since the overall gain required for the op-amp is
very high then the input stage alone
cannot achieve this, so the main function of the
intermediate stage is to provide additional
voltage gain required.
 Practically this stage is not a single amplifier but
the chain of cascaded amplifiers.
3 r d Level Shifting Stage
 Since the op-amp also amplifies DC signals, so stage
by stage the DC level increases above the ground
 potential.
 This high DC voltage level may drive the transistors
into saturation which may further cause the
distortion in the output due to clipping
 This may in turn limit the maximum AC output
voltage swing without any distortion
Hence before the output stage, it is necessary to bring such
high DC voltage level to 0volts with respect to ground
3 r d Level Shifting Stage
 Level shifter stage brings the DC level down to ground
potential, when no signal is applied at the input
terminals.
 The buffer is usually an emitter follower whose input
impedance is very high, this prevents loading of
the high gain stage.

4 t h Output Stage
 The basic requirements of an output stage are low
output impedance, large a.c. output voltage swing and
high current sourcing and sinking capability.
 The amplifier which meets these requirements is Push-
pull complementary amplifier, hence it is used as an
output stage.
 This stage increases the output voltage swing.
 (2marks each block)
45 i. Convert the following Solution
decimals 151, 999, 93 into i. For 151, divide them by 2 (3 marks)
binary.
151 75 37 18 9 4 2
ii. Convert the following
75 37 18 9 4 2 1
decimal numbers 3509,
1021 into hexadecimal. remin 1 1 1 0 1 0 0

iii. Convert 1101.1 binary der

and (9 B 2.1 A) H into Ans. (11101001)2

decimal equivalent for

iv. Convert decimal 214 to 999 499 249 124 62 31 15 7 3

its octal equivalent 499 249 124 62 31 15 7 3 1

v. Convert (475.25)8 and to 1 1 1 0 0 1 1 1 1
its decimal equivalent Ans. (1110011111)2
vi. Convert the year you 93 46 23 11 5 2
have born into octal and 46 23 11 5 2 1
hexadecimal equivalent.. 1 0 1 1 1 0
Ans. (1011101)2
ii. For 3509 to hexadecimal (2 marks)

Divide by 16
3509 219 13
219 13 0
REMINDER 5 11 13
5- LSD
11-B
13-D, MSD
ANS: (DB 5)16
 FOR 1021
1021 62 3
63 3 0
REMINDER 13 15 3
D F LSD
ANS: (3 FD)16
iii. For 1101.1 ( 2 marks)

N= 1x 23 + 1x 22 + 0x 21 + 1x 20 + 1x 2−1
=8+4+ 1+0.5
= : 13.510
For (9 B 2.1 A) H
N=9x 162 + B(11)x 161 + 2x 160 + 1x 16−1 + A(10)x 16−2
=2304+176+2+0.0625+0.0390625
= 2482.110
iv. Given 214 ( 1 marks)

214 26 3
Divide by 8 26 3 0
reminder 6 2 3
6238

v. Given475.25 8 ( 1 marks)

N= 4x 82 + 7x 81 + 5x 8 0 + 2x 8−1 + 5x 8−2
=128+ 56+5+0.25+0.078125
= 317.32812510 .
(3 marks)
46 Use Boolean algebra show that:
i. A B+BC+ A BC = A +BC
ii. D ¿+B)+ B (C+AD)=D+BC
iii. ¿A+B)(A+C)=A+BC
iv. A ¿B+C(( A . B+ AC ) ]=A.B
v. AB+ AC +B C=AB+ BC
vi. BC +AC
+AB+BCD=BC+AC
(2 marks each)
47 Using karnaugh map simplification
simplify the following expression
i. Y= A B + A B +AB
ii. Y = A BC + A BC
iii. Y= A BC + A BC+
ABC + A BC
iv. Y= A BC + ABC

(3 marks each)
48 Write short notes on Multiplexer, Multiplexers
De-multiplexer, encoder and Multiplexer is a special type of combinational circuit.
decoder. There are n-data inputs, one output and m select inputs
with 2m = n.
It is a digital circuit which selects one of the n data inputs
and routes it to the output.
The selection of one of the n inputs is done by the
selected inputs.
Depending on the digital code applied at the selected
inputs, one out of n data sources is selected and
transmitted to the single output Y. E is called the strobe
or enable input which is useful for the cascading.

Demultiplexers
A demultiplexer performs the reverse operation of a
multiplexer i.e. it receives one input and distributes it over
several outputs.
It has only one input, n outputs, m select input. At a time only
one output line is selected by the select lines and the input is
transmitted to the selected output line.

Decoders :
 The decoder is called n-to-m-line decoder, where m≤2n
 the decoder is also used in conjunction with other code
converters such as a BCD-to-seven_segment decoder.
 3-to-8 line decoder: For each possible input
combination, there are seven outputs that are equal to
0 and only one that is equal to 1.

Encoder
 An encoder is a combinational logic circuit that essentially
performs a “reverse” of decoder functions.
 An encoder accepts an active level on one of its inputs,
 representing digit, such as a decimal or octal digits, and
converts it to a coded output such as BCD or binary

(3 marks each)
49 Give short notes about SR flip flop SR flip flop
and JK flip flop. -it is a set/reset flip flop
-it contains two input (S and R) and two output (Q an Q ).
-construction is made by NAND gate and NOR gate.
-working: no change condition S=R=0, Qn=0
Reset condition S=0, R=1, , Qn=0
Set condition S=1, R=0, , Qn=1
Forbidden condition S=R=1, , Qn=X

(6 marks)
JK flip flop
-it is a defined SR flip flop
-it have three input (J,K, C/K) and two output
-working: Reset J=0, K=1, Qn=0
Set J=1, K=0, Qn=1
Toggle J=1, K=1, Qn=1
 (6 marks)
50 Explain two types of triggered flip There are two types of triggered flip flop
flop and JK master slave flip flop. i. Level triggered flip flop
ii. Edge triggered flip flop

Level triggered flip flop: in clocked SR flip flop,the clock

triggeres flip flop when the clock pulse goes high, so this is
called level triggered flip flop.
There are of two types →high level
→low level
Edge triggered flip flop : the basic flip flop are level
triggered because the output respond to input as long as the
clock signal is present.
The flip which produces the original output at the falling edge
of the clock pulse is called edge triggered flip flop .
They are of two types →positive edge triggered
→negative edge triggered
(6marks)
JK master slave flip flop:
…This contain three input and two output (Q and Q )
…It is the combinations of two JK flip flop
…One is a master and other is a slave
…The output of master is input of the slave
Working: like of JK flip flop no change.
Reset J=0, K=1, Qn=0
Set J=1, K=0, Qn=1
Toggle J=1, K=1, Qn=1
 (6marks)
51 Explain types of shift register TYPES OF SHIFT REGISTER
i. SERIAL IN SERIAL OUT

Here the read and write operation are in serial form.

(3 marks)
ii. SERIAL IN PARALLEL OUT

In this type write operation are in serial form while read

operation aren in parallel form.

(3 marks)
iii. PARALLEL IN PARALLEL OUT

Here both read and write are in parallel form

 (3 marks)
iv. PARALLEL IN SERIAL OUT

In this write operation are in parallel form and read are in

serial form.

(3 marks)
52 a. Briefly explain about Synchronous counter is a parallel counter, where the clock
4-bit synchronous pulse is applied to all flip flop simultaneously.
counter. -hence all flip flops are operated in time. This setting time is
b. Write four differences simply equal to the delay time of single flip flop.
between synchronous -the speed of operation is equal to speed of single flip flop,
counter and hence speed is high and constant.
asynchronous -it is an up counter and counts in upward direction.
counter? -the J and K inputs of all flip flops are connected to +vcc
such that all flip flops will toggle at the negative edge of
every clock pulse.
-the triggering is done by system clock.
(4 marks
Difference between synchronous and asynchronous counter
S. SYNCHRONOUS ASYNCHRONOUS
no COUNTER COUNTER
 1. System clock pulse is System clock pulse is
applied to first FF only applied to all FFS
2. Except the first flip flop All flip flops are triggered
remaining are triggered by by the system clock pulse.
output of previous flip flop

3. The flip flops are triggered All flip flop are triggered
one by one simultaneously
4. Propagation delay is high Propagation delay is low
5. Propagation delay is not Propagation delay is
uniform uniform

(12 marks)
53 Find digital value V i n of 8-bit ADC • MSB è LSB (generation of bits)
with V i n = 7.65V and V full scale=10v. • Average high/low limits
• Compare to V i n
• V i n > Average è MSB = 1
• V i n < Average è MSB = 0

1
If the bit is 0 in the next step change the Full scale, if the
bit is 1 change the added value
• Bit 6
• (V f u l l s c a l e +5)/2 = 7.5
• 7.65 > 7.5 è Bit 6 = 1
1 1
• Bit 5
• (V f u l l s c a l e +7.5)/2 = 8.75
• 7.65 < 8.75 è Bit 5 = 0
1 1 0
• Bit 4
• (8.75+7.5)/2 = 8.125
• 7.65 < 8.125 è Bit 4 = 0
1 1 0 0
 • Bit 3
• (8.125+7.5)/2 = 7.8125
• 7.65 < 7.8125 è Bit 3 = 0
1 1 0 0 0
• Bit 2
• (7.8125+7.5)/2 = 7.65625
• 7.65 < 7.65625 è Bit 2 = 0
1 1 0 0 0 0
• Bit 1
• (7.65625+7.5)/2 = 7.578125
• 7.65 > 7.578125 è Bit 1 = 1
1 1 0 0 0 0 1
• Bit 0
• (7.65625+7.578125)/2 =7.6171875
• 7.65 > 7.6171875 è Bit 0 = 1
1 1 0 0 0 0 1 1

(12 marks)

54  Referring to the circuit as shown, the highest value

resistor (150KΩ) is a digital input resistor. The
smallest bit (least significant bit), and the values of
other resistor are

Referring to the circuit as shown,

the highest value resistor (150KΩ)
is a digital input resistor. Find the
gain and output voltage for 16-bit
of this circuit. And draw the truth If binary input is 0001
table. R 1 =150K Ω , R f =20K Ω
Rf 20 KΩ
Voltage gain( A v) = = =0.1333
R 1 150 KΩ
V out = V ref x A v= 3V x 0.1333
=0.4V
 Simply that we can see the resulting output is shown in
the table below

(12 marks)
55 Explain the quantization step of Quantization
ADC.  Sampling results in a series of pulses of varying
amplitude values ranging between two limits: a min
and a max.
 The amplitude values are infinite between the two
limits.
 We need to map the infinite amplitude values onto a
 finite set of known values.
 This is achieved by dividing the distance between min
and max into L zones, each of height D.
D = (max - min)/L
 The midpoint of each zone is assigned a value from 0
to L-1 (resulting in L values)
 Each sample falling in a zone is then approximated to
the value of the midpoint.
Quantization Zones
 Assume we have a voltage signal
with amplitudes V m i n = -20V and V m a x =+20V.
 We want to use L=8 quantization levels.
 Zone width D = (20 - -20)/8 = 5
 The 8 zones are: -20 to -15, -15 to -10, -10 to -
5, -5 to 0, 0 to +5, +5 to +10, +10 to +15, +15
to +20
 The midpoints are: -17.5, -12.5, -7.5, -2.5, 2.5,
7.5, 12.5, 17.5
Assigning Codes to Zones
 Each zone is then assigned a binary code.
 The number of bits required to encode the zones , or
the number of bits per sample as it is commonly
referred to, is obtained as follows:
n b = log 2 L
 Given our example, n b = 3
 The 8 zone (or level) codes are
therefore: 000, 001, 010, 011, 100, 101,
110, and 111
 Assigning codes to zones:
 000 will refer to zone -20 to -15
 001 to zone -15 to -10, etc.
 (12 markS)
56 a. The digital input for a 4-bit a.
DAC is (0110)2 calculate the
final output voltage.
b. Find the step size and analogy
output for 4-bit R-2R ladder
DAC when input is 1000 and
1111. (Assume V ref = +5V.

b.
 (6 marks each)
57 Explain Pin four Configuration of a Pin Configuration ▪ The 555 Timer IC is available as an
timer and draw a Timer pin digram. . 8-pin metal can, an 8-pin mini DIP (dual-in-package) or a
14-pin DIP. The pin configuration is shown in the figures

Pin 1: Grounded Terminal

➢ All the voltages are measured with respect to the
Ground terminal.
Pin 2: Trigger Terminal
➢ The trigger pin is used to feed the trigger input
then the 555 IC is set up as a monostable
multivibrator. This pin is an inverting input of a
comparator and is responsible for the transition of
flip-flop from set to reset. The output of the timer
depends on the amplitude of the external trigger
pulse applied to this pin.
Pin 3: Output Terminal:
➢ Here is where the output of the timer is taken from.
➢ The complementary signal output (Q’) of the flipflop
goes to pin 3 which is the output.

(12 marks)
58 Draw an IC723 pin diagram and
name all pins.

(12 marks)

59 Give out six (6) features of IC723 Features of IC 723

1. It works as both positive and negative voltage
regulators with an output voltage ranging from 2 V to
37 V.
2. It can be used at load currents greater than 150mA
with use of suitable NPN or PNP external pass
transistor.
3. Input voltage 40V max.
4. Input and output short-circuit protection is provided.
5. Wide variety of applications of series, shunt, switching
regulators.
6. Low temperature drift and high ripple rejection.
7. Small size, lower cost.
8. Relative easy with power supply can be designed.
9. It has good line and load regulation.
(2 marks each)
60 Explain types of Voltage regulators Types of Voltage regulators 2. Shunt voltage regulator ▪
Control element in shunt with the loa

There are basically two kinds of IC voltage regulators: ▪

Multipin type, e.g. LM723C ▪ 3-pin type, e.g. 78/79XX,
LM317
➢ Multipin regulators are less popular but they provide
the greatest flexibility and produce the highest quality
voltage regulation.
➢ 3-pin types make regulator circuit design simple.
(6 marks)
1. Series voltage regulator

Control element in series with the load

(6 marks)
 Descriptions of the major categories in the Instructional objectives Illustrative verbs for
cognitive domain stating specific learning
outcomes
Defines, describes, and
Knowledge. Knowledge is defined as the
Knows common terms, specific identifies, labels, lists,
remembrance of previously learned material. This
facts, methods and procedures, matches, names, outlines,
may involve the recall of a wide range of materials
basic concepts and principles. reproduces, selects,
from specific facts to complete theories.
states.
Understands facts and principles,
Comprehension. Comprehension is defined as the Converts, defends,
interprets verbal material,
ability to grasp the meaning of material. This may distinguishes, estimates,
Interprets charts and graphs, and
be shown by translating material from one form to explains, extends,
Translates verbal material to
another (words of numbers), by interpreting generalizes, gives
Mathematical formulae,
material (explaining or summarizing), and by examples, infers,
Estimates consequences implied
estimating future trends (predicting consequences paraphrases, predicts,
in data, Justifies methods and
or effects). rewrites, summarizes
procedures.
Application. Application refers to the ability to Applies principles to new Changes, computes,
use learned material in new and concrete situations, Applies theories to demonstrates, discovers,
situations. This may include the application of practical situations, solves manipulates, modifies,
such things as rules, methods, concepts, mathematical problems, operates, predicts,
principles, laws and theories. Learning outcomes constructs charts and graphs and prepares, produces,
in this area require a higher level of understanding demonstrates correct usage of a relates, shows, solves,
than those under comprehension. procedure. uses

Question Categorization* NTA LEVEL 5

Knowledge Type - 35% - 126Marks/360Marks

Comprehension Type - 35% - 126Marks/360Marks
Application Type - 30% - 108Marks/360Marks
Coverage of the syllabus
PART –A (2 Marks) PART – B (4 Marks) PART – C (12 Marks)
Questio
Question Question
n
No No
No
i ii iii
1–4 21 – 24 41 – 44
i ii iii
i ii iii
5–8 25– 28 45 – 48
i ii iii
i ii iii
9 – 12 29 – 32 49 – 52
i ii iii

13-16 33-36 53-56

17-20 37-40 57-60