Input/Output Data Transfer

Data from Peripherals have to reach Memory so that the CPU can use it. Similarly, the processed output
has to reach peripherals like printer, internet devices, DISK, etc.
Thus, I/O data transfer is about how the three subsystems i.e. CPU, Memory and I/O Controller, are
involved in achieving the data exchange with peripherals. The word Data Exchange means successful
Data in/Data Out with necessary handshake and coordination.
Data Exchange with a peripheral involves few steps and not straight forward as devices are mostly
electromechanical and/or operate at a different speed than CPU and Memory.
 The device to be initiated and checked for status whether it is ready for Data Exchange.
 The data transfer has to happen at the acceptable capsule and speed of the device using the applicable
protocol.
 This may happen in more than one sequence, as necessitated.
 If the device status is an Error status, it is to be suitably handled.
I/O Controller's role is to ensure seamless data exchange by ensuring the following (Please refer to
diagram 20.2)
 Processor/Memory Communication
 Device Communication
 Control timing and Status processing – Coordination of the data traffic between CPU, Memory and Io
devices
 Data Buffering – To manage the data transfer speed mismatch
 Error management ( Transmission errors are corrected other status errors are communicated)
I/O Data Transfer Techniques
Mode of Transfer:
The binary information that is received from an external device is usually stored in the memory unit.
The information that is transferred from the CPU to the external device is originated from the memory
unit. CPU merely processes the information but the source and target is always the memory unit. Data
transfer between CPU and the I/O devices may be done in different modes. Data transfer to and from
the peripherals may be done in any of the three possible ways
 Programmed I/O
 Interrupt driven I/O
 Direct Memory Access

Figure 21.1 I/O Data exchange methods and features

Programmed I/O
A program controls the I/O Operation; hence CPU is fully involved. CPU Monitors the status of the
device and the I/O data transfer. This keeps the CPU hooked until the I/O operation is completed for the
desired number of bytes. In the case of READ from I/O device, the final destination for Data is Memory.
CPU writes the data collected from the device into Memory. It happens vice versa in the case of WRITE
onto the device.
Programmed I/O is used for tiny data transfer i.e. few bytes. Before an actual Data transfer to a device,
selecting, readying the device and verifying the status are to be done. Ex: Selecting the Printer and
initialization before printing. This is shown by the decision box loop in figure 20.2.
In the diagram, at each step, the direction of information flow between the subsystems is marked to
reinforce your understanding.
The CPU loop during status check is eliminated in the Interrupt Driven I/O Operation.
 Figure 21.2 Programmed
I/O and Interrupt Driven I/O
Interrupt Driven I/O data transfer
Since in the above case we saw the CPU is kept busy unnecessarily. This situation can very well be
avoided by using an interrupt driven method for data transfer. By using interrupt facility and special
commands to inform the interface to issue an interrupt request signal whenever data is available from
any device. In the meantime the CPU can proceed for any other program execution. The interface
meanwhile keeps monitoring the device. Whenever it is determined that the device is ready for data
transfer it initiates an interrupt request signal to the computer. Upon detection of an external interrupt
signal the CPU stops momentarily the task that it was already performing, branches to the service
program to process the I/O transfer, and then return to the task it was originally performing.
 The I/O transfer rate is limited by the speed with which the processor can test and service a device.
 The processor is tied up in managing an I/O transfer; a number of instructions must be executed for
each I/O transfer.
 Terms:
o Hardware Interrupts: Interrupts present in the hardware pins.
o Software Interrupts: These are the instructions used in the program whenever the required functionality
is needed.
o Vectored interrupts: These interrupts are associated with the static vector address.
o Non-vectored interrupts: These interrupts are associated with the dynamic vector address.
o Maskable Interrupts: These interrupts can be enabled or disabled explicitly.
o Non-maskable interrupts: These are always in the enabled state. we cannot disable them.
o External interrupts: Generated by external devices such as I/O.
o Internal interrupts: These devices are generated by the internal components of the processor such as
power failure, error instruction, temperature sensor, etc.
o Synchronous interrupts: These interrupts are controlled by the fixed time interval. All the interval
interrupts are called as synchronous interrupts.
o Asynchronous interrupts: These are initiated based on the feedback of previous instructions. All the
external interrupts are called as asynchronous interrupts.

The steps involved in I/O data transfer are the same but for a change in freeing the CPU until the device is
ready for data transfer. Refer to figure 20.2.
 The CPU initiates the command on the device and takes up other tasks.
 Once the device is ready with data, the I/O controller generates an Interrupt.
 On recognizing the pending Interrupt signal from I/O controller, the CPU temporarily suspends the
ongoing execution, goes in for interrupt service routine and collects the data and stores in memory or vice
versa and then resumes the suspended execution. In this mode also, it is the CPU which interacts with
memory for storing the device data.
Most of the devices are electromechanical and have high latency. The period for which the CPU is freed
is proportional to this. Hence the benefit achieved is reasonable. The interrupt is asynchronous. The I/O
controller waits until the interrupt is serviced by CPU. Thus, what we have achieved is the I/O controller
 is made to wait instead of the CPU. CPU time is more precious. Details of Interrupt servicing will be dealt
with in the next chapter.
Interrupt service routine is also a complex and costly matter involving OS. This method is also feasible
for a small quantum of data transfer. Direct Memory access can resolve the CPU availability in a
hardware environment.
Direct Memory Access (DMA) Data Transfer
3. Interrupt servicing of the device is still accomplished using the software. This may not be fast enough for
a large chunk of data transfer from DISK. Recall that the Virtual memory implementation is supported by
Disk. This involves large data exchange to memory. The software routine is replaced with a specialized
hardware processor, called the Direct Memory Access Controller (DMAC). DMA technique facilitates
I/O data transfer between Main Memory and devices connected to DMAC, Fast data rate devices are
connected to DMAC. The data transfer between a fast storage media such as magnetic disk and memory
unit is limited by the speed of the CPU. Thus we can allow the peripherals directly communicate with
each other using the memory buses, removing the intervention of the CPU. This type of data transfer
technique is known as DMA or direct memory access. During DMA the CPU is idle and it has no
control over the memory buses. The DMA controller takes over the buses to manage the transfer
directly between the I/O devices and the memory unit.
1. Bus grant request time.
2. Transfer the entire block of data at transfer rate of device because the device is usually slow than the
speed at which the data can be transferred to CPU.
3. Release the control of the bus back to CPU So, total time taken to transfer the N bytes = Bus grant
request time + (N) * (memory transfer rate) + Bus release control time.
4. Buffer the byte into the buffer
5. Inform the CPU that the device has 1 byte to transfer (i.e. bus grant request)
6. Transfer the byte (at system bus speed)
7. Release the control of the bus back to CPU.

 The CPU passes necessary information to DMA and goes on with any other work.
 The DMA takes care of data transfer to Memory.
 On completion, DMA generates an Interrupt to inform the CPU of the job done.
Note that the CPU as a boss gives the work and informed of Job done but not involved for doing the job.
It is independently taken care of by DMAC.

The DMA method improvises the interrupt method with optimal efficiency as the data is not routed via
CPU. Thus DMA unburdens CPU.