Lecture #23

ANNOUNCEMENTS
• Quiz #5 will be given at the beginning of class on Thursday (4/17)
– topics to be covered: BJT transient response, MOS band diagrams
– closed book; 5 pages of notes + calculator allowed

OUTLINE
• MOS non-idealities (cont.)
• VT adjustment
• MOSFET structure and operation

Reading: Course Reader Chapter 3.1

(Textbook Chapters 18.3, 17.1-2)

Spring 2003 EE130 Lecture 23, Slide 1

Poly-Si Gate Depletion

• A heavily doped film of polycrystalline silicon (poly-Si)
is typically employed as the gate-electrode material in
modern MOS devices.
NMOS PMOS

N+ poly-Si P+ poly-Si

P-type Si n-type Si

– There are practical limits to the electrically active dopant

concentration (usually less than 1x1020 cm-3)
⇒ The gate must be considered as a semiconductor, rather
than a metal

Spring 2003 EE130 Lecture 23, Slide 2

1
 MOS Band Diagram with Gate Depletion
Si biased to inversion:

Wdm
Ec VG is effectively reduced:
EFS Qinv = Cox (VG − V poly − VT )
qψ B Ev
qVpoly qVG

Ec 2ε SiV poly
W poly =
Ev
qN poly
Wpoly
How can gate depletion
N+ poly-Si gate P-type Si be minimized?

Spring 2003 EE130 Lecture 23, Slide 3

Gate Depletion Effect

Gauss’s Law dictates

Wpoly = ε ox ox / qN poly
tox is effectively increased:
−1 −1
 1 1   t W 
N+ poly-Si C = + =  ox + poly 
C   ε SiO ε Si 
Cpoly
+ + + + + + + +
 ox C poly   2

Cox
- - - - - - - - - ε SiO
N+ = 2

p-type Si tox + (W poly / 3)

ε SiO
Qinv = (VG − VT ) ⋅ 2

tox + (W poly / 3)

Spring 2003 EE130 Lecture 23, Slide 4

2
 Example: GDE
Vox , the voltage across a 2 nm thin oxide, is 1 V. The n+
poly-Si gate active dopant concentration Npoly is 8 ×1019 cm-3
and the Si substrate doping concentration NA is 1017cm-3.
Find (a) Wpoly , (b) Vpoly , and (c) VG .

Solution:
(a) Wpoly = ε ox ox / qN poly = ε oxVox / t ox qN poly
−
3.9 × 8.85 ×10 14 (F/cm) ⋅1 V
= − − −
2 ×10 7 cm ⋅1.6 ×10 19 C ⋅ 8 ×1019 cm 3
= 1.3 nm

Spring 2003 EE130 Lecture 23, Slide 5

2ε SiV poly
(b) W poly =
qN poly

V poly = qN polyW poly

2
/ 2ε Si = 0.11 V

(c) VG = VFB + 2ψ B + Vox + V poly

E kT  N A 
VFB = −  G + ln  = −0.98 V
 2q q  ni 
VG = −0.98 V + 0.84 V + 1 V + 0.11 V = 0.97 V

Is the loss of 0.11V significant?

Spring 2003 EE130 Lecture 23, Slide 6

3
 Inversion-Layer Thickness Tinv
The average inversion-layer location below the Si/SiO2 interface
is called the inversion-layer thickness, Tinv .

Electron Density
poly-Si
gate depletion SiO2
region
Quantum
mechanical theory

Å
-50 -40 -30 -20 -10 0 10 20 30 40 50 A
Physical Tox

effective Tox

Spring 2003 EE130 Lecture 23, Slide 7

Electrical Oxide Thickness, Toxe

W poly Tinv
Toxe = tox + + at VG=Vdd
3 3

(VG + VT)/Tox can be shown to be the average electric field in the

inversion layer. Tinv of holes is larger than that of electrons because
of the difference in effective masses.
Spring 2003 EE130 Lecture 23, Slide 8

4
 Effective Oxide Capacitance
Toxe = tox + W poly / 3 + Tinv / 3

Qinv = Coxe (VG − VT )

C
Basic LF C-V
Cox
with gate-depletion

with gate-depletion and

charge-layer thickness

data

VG

Spring 2003 EE130 Lecture 23, Slide 9

VT Adjustment by Ion Implantation

• In modern IC fabrication processes, the threshold
voltages of MOS transistors are adjusted by ion
implantation:
– A relatively small dose NI (units: ions/cm2) of dopant atoms is
implanted into the near-surface region of the semiconductor
– When the MOS device is biased in depletion or inversion,
the implanted dopants add to the dopant-ion charge near the
oxide-semiconductor interface.

qN I N I > 0 for donor atoms

∆VT = −
Cox N I < 0 for acceptor atoms

Spring 2003 EE130 Lecture 23, Slide 10

5
 VT Adjustment by Back Biasing
• In some IC products, VT is dynamically adjusted by
applying a back bias:
– When a MOS capacitor is biased into inversion, a pn junction
exists between the surface and the bulk.
– If the inversion layer contacts a heavily doped region of the
same type, it is possible to apply a bias to this pn junction

N+ poly-Si
• VG biased so surface is inverted
+ + + + + + + +
SiO2 • Inversion layer contacted by N+ region
- - - - - - - - - • Bias VC applied to channel
N+
Æ Reverse bias VB-VC applied
p-type Si btwn channel & body

Spring 2003 EE130 Lecture 23, Slide 11

Effect of VCB on Vs, VT

• Application of reverse bias -> non-equilibrium
– 2 Fermi levels (one for n-region, one for p-region)
• Separation = qVBC ÎVs increased by VCB
• Reverse bias widens Wd, increases Qdep
ÎQinv decreases with increasing VCB, for a given VGB

2qN Aε Si (2ψ B + VCB )

VT = VFB + VC + 2ψ B +
Cox
Spring 2003 EE130 Lecture 23, Slide 12

6
Invention of the Field-Effect Transistor

In 1935, a British patent was issued to Oskar Heil.

A working MOSFET was not demonstrated until 1955.
Spring 2003 EE130 Lecture 23, Slide 13

Modern Field Effect Transistor (FET)

• An electric field is applied normal to the surface of the
semiconductor (by applying a voltage to an overlying
electrode), to modulate the conductance of the
semiconductor
→ Modulate drift current flowing between 2 contacts
(“source” and “drain”) by varying the voltage on the
“gate” electrode

N-channel MOSFET:

Spring 2003 EE130 Lecture 23, Slide 14

7
 MOSFET I-V Characteristic
Basic n-channel MOSFET structure and I-V characteristics

Spring 2003 EE130 Lecture 23, Slide 15

Two ways of representing a MOSFET:

Spring 2003 EE130 Lecture 23, Slide 16

8
Enhancement Mode vs. Depletion Mode

Spring 2003 EE130 Lecture 23, Slide 17

N-channel vs. P-channel

NMOS PMOS

N+ poly-Si P+ poly-Si

N+ N+ P+ P+

P-type Si n-type Si

• For current to flow, VGS > VT • For current to flow, VGS < VT
• Enhancement mode: VT > 0 • Enhancement mode: VT < 0
• Depletion mode: VT < 0 • Depletion mode: VT > 0
– Transistor is ON when VG=0V – Transistor is ON when VG=0V

Spring 2003 EE130 Lecture 23, Slide 18

9
 Complementary MOSFETs (CMOS)
NFET PFET

When Vg = Vdd , the NFET is on and the PFET is off.

When Vg = 0, the PFET is on and the NFET is off.

Spring 2003 EE130 Lecture 23, Slide 19

CMOS Inverter
Vd d
PFET
S
Vin D Vo ut
D
S C:
NFET capacitance
(of interconnect,
0V 0V etc.)
A CMOS inverter is made of a PFET pull-up device and a
NFET pull-down device.
Spring 2003 EE130 Lecture 23, Slide 20

10
 CMOS Logic Gates
V dd

AB

A
This two-input NAND
B gate and many other
logic gates are
extensions of the
basic inverter.

Spring 2003 EE130 Lecture 23, Slide 21

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