SSE3061: Digital System Design

Lecture 8.

Tae Hee Han: than@skku.edu

Semiconductor Systems Engineering
Sungkyunkwan University

Agenda
 Introduction to Programmable Logic Devices
 SPLD
 CPLD
 FPGA

2
Classification

Digital Logic

Programmable
Standard Logic ASICs Full Custom
Logic Devices

Microprocessor
SPLDs CPLDs FPGAs & RAM

TTL CMOS Gate Standard

74xx 4xxx Arrays Cells

Gate Array and Standard Cell

 Both of them are libraries (prepared before physical design)

Standard Cell Gate, flip-flop, 1-bit

adder, …
Adjustable Spacing
…
Metal interconnect
placed in channels
Megacells between cells

Gate Array
Fixed Spacing
Transistor / gate
…
Base Cell

4
Standard Cells (Between Full-custom and Gate Array)
 Use regular layout: Most popular for ASIC implementation
 Can automate the technology mapping process, but
 Takes 1~2 months to fabricate
 Limited flexibility
PWR
CELL CELL CELL CELL CELL CELL
1 2 (ND2) 3 4 (FA) 5 (INV) 6
GND

ROUTING
standard cells PWR
CELL CELL CELL CELL
ROUTING 7 (Flipflop) 8(AN2) 9 10 (MUX)
standard cells GND
ROUTING
standard cells
ROUTING
standard cells PWR
CELL CELL CELL CELL CELL CELL
ROUTING 11 12 13 14 15 16
standard cells GND

Full Custom Logic

 Manual layout
 Extremely high NREs
 Huge design time!
 Can make custom
macroblocks for use with
std. cells

6
Why FPGAs?
 By the early 1980’s most of the logic circuits in typical systems were absorbed by a
handful of standard large-scale integrated circuits (LSI).
 Microprocessors, bus/IO controllers, system timers, ...
 Every system still had the need for random “glue logic” to help connect the large ICs:
 generating global control signals (for resets etc.)
 data formatting (serial to parallel, multiplexing, etc.)
 Systems have lots of ICs and passive components.

Cost Issues in Production

 Constrained by production volume and time-to-market, the chip
maker must consider ROI (return on investment)
 Non-recurring Engineering Costs (NRE)
 Refers to the one-time cost to research, design, develop and test a new product
or product enhancement.
 Production Costs

8
Why FPGAs?
 Custom ICs sometimes designed to
replace the large amount of glue
logic:
 Reduced system complexity and
manufacturing cost, improved
performance.
 However, custom ICs are very expensive
to develop, and delay introduction of
product to market (time to market)
because of increased design time.

 Note: need to worry about two kinds

of costs:
1. cost of development, sometimes called
non-recurring engineering (NRE)
2. cost of manufacture
 A tradeoff usually exists between NRE
cost and manufacturing costs

ASIC versus FPGA

ASIC FPGA
Application Specific Field Programmable
Integrated Circuit Gate Array
• Designs must be sent • Bought off the shelf and
for expensive and time reconfigured by designers
consuming fabrication themselves
in semiconductor foundry
• No physical layout design;
• Designed all the way design ends with a bitstream
from behavioral description used to configure a device
to physical layout

10
Which Way to Go?

ASICs FPGAs

Off-the-shelf
High performance
Low development cost
Low power
Short time to market
Low cost in
high volumes Reconfigurability

11

Programmable Logic Devices

12
Brief History of Programmable Logic
 ROM can be considered as an early form of programmable logic
 User programmable logic in the form of AND-OR (Two-level logic)
circuits was developed at the beginning of the 1970s
 In the 1970s and 1980s, PALs and PLAs were very popular
 The early programmable devices allowed only one-time
programming with ultraviolet:
 However, it was slow (tens of minutes) and in-circuit erasure was not
possible
 Electrical erasable technology led to creation of FPGA: Fast and in-
circuit programming is possible
 In the late 1980s, Altera and Xilinx started using SRAM storage
elements to hold configuration information and created FPGA
markets

13

A Comparison of Programmable Devices

14
Programmable Logic Devices
 SPLDs (Simple PLDs)
 ROM, PLA, PAL
 Small gate count, fixed internal routing, deterministic propagation
delays (Two-level logic structure)

 CPLDs (Complex PLDs)

 Multiple SPLDs onto a single chip
 Programmable interconnect

 FPGAs
 An array of logic blocks
 Large number of gates, user selectable interconnection, delays
depending on design and routing
 A high ratio of flip-flops to logic resources

15

ROMs and Combinational Logic

 Combinational logic implementation (two-level canonical form) using a
ROM
F0 = A’B’C + AB’C’ + AB’C
F1 = A’B’C + A’BC' + ABC
F2 = A’B’C’ + A’B’C + AB’C’
F3 = A’BC + AB’C’ + A’BC’

Look-up Table (LUT) method

A B C F0 F1 F2 F3
0 0 0 0 0 1 0
ROM
0 0 1 1 1 1 0
8 words × 4 bits/word
0 1 0 0 1 0 0
0 1 1 0 0 0 1
1 0 0 1 0 1 1
1 0 1 1 0 0 0 A B C F0 F1 F2 F3

1 1 0 0 0 0 1 address outputs
1 1 1 0 1 0 0

truth table block diagram

16
ROM Structure
 Fully decoded AND array and Completely flexible OR
array

n address lines
• • •
inputs

Memory array
Address decoder 2n word (2n words
lines by m bits)

outputs
• • •

m data lines

17

Programmable Logic Array (PLA)

 Pre-fabricated building block of many AND/OR gates
 Actually NOR/NOR or NAND/NAND
 ”Personalized" by making or breaking connections among gates
 Programmable array block diagram for sum of products (SOP) form

• • •
inputs

AND OR
product
array array
terms

outputs
• • •

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Programmable Logic Array Example
 Multiple output functions of A, B,
C full decoder as for memory address
 F0 = ABC
 F1 = A + B + C bits stored in memory
A B C
 F2 = A’B’C’
 F3 = A’+ B’+ C’ A'B'C'
 F4 = A xor B xor C A'B'C
 F5 = A xnor B xnor C A'BC'
A'BC
A B C F0 F1 F2 F3 F4 F5
AB'C'
0 0 0 0 0 1 1 0 0
0 0 1 0 1 0 1 1 1 AB'C
0 1 0 0 1 0 1 1 1 ABC'
0 1 1 0 1 0 1 0 0 ABC
1 0 0 0 1 0 1 1 1
1 0 1 0 1 0 1 0 0
1 1 0 0 1 0 1 0 0 F0 F1 F2 F3 F4
1 1 1 1 1 0 0 1 1 F5

19

Alternate Representation for High Fan-in Structures

 Short-hand notation - don't have to draw all the wires
 Signifies a connection is present and perpendicular signal is an
input to gate
notation for implementing
F0 = AB + A’B’
F1 = CD’ + C’D

A B C D

AB

A’B’

CD’

C’D

AB+A’B’
CD’+C’D

20
PLA vs. PAL
 PLAs (Programmable Logic Arrays)
x1 x2 xn  Logic functions in Sum of Product form
 Both AND and OR planes are programmable
 PALs (Programmable Array Logics)
Input buffers  The AND plane is programmable; the OR plane is fixed
and  Simpler to manufacture, less expensive, better
Inverters performance than PLAs

x1 x1 𝑥 xn
P1

P2
Output inverters
AND plane OR plane
Pk

f1 fm

21

PLA vs. PAL

x1 x2 x3
PLA x1 x2 x3 PAL
Fixed

P1
P1

P2 f1
P2

P3
P3

P4 f2
P4

f1 f2

22
Regular Logic Structures for Two-level Logic (1/2)
 ROM – Full AND plane, general OR plane
 Cheap (high-volume component)
 Can implement any function of n inputs
 Medium speed

 PAL – Programmable AND plane, fixed OR plane

 Intermediate cost
 Can implement functions limited by number of terms
 High speed (only one programmable plane that is much smaller than ROM's
decoder)

 PLA – Programmable AND and OR planes

 (When compared to ROM and PAL) More complex in design and need more
sophisticated tools
 Can implement any function up to a product term limit
 Slow (two programmable planes)

23

Regular Logic Structures for Two-level Logic (2/2)

 ROM approach advantageous when
 Design time is short (no need to minimize output functions)
 Most input combinations are needed (e.g., code converters)
 Little sharing of product terms among output functions

 ROM problems
 Size doubles for each additional input
 Can't exploit don't cares

 PLA approach advantageous when

 Design tools are available for multi-output minimization
 There are relatively few unique minterm combinations
 Many minterms are shared among the output functions

 PAL problems
 Constrained fan-ins on OR plane

24
 Complex Programmable Logic Devices (CPLD)
 CPLD are similar to SPLD
except that they are
significantly higher capacity. L L L L L L L L

L L

L L
 The key feature of this L L
architecture is the arrangement L
Programmable L
of logic cells on the periphery L
routing L
of a central shared routing resource
L L

resource. L L

L L

L L L L L L L L
 CPLD are generally best for
control-oriented designs, due
in part to their fast pin-to-pin
performance.
25

CPLDs

1
I/O block

I/O block

PAL-like PAL-like To
0
block block interconnection
wires

Interconnection wires

To
I/O block

I/O block

PAL-like PAL-like D I/O

block block Q block

To implement multiple logic circuits Microcell

26
CPLD Architecture Detail (Altera MAX)

(PIA: programmable interconnect array)

27

What is an FPGA?

Configurable
Logic Blocks (CLB)
Block RAMs

Block RAMs

I/O Blocks

Block RAMs

28
Field Programmable Gate Arrays (FPGA)
 FPGA contain hundreds (or thousands) of
configurable Logic Block (CLB).
 One CLB is a rectangular area on the chip
that contains a lookup table (LUT), a flip-
flop and routing. L L L L L L L L
 LUT are used to create a logic function such L L L L L L L L
as AND, OR, and XOR. L L L L L L L L
 Flip-flop is a storage element (register) L L L L L L L L
 Routing is just a lot of interconnection L L L L L L L L
wiring between the CLB which can be
L L L L L L L L
linked together to form complex logic
implementations. L L L L L L L L
 Array of logic blocks is surrounded by L L L L L L L L
programmable I/O blocks and connected
with programmable interconnection.
 Most FPGAs do not provide 100%
interconnection between their logic blocks
because it would be prohibitively expensive.

29

CPLDs and FPGAs

Complex Programmable Logic Device (CPLD) Field-Programmable Gate Array (FPGA)

Architecture PAL-like Gate array-like

More Combinational More Registers + RAM
Density Low-to-medium Medium-to-high

Performance Predictable timing Application dependent

Up to hundreds MHz Up to hundreds MHz
Interconnect “Crossbar Switch” Incremental
(more flexible general-purpose interconnect)

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FPGA Design Flow (Overview)

Design Verification
HDL Source Design Entry

RTL Simulation
Design
Logic Synthesis to Gate Synthesis

Gate-level
Simulation
Mapping (pre-layout)

Placement Design Implementation STA

Gate-level
Route Back
Simulation
annotation
(post-layout)

Bitstream generation
& Programming Xilinx Device In-Circuit
Programming Verification
(Unique to FPGAs)

From
www.xilinx.com

31

FPGA Design Flow (Overview)

32
 33

Field Programmability
 Field programmability is achieved through switches
(Transistors controlled by memory elements or fuses)

 Switches control the following aspects

 Interconnection among wire segments
 Configuration of logic blocks
 Input / Output Blocks

 Distributed memory elements controlling the switches

and configuration of logic blocks are together called
“Configuration Memory”

34
User Programmability
 Latch-based (Xilinx, Altera, …)
 Latches are used to:
1. make or break cross-point
connections in interconnect
latch
2. define function of logic blocks
3. set user options:
 within the logic blocks
 in the input/output blocks
 global reset/clock

+reconfigurable
 “Configuration bit-stream”
- volatile loaded under user control:
- relatively large die size  All latches are strung together in a
shift chain
 “Programming”  creating bit-
- Note: Interconnection area stream
is dominant

35

Idealized FPGA Logic Block

set by configuration
Logic Block latch
bit-stream

1
INPUTS 4-LUT FF OUTPUT
0

4-input "look up table"

 4-input Look Up Table (4-LUT)

 Implements combinational logic functions
 Register
 Optionally stores output of LUT
 Latch determines whether read FF or LUT

36
Boolean Function Logic and a LUT

37

Look-up Tables
Multiplexer
 Using multiplexer
0
example
0 A 0
Z
0 1 1
B
 Configuration memory 0
S
holds truth table 1 0
1
1 1
 Input signals connect 0
Z Truth table

to select inputs of 0 0
1 1 S
0
A
0
B
0
Z
0
multiplexers to select 1 1
0 0
0
0
1
1
0
0
1
output value of truth 1
0 1 1 1
1 0 0 0
table for any given 0 0
1 0 1 1
input value 1 1 1
1
1
1
0
1
0
1
1 0 1
B A S

38
4-LUT Implementation
 n-bit LUT is actually implemented
as a
2n × 1 memory:
INPUTS  inputs choose one of 2n memory
locations
latch
 memory locations (latches) are
normally loaded with values from
latch user’s configuration bit stream.
 Inputs to mux control are the
latch 16 x 1 CLB (Configurable Logic Block)
16 OUTPUT
mux inputs
 Result is a general purpose “logic
gate”
 n-LUT can implement any
latch function of n inputs!
Latches programmed as part
of configuration bit-stream

39

Technology of Programmable Elements

 Vary from vendor to vendor. All share the common
property: Configurable in one of the two positions – ‘ON’
or ‘OFF’
 Can be classified into three categories:
 SRAM based
 Anti-fuse based
 EPROM/EEPROM/Flash based
 Desired properties:
 Minimum area consumption
 Low on resistance; High off resistance
 Low parasitic capacitance to the attached wire
 Reliability in volume production

40
SRAM Programming Technology
 Employs SRAM (Static RAM) cells to control pass transistors and/or transmission
gates
 SRAM cells control the configuration of logic block as well
 Volatile
 Needs an external storage
 Needs a power-on configuration mechanism
 In-circuit re-programmable
 Lesser configuration time
 Occupies relatively larger area

41

Anti-fuse Programming Technology

 Though implementation differ, all anti-fuse programming elements
share common property
 Uses materials which normally resides in high impedance state
 But can be fused irreversibly into low impedance state by applying high
voltage

42
Anti-fuse Programming Technology
 Very low ON Resistance (Faster implementation of circuits)

 Limited size of anti-fuse elements; Interconnects occupy

relatively lesser area
 Offset: Larger transistors needed for programming

 One-Time Programmable (OTP)

 Cannot be re-programmed
 (Design changes are not possible)
 Retain configuration after power off

43

EPROM, EEPROM or Flash Based Programming Technology

 EPROM (Erasable PROM)

Technology
 Two gates: Floating and Select
 Normal mode:
 No charge on floating gate
 Transistor behaves as normal n-
channel transistor
 Floating gate charged by applying
high voltage UV Light

 Threshold of transistor (as seen Vgg

by gate) increases
 Transistor turned off permanently Vss Vdd

 Re-programmable by exposing to ------------------ +++++++++++

UV radiation Hot electrons

n+ n+ n+ n+

Program Erase

44
Programming (writing to) the EPROM
 Programmers send the address for location to be
programmed, its data, and pulse the PGM pin low for
~100 ms

45

Programming (writing to) the EPROM

46
EPROM vs. E2PROM
 Disadvantages of the EPROM:
 Should be removed from circuit board to be programmed
 Byte eraser is not possible
 The quartz window is expensive

 Electrically Erasable PROM: E2PROM

 Can be programmed and erased in its place
 Both byte and bulk eraser modes are possible
 It has a lifetime : typically 1,000,000 read/write cycles

47

48
Programmable Logic Block Architecture
 Basic building blocks in FPGA
 Look-up Table (LUT) based logic blocks
 Mux and logic gate based logic blocks

 Different FPGA manufactures use different names to

denote their logic blocks
 Configurable Logic Block (CLB) – Xilinx
 Logic Elements (LE), Logic Array Blocks (LABs) – Altera
 VersaTiles - Actel

49

50
51

52
 Programmable Interconnects

Symmetric
Array
FPGAs

Row-Based
FPGAs

53

Programmable I/O Blocks in FPGAs

54
Dedicated Specialized Components in FPGAs
 Dedicated Memory
 Dedicated Arithmetic Units
 Multipliers
 Digital Signal Processing Blocks
 Embedded Processors
 Contents Addressable Memory (CAM)

55

Xilinx SoC-like FPGA Versal

56
Regular Logic Structures for Multi-level Logic
 Difficult to devise a regular structure for arbitrary
connections between a large set of different types of
gates
 Efficiency/speed concerns for such a structure
 Xilinx field programmable gate arrays (FPGAs) are just such
programmable multi-level structures
 Programmable multiplexers for wiring
 Lookup tables for logic functions (programming fills in the table)
 Multi-purpose cells (utilization is the big issue)

 Use multiple levels of PALs/PLAs/ROMs

 Output intermediate result
 Make it an input to be used in further logic

57

Applications of FPGAs
 Rapid Prototyping
 As Final Product in Medium-speed Systems
 Reconfigurable Circuits and Systems
 Glue Logic
 Hardware Accelerators/Coprocessors

58
Announcements
 Homework #5
 Textbook problems
 Probs.: 3.7, 3.8, 3.10, 3.11, 3.14, 3.15
 Reports must be written in hand, not in computer printing

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