SSE3061: Digital System Design

Verilog: Part 1

Tae Hee Han: than@skku.edu

Semiconductor Systems Engineering
Sungkyunkwan University

Ways of specifying digital logics

 Schematics
 Structural description
 Describe circuit as
interconnected elements
 Build complex circuits using
hierarchy
 Large circuits are unreadable

 Hardware description
languages (HDLs)
 Not (SW) programming
languages
 Parallel languages tailored to
digital design
 Synthesize code to produce a
circuit

2
Hardware Description Language
 HDL – a “language” for
describing hardware
 Two industry IEEE standards:
 Verilog
 VHDL (Very High Speed
Integrated Circuit HDL)

 Verilog
 Originally designed for
simulation and verification
 Gateway Design Automation,
1984
 Functionality later added for
synthesis

History of the Verilog HDL

 Need: a simple, intuitive and effective way of describing
digital circuits for modeling, simulation and analysis
 1984: Gateway Design Automation introduced the
Verilog-XL digital logic simulator
 The Verilog language was part of the Verilog-XL simulator
 The language was mostly created by one person, Phil Moorby
 Verilog : Verify Logic
 1989: Gateway merged into Cadence Design Systems
 1990: Cadence made the Verilog HDL public domain
 Open Verilog International (OVI) controlled the language

4
History of the Verilog HDL (Cont’d)
 1995: The IEEE standardized the Verilog HDL (IEEE 1364)
 2001: The IEEE enhanced the Verilog HDL for modeling
scalable designs, deep sub-micron accuracy, etc.
 2005: Verilog 2005 (IEEE Standard 1364-2005) consists
of minor corrections, spec clarifications, and a few new
language features
 A separate part of the Verilog standard, Verilog-AMS, attempts
to integrate analog and mixed signal modeling with traditional
Verilog.
 2009: Verilog standard (IEEE 1364-2005) was merged
into the SystemVerilog standard (IEEE 1800-2009)
 Now Verilog is officially part of the SystemVerilog language
 Current version is IEEE 1800-2017
5

Useful Features of the Verilog HDL

 A general-purpose HDL
 Easy to learn and use
 Syntax is similar to C (VHDL is similar to PASCAL)
 Allows different levels of abstraction to be mixed in the same
model
 In terms of switches, gates, RTL, or behavioral code
 Need to learn only for stimulus and hierarchical design
 Most popular logic synthesis tools support Verilog
 Rich of Verilog HDL libraries
 Provided by fabrication vendors for post logic synthesis simulation
 Allows the widest choice of vendors while designing a chip
 With powerful PLI (Programming Language Interface)
 Write custom C code to interact with internal data structure
6
Trends in HDLs
 Higher levels of abstraction
 Think only in terms of functionality for designers
 CAD tools take care of the implementation details
 Behavioral modeling
 Design directly in terms of algorithms and the behavior of the circuit
 Formal verification
 Supports for Mixed-level design
 Ex: very high speed and timing-critical circuits like μPs
 Mix gate-level description directly into the RTL description
 System-level design in a mixed bottom-up methodology
 Use either existing Verilog modules, basic building blocks, or IPs
 Ex: SystemC for SoC designs

Issues In RTL Design & Verification Today

 Designs are getting bigger
 Need to code for reuse and higher abstraction
 Need more efficient coding constructs
 Testbenches are growing exponentially
 Generate more tests faster
 More advanced techniques needed over traditional simulation
 Need ways to measure verification progress
 What users want
 An "incremental" change to their existing environment
 Re-use of their existing code
 Vendor-independent design and testbench language
 Minimal learning curve

Productivity is critical!
8
SystemVerilog Misunderstandings
Verilog is a design language, and
SystemVerilog is a verification
language And synthesis
compilers can’t
read in
SystemVerilog

 Not True! – SystemVerilog was designed to enhance both the

design and verification capabilities of traditional Verilog
 Technically, there is no such thing as “Verilog” – the IEEE
changed the name to “SystemVerilog” in 2009
 SystemVerilog is a significant set of extensions to Verilog
 SystemVerilog object-oriented features are just like C++ and SystemC
and will take some time to learn
9

What is SystemVerilog?
 SystemVerilog offers productivity!
 It is a concise, unified language for design and testbenches.
 A single simulation tool can verify a design with advanced testbench, and
verification features included.
 SystemVerilog (IEEE 1800) adds extensions to the IEEE Verilog
2001 standard:
 C/C++ type language constructs for efficient programming
 Language enhancements for synthesis and downstream tools
 Interfaces to encapsulate communication between design blocks
 Assertions and coverage for new verification techniques
 System-level testbench features to allow advanced verification
methodologies
 Lightweight interface to C/C++ programs

A single language for modeling complete digital systems!

10
SystemVerilog Extensions
SystemVerilog (IEEE 1800)
verification

assertions mailboxes classes dynamic arrays 2-state types

test program blocks semaphores inheritance associative arrays shortreal type
clocking domains constrained random values strings queues globals
process control direct C function calls references checkers let macros

Interfaces packed arrays break enum ++ -- += -= *= /=

nested hierarchy array assignments continue typedef >>= <<= >>>= <<<=
unrestricted ports unique/priority case/if return structures &= |= ^= %=
design

automatic port connect void functions do–while unions ==? !=?

enhanced literals function input defaults case inside 2-state types inside
time values and units function array args aliasing packages streaming
specialized procedures parameterized types const $unit casting

Verilog-2005
uwire `begin_keywords `pragma $clog2
Verilog-2001
ANSI C style ports standard file I/O (* attributes *) multi dimensional arrays
Generate $value$plusargs Configurations signed types
Localparam `ifndef `elsif `line memory part selects automatic
constant functions @* variable part select ** (power operator)
Verilog-1995 (created in 1984)
modules $finish $fopen $fclose initial wire reg begin–end
parameters $display $write disable integer real while + =* /
function/tasks $monitor Events time for forever %
always @ `define `ifdef `else wait # @ packed arrays if–else >> <<
assign `include `timescale fork–join 2D memory repeat

11

General Features in SystemVerilog

 SystemVerilog has a lot of new content
 97 new keywords
 31 different sections of the LRM (Language Reference Manual)
 584 pages in the SV3.1a LRM, all new content
 Major categories of SystemVerilog features
 Convenience and synthesis features
 Data Types
 Interfaces Designer Productivity
Features
 SystemVerilog Assertions (SVA)
 Designer testbench
 Object-oriented testbench
Testbench
 Coverage Enhancements
 Direct Programming Interface (DPI)
12
Why Code Size Matters

Designers inject approx. 1 defect per 10 lines of code

Excellent code ships with ~1 defect per KLOC

100M LOC

13

Typical RTL Code

14
Design Flow
 What functions are you want to program?
 Input and output
 Specify the Input/Output signals
 Separate the whole circuit into smaller ones
 Each block has its own function / purpose
 Connect all blocks/modules

B1 B2

B3

15

Verification Scenario
 Use test bench file to verify your design

Stimulus Response
& &
Control Signal Verification

Test-Bench Module Monitor Signals

16
Simulation and Synthesis
 Simulation tools typically accept full set of Verilog
language constructs
 Some language constructs and their use in a Verilog
description make simulation efficient and are ignored by
synthesis tools  details will be covered later
 Synthesis tools typically accept only a subset of the full
Verilog language constructs
 Synthesizable subset

17

Simulation …

18
… and Synthesis

19

Four values in Verilog

Value Meaning
0 Logic zero
1 Logic one
X Unknown logic value
Z High impedance, floating

An X bit might be a 0, 1, Z, or in transition. We can set

bits to be X in situations where we don’t care what the
value is. This can help catch bugs and improve
synthesis quality.

20
wire is used to denote a standard hardware net

wire [15:0] instruction;

Absolutely no type safety
wire [15:0] memory_req;
when connecting nets!
wire [ 7:0] small_net;

?
memory_req

instruction
instruction

small_net
21

bit literals in various bases

 Binary literals
 8’b0000_0000

 8’b0xx0_1xx1
4’b10_11
 Hexadecimal literals Underscores
 32’h0a34_def1 are ignored

 16’haxxx Base format

(d,b,o,h)
 Decimal literals
Decimal number
 32’d42
representing size in bits

We’ll learn how to

actually assign literals to
nets a little later

22
Testbench Approach
 Use Verilog module to produce testing environment
including stimulus generation and/or response
monitoring

Stimulus Response
UUT
Module

Testbench Module

23

Modules
 The Module Concept
 Basic design unit for Verilog designs
 Modules are:
 Declared
 Instantiated

 Module declarations cannot be nested

24
What is a module?
 module is a block of circuit
 Special function
 AND, OR, Mux, Adder, Shifter…
 Most important
 Input and Output

module

25

Module
 General definition  Example

module module_name
module HalfAdder (A, B, Sum, Carry);
( port_list );
input A, B;
port declarations; output Sum, Carry;
… assign Sum = A ^ B;
variable declaration; //^ denotes XOR
… assign Carry = A & B;
// & denotes AND
description of behavior
endmodule
endmodule

26
Lexical Conventions
 Comments
// Single line comment
/* Another single line comment */
/* Begins multi-line (block) comment
All text within is ignored
Line below ends multi-line comment
*/
 Number
decimal, hex, octal, binary
unsized decimal form
size base form
 String
" Enclose between quotes on a single line"

27

Lexical Conventions (cont.)

 Identifier
 A ... Z
 a ... z
 0 ... 9
 Underscore
 Strings are limited to 1024 chars
 First char. of identifier must not be a digit
 Verilog is case sensitive

28
Module name and a port list

module adder( A, B, cout, sum );

input [3:0] A;
A B input [3:0] B;
4 4 output cout;
output [3:0] sum;

// HDL modeling of
Adder // adder functionality

endmodule
4

Note the semicolon at

cout sum Ports must have a the end of the port list!
direction (or be
bidirectional) and a
bitwidth.

29

Module name and a port list

A B Traditional Verilog-1995 Syntax

module adder( A, B, cout, sum );
4 4
input [3:0] A;
input [3:0] B;
output cout;
Adder output [3:0] sum;

4 ANSI C Style Verilog-2001 Syntax

module adder( input [3:0] A,
cout sum input [3:0] B,
output cout,
output [3:0] sum );

30
Module instantiation to create a module hierarchy

a b module FA( input a, b, cin,

output cout, sum );
cin
cout FA // HDL modeling of 1 bit
// full adder functionality

endmodule
c

31

Module instantiation to create a module hierarchy

A B

Adder FA FA FA FA

cout S

module adder( input [3:0] A, B,

output cout,
output [3:0] S );
wire c0, c1, c2;
FA fa0( ... );
FA fa1( ... );
FA fa2( ... );
FA fa3( ... );
endmodule

32
Module instantiation to create a module hierarchy

A B

Adder FA FA FA FA

cout S

module adder( input [3:0] A, B,

output cout,
output [3:0] S );
wire c0, c1, c2;
FA fa0( A[0], B[0], 1’b0, c0, S[0] );
FA fa1( A[1], B[1], c0, c1, S[1] );
FA fa2( A[2], B[2], c1, c2, S[2] );
FA fa3( A[3], B[3], c2, cout, S[3] );
endmodule Carry Chain
33

Mapping ports by position or by name

Connecting ports by ordered list
FA fa0( A[0], B[0], 1’b0, c0, S[0] );

Connecting ports by name (compact)

FA fa0( .a(A[0]), .b(B[0]),
.cin(1’b0), .cout(c0), .sum(S[0]) );

Connecting ports by name

FA fa0
( For all but the smallest
.a
.b
(A[0]),
(B[0]),
modules, connecting ports by
.cin (1’b0), name yields clearer and less
.cout (c0), buggy code.
.sum (S[0])
);

34
Schematic diagram into structural Verilog

FA FA FA FA

module adder( ... ); [3:0] A, B,

input
output cout,
output [3:0] S );
wire c0, c1, c2;
FA fa0( A[0],
... );B[0], 1’b0, c0, S[0] );
FA fa1( ...
A[1],
);B[1], c0, c1, S[1] );
FA fa2( ...
A[2],
);B[2], c1, c2, S[2] );
FA fa3( A[3],
... );B[3], c2, cout, S[3] );
endmodule

35

Functional Verilog in three abstraction levels

Behavioral
Algorithm V Abstract algorithmic description

Manual

Register Describes how data flows between

Transfer Level V state elements for each cycle
Logic Synthesis

Gate Level V Low-level netlist of primitive gates

Auto Place + Route

36
Gate-level Verilog uses Structural Verilog
module mux4( input a, b, c, d, input [1:0] sel, output out );
wire [1:0] sel_b;
not not0( sel_b[0], sel[0] ); b d a c sel[1] sel[0]
not not1( sel_b[1], sel[1] );
wire n0, n1, n2, n3;
and and0( n0, c, sel[1] );
and and1( n1, a, sel_b[1] );
and and2( n2, d, sel[1] );
and and3( n3, b, sel_b[1] );
wire x0, x1;
nor nor0( x0, n0, n1 );
nor nor1( x1, n2, n3 );
wire y0, y1;
or or0( y0, x0, sel[0] );
or or1( y1, x1, sel_b[0] );
nand nand0( out, y0, y1 );
out
endmodule

37

Continuous Assignment
Explicit continuous assignment

wire [15:0] netA;

wire [15:0] netB;

assign netA = 16’h3333;

assign netB = netA;

Implicit continuous assignment

wire [15:0] netA = 16’h3333;

wire [15:0] netB = netA;

38
Using Continuous Assignment for 4-to-1 Mux

module mux4( input a, b, c, d d,

input [1:0] sel,
output out );

wire out, t0, t1;

assign t0
out = ~( (sel[1]
(t0 | sel[0])
& c) |&(~sel[1]
(t1 | ~sel[0])
& a) ););
assign t1 = ~( (sel[1] & d) | (~sel[1] & b) );
assign out
t0 = ~( (sel[1]
(t0 | sel[0])
& c) |&(~sel[1]
(t1 | ~sel[0])
& a) ););

endmodule

The order of these continuous assignment

statements does not matter.
They essentially happen in parallel!

39

Verilog Includes Many Operators

// Four input multiplexer

module mux4( input a, b, c, d,
input [1:0] sel,
output out );
assign out = ( sel == 0 ) ? a : If input is undefined, we want
( sel == 1 ) ? b :
to propagate that information.
( sel == 2 ) ? c :
( sel == 3 ) ? d : 1’bx;

endmodule

// Simple four-bit adder

module adder( input [3:0] op1, op2,
output [3:0] sum );
assign sum = op1 + op2;
endmodule

40
Verilog RTL Operators
Arithmetic + - * / % ** Reduction & ~& | ~| ^ ^~(or ~^)
Logical ! && || Shift >> << >>> <<<
Relational > < >= <= Concatenation {}
Equality == != === !== Conditional ?:
Bitwise ~ & | ^ ^~(or ~^)

wire [ 3:0] net1 = 4’b00xx;

wire [ 3:0] net2 = 4’b1110;
wire [11:0] net3 = { 4’b0, net1, net2 };

wire equal = ( net3 === 12’b0000_00xx_1110 );

logical case equality (===), logical case inequality (!==): allows for checking of x and z
values

Avoid ( / % ** ) since they usually synthesize poorly

41

Verilog RTL Operators

 Logical Operators
 logical-and (&&) //binary operator
 logical-or (||) //binary operator
 logical-not (!) //unary operator

//suppose that: a = 3 and b = 0, then...

(a && b) //evaluates to zero
(b || a) //evaluates to one
(!a) //evaluates to 0
(!b) //evaluates to 1
//with unknowns: a = 2'b0x; b = 2'b10;
(a && b) // evaluates to x
//with expressions...
(a == 2) && (b == 3) /* evaluates to 1 only if both
comparisons are true */

42
Verilog RTL Operators
 Bitwise Operators
 Logical operators result in logical 1, 0 or x
 Bitwise operators results in a bit-by-bit value

// let a = 4'b1010, b = 4'b0000

a | b // bitwise OR, result is 4'b1010
a || b // logical OR, result is 1

43

Verilog RTL Operators

 Equality Operators

// let a = 4, b = 3, and...
// i = 4'b1010, j = 4'b1101,
// k = 4'b1xxz, m = 4'b1xxz, n = 4'b1xxx

a == b //evaluates to logical 0
i != j //evaluates to logical 1
i == k //evaluates to x
k === m //evaluates to logical 1
k === n //evaluates to logical 0
m !== n //evaluates to logical 1

44
Verilog RTL Operators
 Reduction Operators
 and(&), nand(~&), or(|), nor(~|), xor(^), xnor (~^)
 Operates on only one operand
 Performs a bitwise operation on all bits of the operand
 Returns a 1-bit result
 Works from right to left, bit by bit

// let a = 4'b1010

&a //equivalent to 1 & 0 & 1 & 0. Results in 1'b0

|a //equivalent to 1 | 0 | 1 | 0. Results in 1'b1
^a //equivalent to 1 ^ 0 ^ 1 ^ 0. Results in 1'b0

45

Verilog RTL Operators

 Shift Operators
 right shift (>>)
 left shift (<<)
 arithmetic right shift (>>>)
 arithmetic left shift (<<<)
 Shift operator shifts a vector operand left or right by a specified number of
bits, filling vacant bit positions with zeroes
 Shifts do not wrap around (not Rotate)

// let a = 4'b1100
y = a >> 1; // y is 4'b0110
y = a << 1; // y is 4'b1000
y = a << 2; // y is 4'b0000

46
Verilog RTL Operators
 Shift Operators
 Arithmetic Shift Operators
 arithmetic right shift (>>>)
 Shift right specified number of bits, fill with value of sign bit if expression is
signed, otherwise fill with zero
 arithmetic left shift (<<<)
 Shift left specified number of bits, filling with zero

47

Functions
 Use functions for complex combinational logic
module and_gate (out, in1, in2);
input in1, in2;
output out;

assign out = myfunction(in1, in2);

function myfunction;
input in1, in2; Benefit:
begin Functions force a result
myfunction = in1 & in2;  Compiler will fail if function
end does not generate a result
endfunction

endmodule

48
Procedural Constructs
 Two Procedural Constructs
 initial Statement
 always Statement
 initial Statement : Executes only once
 usually not used in design because it is not synthesizable.
 always Statement : Executes in a loop
 Example:
… …
initial begin always @(A or B) begin
Sum = 0; Sum = A ^ B;
Carry = 0; Carry = A & B;
end end
… …

49

@ Time Control
 @(*)
 @ (expression)
 @ (expression or expression or …)
 @ (posedge onebit)
 @ (negedge onebit)
 do not execute statement until event occurs
 @(clk) is same as @(posedge clk or negedge clk)

50
Event Control
 Event Control
 Edge Triggered Event Control
 Level Triggered Event Control

 Edge Triggered Event Control

@ (posedge CLK) //Positive Edge of CLK
Curr_state = Next_state;

 Level Triggered Event Control

@ (A or B) //change in values of A or B
Out = A & B;

51

Activation (or sensitivity) List

 Tells the simulator when to ‘run’ this block
 Allows the user to specify when to run the block and makes the
simulator more efficient
 If not sensitized to every input, you get a storage element
Usually resulted in unintended storage

 But also makes it possible for subtle flaws to creep into

the design.
 Two forms of activation list in Verilog:
 @(signalName or signalName or …)
 Evaluate this block when any of the named signals change
 @posedge(signalName); or @negedge(signalName);
 Makes an edge triggered flop. Evaluates only on one edge of a signal.
52
Three Ways of Writing Sensitivity List

reg sum, carry; reg sum, carry; reg sum, carry;

always @ (x or y) always @ (x, y) always @ (*)

begin begin begin
sum = x^y; sum = x^y; sum = x^y;
carry = x&y; carry = x&y; carry = x&y;
end end end

Verilog-2001 support of
Verilog-2001 style that
Verilog-95 style comma separated
only writes * in the list
sensitivity list

53

Activation List Examples

always @(clk) always @(clk) always @(clk or in)
outA = in; if (clk) outB = in; if (clk) outC = in;

clk

in

outA

outB

outC

54
Loop Statements
 Loop Statements
 repeat
 while
 for

 Repeat Loop
 Example:
repeat (Count)
sum = sum + 5;
 If condition is a x or z it is treated as 0

55

Loop Statements (cont.)

 While Loop
 Example:
while (Count < 10) begin
sum = sum + 5;
Count = Count +1;
end
 If condition is a x or z it is treated as 0
 For Loop
 Example:
for (Count = 0; Count < 10; Count = Count + 1) begin
sum = sum + 5;
end

56
Conditional Statements - if … else if… else
 Format:
if (condition)
procedural_statement
else if (condition)
procedural_statement
else
procedural_statement

 Example:
if (Clk)
Q = 0;
else
Q = D;

57

Conditional Statements - case

 Example 1:
case (sel[1:0])
2’b00: Y = A + B;
2’b01: Y = A – B;
2’b10: Y = A / B;
endcase

 Example 2:
case (3’b101 << 2)
3’b100: A = B + C;
4’b0100: A = B – C;
5’b10100: A = B / C; //This statement is executed
endcase

58
Conditional Statements (cont.)
 Variants of case Statements:
 casex and casez

 casez – z is considered as a don’t care

 casex – both x and z are considered as don’t cares

 Example:
casez (sel[1:0])
2’b0z: A = B + C;
2’b1z: A = B / C;
endcase https://vlsiverify.com/verilog/case-statement

59

Assignments
 Blocking assignments (Q = A) always @(posedge CLK)
 Variable is assigned immediately begin
B = A;
 New value is used by subsequent A = B;
statements end

B=A, A=A
 Non-blocking assignments (Q <= A)
 Variable is assigned after all scheduled
always @(posedge CLK)
statements are executed begin
B <= A;
 Value to be assigned is computed but
saved for later parallel assignment A <= B;
end
 Usual use: Register assignment
 Registers simultaneously take new values Swap A and B
after the clock edge

60
Blocking vs. Non-blocking Assignment
 Blocking assignment  Non-blocking assignment
‘B’ is not
always @(posedge CLK) always @(posedge CLK) affected by the
begin begin previous
statement 
B = A; // evaluated first serially B <= A; // statement  yet.
//wait for the above evaluation to complete C <= B; // statement 
//before its own evaluation, end
//which makes the final evaluation to be // Here, statement  and 
// C = B = A // are executed concurrently.
C = B;
end

A D Q C B

CLK A D Q D Q C

CLK
D Q B

61

‘always’
 ‘always’ blocks have parallel inter-block and sequential
intra-block semantics
module mux4( input a, b, c, d,
input [1:0] sel,
output out );

reg out, t0, t1;

always @( a or b or c or d or sel )
begin
t0 = ~( (sel[1] & c) | (~sel[1] & a) );
t1 = ~( (sel[1] & d) | (~sel[1] & b) );
out = ~( (t0 | sel[0]) & (t1 | ~sel[0]) );
end

endmodule The always block is reevaluated whenever

a signal in its sensitivity list changes

62
‘always’
 ‘always’ blocks have parallel inter-block and sequential
intra-block semantics
module mux4( input a, b, c, d,
input [1:0] sel,
output out );

reg out, t0, t1;

always @( a or b or c or d or sel )
begin
t0 = ~( (sel[1] & c) | (~sel[1] & a) );
t1 = ~( (sel[1] & d) | (~sel[1] & b) );
out = ~( (t0 | sel[0]) & (t1 | ~sel[0]) );
end
The order of these procedural assignment
endmodule statements does matter.
They essentially happen sequentially!

63

‘always’
 ‘always’ blocks have parallel inter-block and sequential
intra-block semantics
module mux4( input a, b, c, d,
input [1:0] sel,
output out );

reg out, t0, t1;

always @( a or b or c or d or sel )
begin
t0 = ~( (sel[1] & c) | (~sel[1] & a) );
t1 = ~( (sel[1] & d) | (~sel[1] & b) );
out = ~( (t0 | sel[0]) & (t1 | ~sel[0]) );
end
LHS of procedural assignments must be
endmodule
declared as a reg type. Verilog reg is not
necessarily a hardware register!
64
‘always’
 ‘always’ blocks have parallel inter-block and sequential
intra-block semantics
module mux4( input a, b, c, d,
input [1:0] sel,
output out );

reg out, t0, t1;

always @( a or b or c or d or sel )
begin
t0 = ~( (sel[1] & c) | (~sel[1] & a) );
t1 = ~( (sel[1] & d) | (~sel[1] & b) );
out = ~( (t0 | sel[0]) & (t1 | ~sel[0]) );
end
What happens if we accidentally forget
endmodule
a signal on the sensitivity list?

65

‘always’
 ‘always’ blocks have parallel inter-block and sequential
intra-block semantics
module mux4( input a, b, c, d,
input [1:0] sel,
output out );

reg out, t0, t1;

always @( * )
begin
t0 = ~( (sel[1] & c) | (~sel[1] & a) );
t1 = ~( (sel[1] & d) | (~sel[1] & b) );
out = ~( (t0 | sel[0]) & (t1 | ~sel[0]) );
end
Verilog-2001 provides special syntax to
endmodule automatically create a sensitivity list for all
signals read in the always block

66
Continuous vs. Procedural Assignments
 Continuous assignments are for naming and thus we cannot have
multiple assignments for the same wire.
wire out, t0, t1;
assign t0 = ~( (sel[1] & c) | (~sel[1] & a) );
assign t1 = ~( (sel[1] & d) | (~sel[1] & b) );
assign out = ~( (t0 | sel[0]) & (t1 | ~sel[0]) );

 Procedural assignments hold a value semantically, but it is

important to distinguish this from hardware state.
reg out, t0, t1, temp;
always @( * )
begin
temp = ~( (sel[1] & c) | (~sel[1] & a) );
t0 = temp;
temp = ~( (sel[1] & d) | (~sel[1] & b) );
t1 = temp;
out = ~( (t0 | sel[0]) & (t1 | ~sel[0]) );
end
67

‘always’ block: Advanced Control Constructs

module mux4( input a, b, c, d, module mux4( input a, b, c, d,

input [1:0] sel, input [1:0] sel,
output out ); output out );
reg out; reg out;
always @( * ) always @( * )
begin begin
if ( sel == 2’d0 ) case ( sel )
out = a; 2’d0 : out = a;
else if ( sel == 2’d1 ) 2’d1 : out = b;
out = b; 2’d2 : out = c;
else if ( sel == 2’d2 ) 2’d3 : out = d;
out = c; default : out = 1’bx;
else if ( sel == 2’d3 ) endcase
out = d; end
else
out = 1’bx; endmodule
end
endmodule

68
What happens if ‘case’ statement is not complete?

module mux3( input a, b, c,

input [1:0] sel,
output out );
reg out;
always @( * )
begin If sel = 3, mux will output
case ( sel ) the previous value.
2’d0 : out = a; What have we created?
2’d1 : out = b;
2’d2 : out = c;
endcase
end

endmodule

69

What happens if ‘case’ statement is not complete?

module mux3( input a, b, c,

input [1:0] sel,
output out );
reg out;
always @( * )
begin We can prevent creating state with
case ( sel ) a default statement
2’d0 : out = a;
2’d1 : out = b;
2’d2 : out = c;
default : out = 1’bx;
endcase
end

endmodule

70
How to make Latches and Flip-Flops?

module latch( module flipflop(

input clk, input clk,
input d, input d,
output reg q ); output reg q );

always @( clk or d ) always @( posedge clk )

begin begin
if ( clk ) q <= d;
q <= d; end Edge-triggered
end always block
endmodule
endmodule

71

Non-blocking Assignment
 The order of non-blocking assignments does not matter!

wire A_in, B_in, C_in; wire A_in, B_in, C_in;

reg A_out, B_out, C_out; reg A_out, B_out, C_out;

always @( posedge clk ) always @( posedge clk )

begin begin
A_out <= A_in; C_out <= C_in;
B_out <= B_in; B_out <= B_in;
C_out <= C_in; A_out <= A_in;
end end

assign B_in = A_out + 1; assign B_in = A_out + 1;

assign C_in = B_out + 1; assign C_in = B_out + 1;

72
Incorrect Flip-Flop in Verilog
 Use always block's sensitivity list to wait for clock to
change
module dff (CLK, d, q);

input CLK, d;
output q; Double edge-triggered.
reg q; This should be avoided.
always @(CLK)
q <= d;

endmodule

73

Correct Flip-Flop in Verilog

 Use always block's sensitivity list to wait for clock edge

module dff (CLK, d, q);

input CLK, d;
output q;
reg q;

always @(posedge CLK)

q <= d;

endmodule

74
Common Patterns for Latch and Flip-Flop Inference

always @( clk or D )
begin next_X D Q X
if ( clk )
clk
Q <= D;
end

always @( posedge clk ) next_X D Q X

begin
Q <= D; clk
end

always @( posedge clk )

next_X D Q X
begin
if ( enable ) clk
Q <= D;
end enable

75

More Flip-Flops
 Synchronous/asynchronous reset
 single thread that waits for the clock
 two parallel threads – only one of which waits for the clock

Synchronous Asynchronous

Specifying
module dff (CLK, rb, en, d, q); module dff (CLK, rb, en, d, q);
active low
input CLK, rb, en, d; input CLK, rb, en, d;
output q; reset
output q;
reg q; reg q;
always @(posedge CLK)
if (!rb) q <= 1'b0; always @(negedge rb or posedge CLK)
else if (en) q <= d; if (!rb) q <= 1’b0;
endmodule
else if (en) q <= d;
endmodule

76
Writing Good Synthesizable Verilog (but not mandatory)
 Only leaf modules should have functionality
 All other modules are strictly structural, i.e., they only wire together sub-
modules
 Use only positive-edge triggered flip-flops for state
 Do not assign to the same variable from more than one always
block
 Separate combinational logic from sequential logic
 Combinational logic described using always @(*) and blocking =
assignments and assign statements
 Sequential logic described with always @(posedge clk) and non-blocking
<= assignments
Combinational logic
assign C_in = B_out + 1;
always @( posedge clk ) Update of state only (don’t be tempted
C_out <= C_in; to add combinational logic into
clocked always block)

77

Behavioral Verilog
 Behavioral Verilog is used to model the abstract function
of a hardware module
 Characterized by heavy use of sequential blocking
statements in large always blocks
 Many constructs are not synthesizable but can be useful
for behavioral modeling
 Data dependent for and while loops
 Additional behavioral data types : integer, real
 Magic initialization blocks : initial
 Magic delay statements: #<delay>

78
High-level Behavioral Hardware Model
module factorial( input [ 7:0] in, output reg [15:0] out );

integer num_calls;
initial num_calls = 0;
Initial statement

integer multiplier;
integer result; Variables of type integer
always @(*)
begin

multiplier = in;
result = 1;
while ( multiplier > 0 )
begin
result = result * multiplier; Data dependent while loop
multiplier = multiplier - 1;
end

out = result;
num_calls = num_calls + 1;
end

endmodule
79

Delay Statements

module mux4
(
input a,
input b,
input c, Although this will add a delay for simulation,
input d, these are ignored in synthesis
input [1:0] sel,
output out
);

wire #10 t0 = ~( (sel[1] & c) | (~sel[1] & a) );

wire #10 t1 = ~( (sel[1] & d) | (~sel[1] & b) );
wire #10 out = ~( (t0 | sel[0]) & (t1 | ~sel[0]) );

endmodule

80
# Time Control
 $time
 A built-in variable that represents simulated time
 a unitless integer
 $display($time, “a=%d”, a);

 # Time Control
 #<number> statement
 statement is not executed until <number> time units have
passed
 control is released so that other processes can execute
 used to model propagation delay in combinational logic

81

System Tasks
 System tasks are used for test harnesses and simulation management

reg [ 1023:0 ] exe_filename;

Initial begin
/* To enable all the features of vcs, put the following statement
at the very beginning of your "initial" block. */
$vcdpluson( ); //allows all signals to be visible in the simulation.

// This gets the program to load into memory from the command line
if ( $value$plusargs( "exe=%s", exe_filename ) )
$readmemh( exe_filename, mem.m );
else
begin
$display( "ERROR: No executable specified! (use +exe=<filename>)" );
$finish;
end

// Stobe reset
#0 reset = 1;
#38 reset = 0;

end

82
Which Abstraction is the Right One?

High-Level Behavioral Designers usually use a mix of

all three! Early in the design
process they might use mostly
behavioral models. As the
design is refined, the behavioral
Register Transfer Level
models begin to be replaced by
dataflow models. Finally, the
designers use automatic tools to
synthesize a low-level gate-level
Gate Level model.

A common approach is to use C/C++ for initial

behavioral modeling, and for building test rigs.

83

Take Away Points

 Structural Verilog enables us to describe a hardware
schematic textually
 Verilog can model hardware at three levels of abstraction:
gate level, register transfer level, and behavioral
 Understanding the Verilog execution semantics is critical
for understanding blocking and non-blocking
assignments
 Designers must have the hardware they are trying to
create in mind when they write their Verilog

84
Interview Question: which is better?

A D
C
B

2x the
processes clk Combinational
= 2x the & sequential
complexity logics are not
separated.

assign D = A & B;
always @ (posedge clk)
always @ (posedge clk) begin
begin C <= A & B;
C <= D; end
end

85

Announcements
 Homework #4 (Due: Next Week)
 Textbook Problems : 2.1, 2.2, 2.4, 2.6, 2.7

86