IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO.

8, AUGUST 1995 847

1-V Power Supply High-speed Digital Circuit

Technology with Multithreshold-Voltage CMOS
Shin’ichiro Mutoh, Member, IEEE, Takakuni Douseki, Member, IEEE, Yasuyuki Matsuya, Member, IEEE,
Takahko Aoki, Member, IEEE, Satoshi Shigematsu, Member, IEEE, and Junzo Yamada, Member, IEEE

Abstruct- 1-V power supply high-speed low-power digital However, it is generally rather difficult to reduce the supply
circuit technology with 0.5-pm multithreshold-voltage CMOS voltage to 1 V. The drastic degradation in speed is the largest
(MTCMOS) is proposed. This technology features both low- problem. Although several studies of high-speed 1-V operating
threshold voltage and high-threshold voltage MOSFET’s in a
single LSI. The low-threshold voltage MOSFET’s enhance speed DRAM’S have been reported [ 3 ] , [4], they seem difficult to
Performance at a low supply voltage of 1 V or less, while the apply to general logic circuits because they assume stand-by
high-threshold voltage MOSFET’s suppress the stand-by leakage node voltages throughout the entire circuit are predictable in
current during the sleep period. This technology has brought memory LSI’s, and utilization of the conventional layout CAD
about logic gate characteristics of a 1.7-11s propagation delay tool is thought to be difficult. Therefore, the development of
time and 0.3-pW/MHz/gate power dissipation with a standard
load. In addition, an MTCMOS standard cell library has been novel circuit technology that achieves high-speed operation
developed so that conventional CAD tools can be used to lay out at a low voltage of 1 V with only a single battery drive
low-voltage LSI’s. To demonstrate MTCMOS’s effectiveness, a and can be easily applied to random logic circuits is the key
PLL LSI based on standard cells was designed as a carrying to developing the LSI designs for mobile equipment in the
vehicle. 18-MHz operation at 1 V was achieved using a 0.5-pm multimedia era.
CMOS process.
This paper proposes just such a new 1-V high-speed circuit
technology that is applicable to all digital CMOS circuits
[5]. We call it multithreshold-voltage CMOS (MTCMOS). Its
I. INTRODUCTION
unique feature is that it uses both high- and low-threshold

A low-power design is essential to achieve miniaturiza-

tion and long battery life in battery-operated portable
equipment. Recently, there has been rapid progress in per-
voltage MOSFET’s in a single chip. In the next section, key
issues in low-voltage operation are discussed. The MTCMOS
technology and its main characteristics are described in Section
sonal communications service (PCS) based on battery drives, 111. In Section IV, layout schemes based on a standard cell and
including digital cellular phones, personal digital assistants, chip configurations are discussed. Finally, the performance of
notebook, and palm-top computers. Future PCS will be more a PLL LSI designed and fabricated using a 0.5-pm CMOS
dedicated to multimedia systems, and thus the LSI’s, the process as a carrying vehicle for MTCMOS technology is
key component of the equipment, are desired not only for shown in Section V.
low-power consumption but also for higher signal or data
processing capability [l], [2]. In order to promote this develop-
ment, the demand for LSI designs achieving both low-power 11. DESIGNISSUES
FOR LOW VOLTAGE CMOS CIRCUITS
and high-speed performance should become stronger.
Lowering the supply voltage is the most effective way to A. Low-Voltage Operation
achieve low-power performance because power dissipation in Power dissipation in digital CMOS circuits is approximately
digital CMOS circuits is approximately proportional to the expressed as
square of the supply voltage. From the point of view of
applications to battery-powered mobile equipment, the supply
voltage should be set at 1 V [l]. 1-V operation enables direct
battery drive by a single Ni-Cd or Ni-H battery cell even taking
the cell’s discharge characteristic into account. This provides where CL is the load capacitance, V d d is the supply voltage,
the smallest size and lightest weight equipment and eliminates and f o p is the operating frequency. According to this formula,
the need for a power wasting dc-to-dc voltage converter. lowering V d d is the most effective way to reduce power
dissipation because it is proportional to the square of V d d .
Fig. 1 shows the relation between power consumption and
Manuscript received April 25, 1994; revised December 21, 1994.
S . Mutoh, T. Douseki, Y. Matsuya, S. Shigematsu, and J. Yamada are with supply voltage. It is apparent that lowering V d d contributes
High-speed Integrated Circuits Laboratory, NTT LSI Laboratories, Kanagawa significantlyto power reduction. Reducing supply voltage from
243-01, Japan. the 3.3 V, widely used at present, to 1 V realizes about 1/10
T. Aoki is with Project Team-4, NTT LSI Laboratories, Kanagawa 243-01,
Japan. the power dissipation. Certainly, scaling down CL or fop in
IEEE Log Number 9412024. (1) also contributes to low-power operation. Decreasing capac-
0018-9200/95$04.00 0 1995 IEEE
848 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 8, AUGUST 1995

8.0 . , . , . , . , 1 , . , . ,
7 10E6

!
10E5
1 OE4

1 OE3
1 OE2
10E1
IOEO
10E-1
0.8
10E-2
SUpply Voltage Vdd M
Threshold Voltage Vth [VI
Fig. 1. Relation between power consumption and supply voltage.
Fig. 2. Gate delay time and subthreshold leakage current dependence on
threshold voltage.
itance CL, however, would be difficult without scaling down
the device and wiring, and higher throughput performance
usually requires an increase in frequency f o p . Although there a MOSFET Is& at VGS = 0 is expressed as
have been attempts to lower f o p by introducing parallel
processing, this approach generally increases hardware over- -&h
head and requires extensive reworking at an architecture or Isub exp (qm) (3)
algorithm design level [2].
where Vth is the threshold voltage of a MOSFET, and is s
B. Key Issue for Low-Voltage Operation subthreshold swing. Leakage current characteristics at a V,d
Although lowering Vdd to 1 v is effective in lowering power of 1 V are also shown in Fig. 2. These values are calculated
dissipation, as previously described, it is generally difficult s
assuming is 85 mvldecade. As Vth is reduced by 0.1 V, I s U b
because the speed performance is dramatically reduced at becomes about ten times larger. This becomes the source of
lower voltages. In CMOS digital circuits, the gate delay time the large stand-by current. With respect to portable equipment,
(tpd) is approximately given by in particular, the stand-by period is generally much longer
than the operating period. Therefore, an increased stand-by
current wastes battery power seriously. That is why it has
been difficult to satisfy the requirements for both high-speed
and low stand-by power at a low supply voltage of 1 V.
where CL is the load capacitance, IDS is the drain current
in the saturation region, Vdd is the supply voltage, Vth is 111. MTCMOS CIRCUITTECHNOLOGY
the MOSFET’s threshold voltage, and A is a constant. In the
above expression, lowering the supply voltage decreases IDS A. Basic Circuit Scheme
proportional to the square of the voltage difference Vdd - Vth, The new MTCMOS circuit technology is proposed to satisfy
which results in a drastic increase in gate delay time as Vdd both requirements of lowering the threshold voltage of a
approaches Vth. MOSFET and reducing stand-by current, both of which are
Until now, supply voltage has generally been lowered by necessary to obtain high-speed low-power performance at a
scaling down the device feature size to ensure the reliability of Vdd of 1 v .
thin gate oxides [6], [ 7 ] .Speed performance is maintained even This technology has two main features. One is that N-
at low voltage due to the improvement in transconductance channel and P-channel MOSFET’s with two different thresh-
gm brought about by shrinking feature size to a half or old voltages are employed in a single chip. The other one
deep submicron size. Considering the increasing demand for is two operational modes, “active” and “sleep,” for efficient
extremely low-power operation, however, much lower voltage power management.
should be applied to devices in the same generation. In this Fig. 3 shows the basic MTCMOS circuit scheme with the
case, a decrease in delay time at lower voltage must be NAND gates. The logic gate is composed of MOSFET’s with
achieved without relying on device feature size scaling. a low threshold voltage of about 0.2-0.3 V. Its power terminals
One way to overcome the speed degradation problem is to are not connected directly to the power supply lines VDD and
reduce the Vth of a MOSFET, as seen clearly in (2). Fig. 2 GND, but rather to the “virtual” power supply lines VDDV
shows the circuit characteristics dependence on Vth. As Vdd and GNDV. The real and virtual power lines are linked by
gets lower from 2 to 1 V, gate delay time t p d becomes MOSFET’s Q1 and Q2. These have a high threshold voltage of
more sensitive to Vth. Therefore, reducing Vth is effective about 0.5-0.6 V and serve as sleep control transistors. Signals
to achieve high-speed operation at a Vdd of 1 V. As Vth SL and E,which are connected to the gates of Q1 and Q2,
is reduced, however, another significant problem emerges-a respectively, are used for activelsleep mode control. Circuit
rapid increase in stand-by current due to changes in the operation in each mode at a supply voltage of 1 V is described
subthreshold leakage current. Subthreshold leakage current of below.
MUTOH et 01.: 1-V POWER SUPPLY HIGH-SPEED DIGITAL CIRCUIT TECHNOLOGY 849

,1.1
......Conv.
................ H-Vth

Low-Vth Tr

D i l XI cv1
v
--f CVlC0=5
Low-Vth gate
.. ...
High-Vth Tr
ra
Hlgh-Vthgate 1 g@
I GNDV
LVth
Ix cv2
1.o
0 2 4 6 8
Normalized aate width W H N L
1 0

* (a) (b)
Fig. 4. Gate delay time and effective supply voltage dependence on the
Fig. 3. MTCMOS circuit scheme. normalized gate width of the sleep control transistor. (a) Simulation results.
(b) Simulation circuit model.
In the active mode, when SL is set low, Q1 and 4 2 are
turned on and their on-resistance is so small that VDDV and " " " " " " '
5.0
GNDV function as real power lines. Therefore, the NAND conv. CMOS
gate operates normally and at a high speed because the Vth of 4.0 - d
, (full H-Vth)

0.3 V is low enough relative to the supply voltage of 1 V. c

NAND gate
In the sleep mode, when SL is set high, Q1 and 4 2 are 5c 3.0 -
turned off so that the virtual lines VDDV and GNDV are
-(U
MTCMOS F.O. = 3
AI : 1 mm

assumed to be floating. The relatively large leakage current, E 2.0 -

determined by the subthreshold characteristics of low-vth -m"

0" 1.0 -
MOSFET's, is almost completely suppressed by Q1 and 4 2 conv. CMOS
since they have a high Vth and thus a much lower leakage (full L-Vth)

current. Therefore, power consumption during the stand-by 0.5 1.o 1.5 2.0
Supply Voltage (V)
period can be dramatically reduced by the sleep control.
It should be pointed out that two other factors affect the (a)
speed performance of an MTCMOS circuit. One is the size
of the sleep control transistors Q1 and 42, and the other is 1.61 . . . . , . . . . , . . . . ,
the capacitances CV, and Cv2 of the virtual power lines. NAND gate
F.O. = 3
Q1 and 4 2 supply current to the virtual lines. The larger A L 1 mm
their gate widths are designed, the smaller the on-resistance (full H-Vth)

becomes. Cvl and Cv2 also act as temporary supply sources

to internal logic gates. Thus, the voltage rise in GNDV and
drop in VDDV caused by the switching of the internal logic
gate are suppressed by setting them large enough to maintain
high-speed performance. 0.4
0
To confirm the effects, simulations were carried out. Fig. 4 = 0.2
0.5 1.o 1.5 2.0
shows the gate delay time tpd and effective supply voltage Supply Voltage M
V e f fdependence on the normalized gate width of sleep control (b)
transistors WH/WL along with the simple single MTCMOS
Fig. 5. MTCMOS performances. (a) Gate delay time. (b) Normalized power
circuit model used for simulations, where Veff is defined as delay product dependence on supply voltage.
the minimum value of spontaneous voltage difference between
VDDV and GNDV (between node a and b in this simulation).
It is clear that larger CV, virtual line capacitance, and W H , B. Electrical Performance
sleep control transistor width, maintain the effective supply
voltage Veff for the internal logic gates and enhance the The measured MTCMOS logic gate delay time is shown
speed performance. For instance, a WH/WL of 5 and Cv/Co in Fig. 5(a) as a function of supply voltage. Data for the
of 5 keep the decrease in Veff within 10% of V& and the conventional full high-Vth and full low-& CMOS logic gates
degradation in gate delay time within 15% compared to a are also plotted for comparison. It is obvious that the voltage
pure low-Vth CMOS. The area penalty for the wider gate dependence of an MTCMOS gate delay is much smaller than
transistors is relatively small because they are shared by all that of a conventional CMOS gate with high-& and that the
the logic gates on a chip. As for CV, the above condition is MTCMOS gate operates almost as fast as the full low-&
generally met in an actual LSI because CV includes the source gate. At a 1-V power supply, the MTCMOS gate delay time
capacitances of all the logic gates connected to virtual power is reduced by 70% as compared with the conventional CMOS
lines and wiring capacitances. Therefore, nothing extra need gate with high-Vth. The dependence of normalized power-
be added. delay product (NPDP) on supply voltage is shown in Fig. 5(b),
850 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 8. AUGUST 1995

TABLE I
CHARACTERISTICS
OF MTCMOS CIRCUIT
TECHNOLOGY
C o w .CMOS
AL:l mm
Power supply voltage 1.ov
Propagation delay time 1.7 nsigate
Power dissipation 0.3 pWiMHzlgate
(2-input NAND with F.O.=3, line = 1 mm)

VDD v-
0.8 1.0 1.2 1.4 1.6
Supply Voltage [VI
VDD 7
Fig. 7. Latch circuit delay time dependence on supply voltage.

mode, when the clock signal CLK is fixed by using the

sleep control signal SL. G3 is designed to be smaller to
suppress both the increases in the gate delay time and the
Y area.
(a) (b)
2) As for the forward path, the inverter G1 and the CMOS-
type transmission gate TG are composed of low-V+h MOS-
Fig. 6. MTCMOS latch circuit. (a) The proposed circuit. (b) The problem
of the leakage current path. FET’s. This makes high-speed operation possible at 1-V power
supply. This circuit also includes local sleep control transistors
QL1 and QL2 with high-Vth. The reason for including them
where power consumption is normalized by frequency. At low can be understood with Fig. 6(b), where a node N1 is assumed
voltages, especially below 1.5 V, the NPDP of the MTCMOS to maintain a “low” state in the sleep mode. If G1 were
is much less than that of the conventional high-& gates, connected directly to the virtual power line VDDV, as shown
reflecting the improved speed performance at lower voltage. in this figure, VDD and VDDV would be short through MI
The smallest NPDP is achieved around 1 V in the MTCMOS and M3, so that stand-by current would be increased in the
gates. This shows that power reduction effect proportional to sleep mode. Therefore, QL1 and QL2 are indispensable for
the square of supply voltage overcomes speed degradation in completely cutting the leakage current path. Fig. 7 shows the
low-voltage operation. In addition, it was confirmed that the simulation results for the delay time of the MTCMOS latch
stand-by current was reduced three or four orders of magnitude circuit. They confirm that the delay time is reduced by 50%
due to the sleep control. at 1 V compared with that of the conventional circuit with
From these results, it is clear that MTCMOS circuit technol- high-Vth. Furthermore, the stand-by current in the sleep mode
ogy achieves both high-speed and low-power operations at a was also confirmed to be almost as low as that of the high-Kh
low supply voltage of 1 V or less. The measured characteristics circuit.
related to this circuit technology are summarized in Table I. At
1 V, NAND gate delay time is typically 1.7 ns per gate, and IV. CHIP LAYOUTSCHEME
power consumption is 0.3 pW/MHz per gate with a standard In order to make this low-voltage technology practical,
output load of three fanouts and 1 mm of wiring. MTCMOS conventional CAD tools must be applicable to lay out an
gate operates about three times faster than conventional 0.5- MTCMOS LSI easily without any special consideration of
pm CMOS gate. Power dissipation of 0.3 pW/MHz is 1/10 of the particular circuit scheme. To meet this requirement, the
the power needed for 3-V operation. MTCMOS standard cell library was developed.
Fig. 8 shows the MTCMOS layout scheme based on a
standard cell. The main feature is that the extra components of
C. Design of Flip-Flop Circuit the MTCMOS circuit are buried in the cells. More specifically,
Special attention must be paid to the MTCMOS design of the virtual power supply lines (VDDV and GNDV) and the
latch or flip-flop circuits that have memory functions. This sleep control signal line (SL) are buried in each cell, while the
is because memorized data in latch or flip-flop circuits must sleep control transistors Q1 and Q2 with high-Vth are buried in
be retained even in the sleep mode when virtual power lines the power supply cell that provides the area needed to connect
are floating to cut leakage current completely. The proposed the true and virtual power supply lines to each other in the II’
MTCMOS latch circuit is shown in Fig. 6(a), which is used and y directions. Power supply cells are placed on both sides
for flip-flop circuits. The features are described below. of the logic cell based core. The true power supply lines VDD
1) A conventional inverter G2 and a newly added one G3 and GND, which are also placed in each cell, fix the voltage
are composed of high-Kh MOSFET’s. They are connected of either the substrate or the well and supply current to flip-
directly to the true power supply lines VDD and GND. The flop circuits. This layout scheme allows the extra MTCMOS
latch path consists of G2 and G3, which are always provided components to be connected automatically throughout the chip
with power. Therefore, data can be retained even in the sleep by abutting cells with a minimum increase in chip area.
 ~

MUTOH ef al.: I-V POWER SUPPLY HIGH-SPEED DIGITAL CIRCUIT TECHNOLOGY 85 1

Power Suwly Cell MiCell Power Suwlv Cell

...

... 1.o
0 10 20 30 40 50 60
S.O.R. [%I

(a) (b)
Fig. 10. Influences of virtual power supply lines. (a) Simulation circuit
Fig. 8. Chip layout scheme based on a standard cell. model. (b) Gate delay time versus SOR.

TABLE 11
DEVICETECHNOLOGY

High-Vth Tr Low-Vth Tr

f&@ Gate length

Gate oxide thichness
0.55 p
110 A
0.65 pm
IIOA
N-channel : Vth 0.55 v 0.25 V
CLK
P-channel : Vth -0.65 V -0.35 V

with the circuit model. Here, the SOR is defined as m/n,

where m and n indicate the number of operating logic blocks
and the total number of blocks, respectively, assuming a 2-
‘g 2.5 -
mm block width. As the SOR increases, the voltage on VDDV
drops because Q1 has to supply more current to VDDV at one
.E time. For similar reasons, the voltage also rises on GNDV.
2 2.0.
-m These voltage changes cause the effective supply voltage V e f f
D
g
W
1.5 between VDDV and GNDV to decrease, extending gate delay
time. Generally, however, the SOR is expected to be at most
.O h 7 - Y - r d : O i5 20 or 30%. In this region, the reduction of V e f fis less than
SOR [%I 15% of the supply voltage, and the speed performance of 1.7
(b) ns/gate is still quite high.
Fig. 9. Gate delay time and effective supply voltage dependence on One way to further decrease the dependence of speed
Switch-On-Rate (SOR). (a) Simulation circuit model. (b) Gate delay time performance on the SOR is to use a sleep control transistor
and effective supply voltage versus SOR. with a wider gate. This is, however, a trade-off between speed
and stand-by current because total stand-by current in a chip
is approximately given by ~ K W H I H . K is the number
Here,
Because Q1 and 4 2 can be placed just under the power of rows in the block shown in Fig. 8, while W H is the gate
supply lines in the power supply cell, their insertion would
width of the sleep control transistor, and IH is its leakage
incur no area penalty. Furthermore, the virtual power lines
current when the gate’s width and length are equal. Another
VDDV and GNDV in each row are connected together so that
effective way to decrease this dependence is to remove one
one cell can be supplied current through all the sleep control set of the two sleep control transistors and virtual power lines.
transistors within the chip, which contributes to suppress speed The expected improvements in speed are shown in Fig. 10
degradation. along with simulation circuits. By removing of GNDV (b-1)
In this experiment, W H the
, poly-gate width of sleep control and VDDV (b-2), gate delay time can be reduced by 15-25%
transistors Q1 and 4 2 in a power supply cell, was design compared with the basic scheme. The removal of VDDV is
to be ten times larger than that in the logic cells (WL).Q1
clearly more effective in increasing speed. The reason for this
and 4 2 are shared by all the logic gates connected to the is that the threshold voltage of the P-channel MOSFET (Ql)
virtual power lines in this scheme. Therefore, the simultaneous
was designed to be higher than that of the N-channel one
switch-on rate (SOR), which indicates how many logic gates (Q2) in this study (see Table 11).
are switched on at almost the same time, seems to affect speed
performance, especially in MTCMOS circuits. The amount of
current supplied through Q1 and Q2 depends on the switching v . TEST CHIP RESULTS
probability of the internal logic gates. Thus, a high SOR
enhances the voltage drops at Q1 and Q2, which consequently A. Process and Device Technology
reduces the effective supply voltage between VDDV and To confirm the effectiveness of MTCMOS circuit technol-
GNDV. Fig. 9 shows the simulation results for the SOR along ogy, a PLL LSI using new MTCMOS standard cells was
852 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 8, AUGUST 1995

0” ’ ’ I
0.5 1 .o 1.5 2.0
Supply Voltage M

Fig. 12. Operation frequency of the PLL chip.

Fig. 11, Microphotograph of the PLL chip. Supply Voltage M

Fig. 13. Power dissipation of the PLL chip versus supply voltage.
TABLE 111
AREA PENALTY
FACTOR

Combinational Circuit 1.1

Sequential Circuit 2.0
PLL LSI Digital Core 1.3

designed and fabricated. Conventional 0.5-pm CMOS process

technology for 3.3-V operation with single-polysilicon and
double-metal layers was used. MOSFET’s with different I&’s
in the same well were formed by optimizing the impurity
concentration in the well and controlling the channel doses
with two additional masks, which minimizes the increase
’ (F)c50nA

lonlk 10k
-.
lOOk 1M 10M
Operation frequency (Hz)
IOOM

Fig 14. Power dissipation of the PLL chip versus operation frequency
in the number of process steps. The key device parameters
and characteristics are summarized in Table II. The gate period, the area penalty can be further reduced by appropriately
length of the low-Vth MOSFET is 0.65 pm, which is 0.1 combining the use of a conventional DFF and the DFF with
pm longer than that of the high-& ones. This is preferable a special memory function.
to suppress variations in the threshold voltage due to short-
channel effects. The gate oxide thickness is 110 8, for both
types of MOSFET’s. The low-Vth’s are 0.25 V for N-channel B. Chip Pegormame
and -0.35 V for P-channel MOSFET’s. Fig. 12 shows the measured operation frequency as a func-
A microphotograph of the PLL chip is shown in Fig. 11. tion of supply voltage. At 1 V, the chip operates at 18 MHz
This chip consists of about 5 K gates, including the automatic which is sufficient for many applications.
frequency control circuit and the intermittent operation con- Fig. 13 shows the power dissipation in the digital core as a
troller [ 8 ] . The whole chip is 4 x 5 mm2, and the digital core function of supply voltage at an operation frequency of 12.8
is about 2 x 2 mm2. Table 111 lists the area penalty factors MHz. The power dissipation of the conventional 5-V operation
in this study. An MTCMOS combinational circuit cell has an PLL is also plotted for comparison. At 1 V, power dissipation
area about 10% larger than a conventional cell does owing is drastically reduced to below 1/20 compared with that of the
to the insertion of virtual supply lines and the sleep control conventional LSI operated at 5 V.
line. A sequential circuit cell, such as an MTCMOS DFF with Fig. 14 shows another aspect of the power perfor-
clear, needs an area about twice that of a conventional cell in mance-the operating current versus the operating frequency
order to store data even in the sleep period. The area increase for the worst case at a supply voltage of 1.2 V. Although the
for the whole digital core, however, is only 30% in spite of operating current is proportional to the frequency in the region
the fact that the DFF’s occupy a relatively large part (about over 1 MHz, it becomes almost constant in the low-frequency
50%) of the total gate counts. This is because the channel region. This is due to the leakage current caused by using
area is almost unchanged. Moreover, because all DFF’s in low-Vth MOSFET’s. In the active mode, the leakage current
an actual LSI aren’t expected to hold the date during sleep of about 30 pA in this chip is negligible because it is less
MUTOH et al.: 1-V POWER SUPPLY HIGH-SPEEDDIGITAL CIRCUIT TECHNOLOGY 853

TABLE N Shin’ichiro Mutoh (M’93) was born in Tokyo,

CHARACTERISTICSOF THE PLL CHIP Japan, on October 12, 1963. He received the B.E.
and M.E. degrees in electronic engineering from
Chiba University, Chiba, Japan, in 1986 and 1988,
Power supply voltage 1.ov
2.4” x 2.3 nun respectively.
Core size
18 MHz In 1988, he joined Nippon Telegraph and
Cycle frequency
Power dissipation Telephone Corporation (“IT), Tokyo, Japan. Since
200 FW (at 10 M H z ) 1988, he has been engaged in the research and
Stand-by current < 50 nA
Turn-on time development of 1-V operating logic and memory
< 500 ns circuit technology. He is now with the High-
Gate counts 5 K gates Speed Integrated Circuits Laboratory, “IT LSI
Laboratories, Kanagawa, Japan.
Mr. Mutoh is a member of the Institute of Electronic, Information, and
Communication Engineers of Japan.
than 1/10 of the dynamic current consumption at a desired
operating frequency of over 10 MHz. In the sleep mode, on
the other hand, the current is dramatically reduced to below
50 nA, so that low stand-by characteristics can be obtained.
Typical PLL LSI features are summarized in Table IV. The Takakuni Douseki (M’93) was born in Fukui,
turn-on time, which is the time needed to switch from sleep Japan, on January 12, 1958. He received the B.S.
and M.S. degrees in electrical engineering from
to active mode, is less than 500 ns even in the worst case. Fukui University, Fukui, Japan, in 1980 and 1982,
respectively.
In 1982, he joined the Musashino Electrical
VI. CONCLUSION Communication Laboratory, Nippon Telegraph and
Multithreshold-voltage CMOS (MTCMOS) circuit technol- Telephone Public Corporation (“IT),where he
worked on the design of static MOS memory. He
ogy has been proposed as a way to achieve a 1-V supply is currently a senior research engineer with ”IT
voltage high-speed and low-power LSI operation. This tech- LSI Laboratories, Kanagawa, Japan, where he is
nology uses MOSFET’s with two different threshold voltages engaged in research on the scaled-down BiCMOS, CMOS, and bipolar
circuits.
on a single chip and introduces a sleep control scheme for effi- Mr. Douseki is a member of the Institute of Electronic, Information, and
cient power management. Low-threshold voltage MOSFET’s Communication Engineers of Japan and the Japan Society of Applied Physics.
improve the speed performance at a low supply voltage of
1 V, while high-threshold MOSFET’s suppress the stand-
by power dissipation. In addition, a standard cell library
has been developed to simplify low-voltage LSI designs. To
demonstrate the effectiveness of this technology, a PLL LSI Yasuyuki Matsuya (M’87) was born in Aomori,
Japan, on February 14, 1956. He received the B.E.
based on standard cells was designed as a carrying vehicle degree in electronic engineeringfrom Iwate Univer-
using a 0.5-pmCMOS process. High-speed operation of 18 sity, Iwate, Japan, in 1978.
MHz at 1 V confirmed the validity of this new technology. In 1978, he joined the NTT Electrical Commu-
nications Laboratories in 1978, where he worked
on the design of high resolution AID and D/A
ACKNOWLEDGMENT converters. He is currently with the High-speed In-
tegrated Circuits Laboratory, “IT LSI Laboratories,
The authors would like to thank S. Horiguchi, E. Arai, N. Kanagawa, Japan. He has been engaged in research
Ieda, and K. Imai for their suggestions and encouragement. on the low voltage power supply AID and D/A
conversion technology.
Mr. Matsuya is a member of the Institute of Electronic, Information, and
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for portable systems,” in ZSSCC Dig. Tech. Papers, pp. 168-169, Feb.
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P I A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low-power
CMOS digital design,” IEEE J. Solid-State Circuits, vol. 27, pp.
473484, Apr. 1992. Takahiro Aoki (M’85) was born in Nagoya, Japan,
[31 M. Horiguchi, T. Sakata, and K. Itoh, “Switched-source-impedance on November 25, 1955. He received the B.S. and
CMOS circuit for low standby subthreshold current giga-scale LSI’s,” M.S. degrees in electrical engineeringfrom Nagoya
ZEEE J. Solid-state Circuits, vol. 28, pp. 1131-1135, Nov. 1993. University, Nagoya, Japan, in 1978 and 1980, re-
r41 T. Kawahara, M. Horiguchi, Y. Kawajiri, G Kitsukawa, T Kure, and spectively.
M. Aoki, “Subthreshold current reduction for decoded-driver by self- From 1980 to 1983, he was with the Musashino
reverse biasing,” IEEE J. Solid-state Circuits, vol. 28, pp. 1136-1 144, Electrical Communication Laboratory,Nippon Tele-
Nov. 1993. graph and Telephone Public Corporation (“IT),
r51 S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, and J. Yamada, “1-V high- Tokyo, Japan. In 1983, he joined the “IT Atsugi
speed digital circuit technology with 0.5-pm multi threshold CMOS,” Electrical Communication Laboratory (now, “IT
in Proc. IEEE Znt. ASIC Conj, Sept. 1993, pp. 186-189. LSI Laboratories) Kanagawa, Japan. He has been
r61 K. Shimohigashi and K. Seki, “Low-voltage ULSI design,” ZEEE J. engaged in the research and development of the CMOS logic LSI design,
Solid-state Circuits, vol. 28, pp. 408-413, Apr. 1993. latch-up modeling and characterization,half-micron CMOSlBiCMOS device
r71 SIA Semiconductor Technology: Workshop Working Group Reports, Nov. design, and 1-V operated low power CMOS process/device design. His present
1992. research interests include CMOS device characterization and technology-
@I M. Ishikawa, N. Ishihara, A. Yamagishi, and I. Shimizu, “A miniaturized CAD.
low-power synthesizer module with automatic frequency stabilization,” Mr. Aoki is a member of the Institute of Electronics, Information, and
in Proc. ZEEE VTC, 1992, pp. 752-755. Communication Engineers of Japan.
854 IEEE JOURNAL OF SOLID-STATECIRCUlTS,VOL. 30, NO. 8, AUGUST 1995

Satoshi Shigematsu "93) was bom in Tokyo, Junzo Yamada (M'86) was bom in Nagoya, Japan,
Japan, on August 2, 1967. He received the B.S. and on April 3, 1951. He received the B.E. and M.S.
M.E. degrees in system engineering from Tokyo degrees in electronic engineering and the Ph.D.
Denki University, Tokyo, Japan, in 1990 and 1992, degree in computer science from Tokyo Institute
respectively. of Technology, Tokyo, Japan, in 1974, 1976, and
In 1992, he joined Nippon Telegraph and 1990, respectively.
Telephone Corporation (NTT), Tokyo, Japan. Since In 1976, he joined the Musashino Electrical
1992, he has been engaged in the research and Communications Laboratory, Nippon Telegraph
development of low voltage, low-power CMOS and Telephone (N'IT) Public Corporation, Tokyo,
circuit. He is now with the High-speed Integrated Japan, where he worked on the design and testing of
Circuits Laboratory, N l T LSI Laboratories, fault tolerant DRAM. He is currently a Low-Voltage
Kanagawa, Japan. Integrated Circuits Research Group Leader with the High-speed Integrated
Mr. Shigematsu is a member of the Institute of Electronic, Information, Circuits Laboratory, NTT LSI Laboratories, Kanagawa, Japan. He has been
and Communication Engineers of Japan and Information Processing Society engaged in research on 1-V CMOS circuit technology including memories
of Japan. and A/D converters.
Dr. Yamada is a member of the Institute of Electronic, Information, and
Communication Engineers of Japan.