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Gadawe NT, Hamad RW, Qaddoori SL. Efficient Implementation of Fractional Sampling Rate Conversion (SRC) on FPGA.. Diagnostyka.
2025;26(3):2025308. https://doi.org/10.29354/diag/208854.

e-ISSN 2449-5220
DIAGNOSTYKA, 2025, Vol. 26, No. 3
DOI: 10.29354/diag/208854
1

EFFICIENT IMPLEMENTATION OF FRACTIONAL SAMPLING RATE

CONVERSION (SRC) ON FPGA

Noor Talal GADAWE , Rasha Waleed HAMAD , Sahar Lazim QADDOORI *

Electronic Engineering Department, Electronics Engineering College, Ninevah University,
Mosul 41005, Iraq
*
Corresponding author Email: sahar.qaddoori@uoninevah.edu.iq

Abstract
Field Programmable Gate Arrays (FPGAs) include versatile features, which make them useful for use in
Digital Signal Processing (DSP)-based systems that require high levels of performance. This paper introduces
hardware implementation of decimator (M), Interpolator (L), and Sample Rate Conversion (SRC) by factor
L/M, using different structure realizations (direct, efficient, and polyphase). Initially, a digital low-pass Finite
Impulse Response (FIR) filter is designed using the Remez algorithm for filter coefficient calculation and
realized with a decimator (M=2), an Interpolator (I=5), and SRC (5/2). These design structures are implemented
using Xilinx Simulink blocks on the Artix 7 (XC7A-1csg324) FPGA development board. In the decimator, the
polyphase structure represents the best design in terms of resource utilization, such as registers, Look Up Table
(LUT), flip-flops, total real-time, memory usage, and multiplexers, while the direct structure consumes more
resources. The same results are in the Interpolator. For SRC, it can be noted that the efficient design with linear
phase is better in terms of device utilizations, while the direct structure is best in the number of unique control
sets and number of multiplexers.

Keywords: Finite Impulse Response (FIR), SRC, decimator, interpolator, polyphase structure

List of Symbols/Acronyms A multirate system employs interpolators with an

integer factor L and decimators with an integer factor
FPGA – Field Programmable Gate Arrays; M. When these two elements are there, the result is
DSP –Digital Signal Processing; an SRC system where the sampling rate is changed
M –Decimator;
L –Interpolator;
by a rational factor L/M. as declared in Figure 1. The
SRC –Sample Rate Conversion; filtering operation is required to avoid imaging and
FIR –Finite Impulse Response; aliasing. This operation is illustrated in Figure 1(a),
LUT –Look Up Table; where the input signal x(n) is first upsampled by a
LPF – Low Pass Filter. factor L and then filtered using a low-pass
interpolation filter LPFL (denoted as HL(z)). After
1. INTRODUCTION the interpolation operation, the signal passes through
a low-pass antialiasing filter LPFM (HM(z)) and is
The process of changing the effective sample rate subsequently downsampled by factor M. As a result,
of a discrete-time signal is known as Sample rate the output signal x(m) has a sampling rate that is L/M
conversion. In real-time processing, the Sample Rate times the original signal x(n) [5]. In practice, since
Converter (SRC) is vital to exchange digital data both HL(z) and HM(z) work at the same sampling
between two hardware modules working at altered rate, they can be combined and replaced with a single
sample rates [1]. low-pass filter H(z), as illustrated in Figure 1(b).
The conversion of a signal from one sample rate This filter has stopband edge frequency ωs to remove
to another is referred to as fractional sampling rate imaging, at the same time addressing the aliasing
adjustment or resampling. This technique is utilized issue arising from decimation [6,7].
widely for various applications such as speech, The FPGA-based architecture offers a low
digital audio, radar, communication systems, and development cost, along with great flexibility and
antenna systems, where each of them works at a functionality, and can be developed with a faster
different sampling rate [2,3,4]. time to market [8,9]. However, the implementation
of DSP algorithms on FPGA encounters several

Received 2025-01-10; Accepted 2025-07-31; Available online 2025-08-02

© 2025 by the Authors. Licensee Polish Society of Technical Diagnostics (Warsaw. Poland). This article is an open access article distributed
under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).
2 DIAGNOSTYKA, Vol. 26, No. 3 (2026)
Gadawe NT, Hamad RW, Qaddoori SL.: Efficient Implementation of Fractional Sampling Rate Conversion …

basic issues, such as determining the sampling rates Comb (CIC) filter. This system is tested on an Altera
and computational complexity of several FPGA development board.
applications [10]. Due to the use of FPGA in the Ali. Zeineddine et al. [14] studied the hardware
implementation of SRC devices, they are highly realization of Arbitrary Sample Rate Conversion
flexible for frequency and phase shifting as well as (ASRC) by variable fractional delay filter (V-FDF)
superior in high realizations [11]. constructions. The authors compared the
employment of altered lately suggested V-FDF
choices based on Newton for Hermite interpolation
and Farrow structures. The implementation was
done on both FPGA and Application-Specific
Integrated Circuit (ASIC).
Dhandapani Vaithiyanathan et al. [15] proposed
the design of cascaded stages of a multirate linear
phase FIR filter. Different architectures are
considered, namely polyphase, folded pipeline,
systolic array, and Farrow architectures, with a focus
on optimizing both power and speed. The analysis
Fig. 1. Sampling Rate Conversion by L/M and synthesis are carried out using Altera Quartus-II
10.0.
The main contribution of this paper is the Jotirmayee Ghosh et al. [16] focused on the
hardware implementation of reconfigurable design and implementation of a configurable
architectures for decimators, Interpolators, and SRC Asynchronous Sample Rate Converter (ASRC) for
with different structures. To assess speed various digital audio applications. The algorithm
performance and mapped hardware resource begins by taking the input audio data and storing it
utilization on the XC7A-100TCSG324 FPGA, in Random Access Memory (RAM) and coefficients
Xilinx FPGA synthesis tools are used. The stored in a Read-Only Memory (ROM). The core of
components are realized by employing the direct, the ASRC algorithm is the implementation of
efficient and polyphase structures that were polyphase filters, which are used in faster processing
developed early, hence leading to improvements in of sample rate conversion for parallel data to ensure
area, power and speed. high-quality audio data transfer with reduced noise
This paper is organized into five sections with and improved efficiency. Shahriar Shahabuddin, et
this section as follows: Section 2 declares the al. [17] proposed an algorithm for a sample rate
related works. Section 3 presents the research converter (SRC) that is designed to handle high
method of SRC. In Section 4, the results and sample rates efficiently, particularly in embedded
discussions are done. Finally, section 5 includes the systems, while maintaining performance-limited
conclusions. clock frequencies, using polyphase SRC for
parallelized algorithms and multiphase output SRC.
2. RELATED WORKS On a Virtex-7 FPGA, the implementation of a very
large-scale integration (VLSI) structure for the dual-
SRC is a well-researched topic, as the presented phase output SRC was achieved.
literature proves, and there are many books and Swetha Pinjerla et al. [10] developed and
resources depicting its solutions. However, getting a optimized a sample rate conversion structure for
specific piece of information is not easy as each multi-standard radio application on the Virtex-6
solution is provided from a different view. XC6VCX240t-2FF484 FPGA. To avoid aliasing in
Moreover, the literature on this topic mostly lacks the downsampling operation, a 16-taps low-pass FIR
information regarding the real-life application of the filter is used. Various techniques and considerations
concept. are employed to achieve an efficient and flexible
Mahamudul Hassan et al. [12] have described a sample rate conversion process, making it suitable
direct approach to the design and implementation of for modern communication systems.
SRC with narrow passband and transition width for
converting the frequency sample rate by a factor of 3. RESEARCH METHOD
L/M equal 2/2 and 2/3. This approach was used to
provide the necessary impulses as a bio-signal, for To clarify the basic concepts of sample rate
example, Electrocardiography (EEG) signals, with converter transformations and all related structures,
an Integrated Synthesis Environment (ISE) Suite an FIR low-pass filter was taken with a stable and
14.7 and Altera Cyclone DE II FPGA board. linear phase response. The filter specifications have
Qingfeng Jing et al. [13] designed multi-rate a stopband attenuation of 30dB, a passband ripple of
digital filters, which are significant to realize multi- 0.1dB, and a filter length of 30. The Remez
rate decimation and interpolation using a Hamming algorithm is used to calculate FIR filter coefficients,
window, a half-band filter and a Cascaded Integrate- as presented in Table 1. Furthermore, Figure (2)
displays the filter’s magnitude response for the
decimator and Interpolator. The realization of the
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Gadawe NT, Hamad RW, Qaddoori SL.: Efficient Implementation of Fractional Sampling Rate Conversion …

filter can be accomplished using a decimator with (d) declares the polyphase realization of the FIR
M=2, an Interpolator with I=5, and SRC with filter.
M/I=5/2. The cutoff frequency wc (pi/2, pi/5, min
[pi/2, pi/5]) for the decimator, Interpolator, and Table 1. The Coefficients of the Proposed Filter Design
sampling rate converter, respectively. Coefficients Decimator Interpolator SRC
Magnitude Response (dB)

0 h (1) =h (30) 0.006 0.0063 0.0063

-10 h (2) =h (29) -0.0128 -0.0147 -0.0147
-20
h (3) =h (28) -0.0028 -0.0010 -0.0010
h (4) =h (27) 0.0136 -0.0028 -0.0028
Magnitude (dB)

-30

h (5) =h (26) 0.0046 0.0104 0.0104

-40

h (6) =h (25) -0.0197 0.0214 0.0214

-50
h (7) =h (24) 0.0159 0.0194 0.0194
-60
h (8) =h (23) 0.0213 -0.0003 -0.0003
0 0.1 0.2 0.3 0.4 0.5 0.6
Normalized Frequency ( rad/sample)
0.7 0.8 0.9 h (9) =h (22) -0.0349 -0.0300 -0.030
(a) Decimator h (10) =h (21) -0.0156 -0.0498 -0.0498
Magnitude Response (dB) h (11) =h (20) 0.0640 -0.0373 -0.0373
0
h (12) =h (19) -0.0073 0.0184 0.0184
-10
h (13) = h (18) -0.1187 0.1074 0.1074
-20 h (14) =h (17) 0.0980 0.1995 0.1995
Magnitude (dB)

-30 h (15) =h (16) 0.4922 0.2579 0.2579

-40

As for the structure shown in Figure 5(a), SRC

-50
has the general case of a direct implementation.
-60 Furthermore, SRC by a factor (I/M) may also be
-70
achieved using a linear time-variant filter described
by a response function, as shown in equation
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Normalized Frequency ( rad/sample)

(b) Interpolator 𝑔 [𝑛, 𝑚] = ℎ [𝑛𝐼 − (𝑚 𝑀) 𝐼] (1)

Fig. 2. Magnitude Response of the filter Where h[n] stands for an impulse response of
FIR LPF for simplicity. Thus, the coefficients set
Figure 3 shows the realization of the proposed {g[n, m]} for each m = 0, 1, 2, I-1. As previously
filter using a decimator with different structures. For pointed out, g[n, m] is periodic with a period of (I);
direct realization, there are two structures. The first therefore, y(m) can be expressed as shown in Eq. (2):
is found by passing the input sequence x[n] through 𝑚 𝑚𝑀
an FIR filter and then downsampling it by a factor 𝑦[𝑚] = ∑𝐾−1 𝑛=0 𝑔 (𝑛, 𝑚 − ⌊ 𝐼 ⌋ 𝐼) ∗ 𝑥((⌊ 𝐼 ⌋ − 𝑛) (2)
M=2, as shown in Figure 3(a). The second structure If the rational rate conversion is possible by the
is derived from the first structure, which is calculated factor (I/M), then there are (I) polyphase filters, as
by passing all input sequences through down represented in Figure 5(c). Polyphase configurations
sampling, as illustrated in Figure 3(b). The efficient enable arithmetic operations to be performed at the
implementation of a linear-phase decimator is lowest possible sampling frequency [4, 18, 19].
obtained from the use of filter coefficient symmetry,
as shown in Figure 3(c). With more than two stages, 4. RESULTS AND DISCUSSION
the FIR filter may be implemented in the parallel
structure. In Figure 3(d), the polyphase The arithmetic choice in DSP implementation on
decomposition of the filter’s transfer function is used processor platforms, in most cases, is determined by
to express the parallel structure of the filter. the platform. Yet, in FPGA implementations, the
For the Interpolator, the direct implementation arithmetic choice is critical not only for determining
has (I – 1) zeros placed at the time base of x[n], as the algorithm’s capacity but also for defining
shown in Figure 4(a), which represents the significant system characteristics such as area,
conventional system. Multiplication operations are power consumption, and speed. Where the multirate
done with the sampling rate of the input signal, and realization is attained using several approaches
then the result sequence is up-sampled by L for each which include direct, efficient, and polyphase. The
branch, as represented in Figure 4(b). An effective output is expressed in terms of input and filter
structure for designing a linear-phase FIR filter for coefficients. This section provides the design of the
the Interpolator using interpolated coefficients is proposed filter in MATLAB’s Simulink toolbox,
shown in Figure 4(c). which consists of the Interpolator, decimator, and
It is quite the same as in decimators, and due to SRC. Then, the VHDL file for the filter’s Simulink
the inherent symmetry of the coefficients, the implementation is developed by using the MATLAB
number of multiplications may be halved. Figure 4 HDL Coder library. The synthesized bitstream file is
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Gadawe NT, Hamad RW, Qaddoori SL.: Efficient Implementation of Fractional Sampling Rate Conversion …

uploaded at speed grade -1 onto FPGA (XC7A- of the use of symmetry of filter coefficients. Figure
1CSG324). Figure (6) shows the hardware 7 (a-e) shows the device utilization summary. It can
implementation of the decimator with different be noted that the number of register/flip-flop,
structures. multiplexer, and adder/subtractor is approximately
The hardware consumption and device equal in direct realization for all structures, while
utilization summary are illustrated in Table (2). efficient realization of SRC is the best in
From this Table, it can be noted that the second direct consumption of register/flip-flop, and then
structure consumes more slices compared with other polyphase realization of Interpolator and decimator,
structures for decimator and interpolator design. In on the other word, the polyphase realization of
contrast, the polyphase structure represents good decimator consumed less multiplexer,
design in resource utilization (registers, LUTs, flip- adder/subtractor and memory usage compared with
flops) by saving 50% in the decimator and 42.9% in Interpolator and SRC. The comparison of diverse
the Interpolator as in memory usage and multiplexer. SRC employments on FPGA with related works is
Still, the first direct realization is best in the number shown in Table 3. In the related works, many SRC
of unique control sets utilized. The efficient filters are designed and implemented with different
realization is the best in the analysis of real-time and structures and various devices, so comparison with
CPU time to XST by saving 37% in decimator and our work is somewhat difficult.
52% for each Interpolator and SRC, this is because

b) Direct 2
a) Direct 1

c) Efficient d) polyphase

Fig. 3. Realization of Decimator with Different Structures

a) b) Direct 2
Direct1

c) Efficient d) Polyphase
Fig. 4. Realization of Interpolator with Different Structures
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Gadawe NT, Hamad RW, Qaddoori SL.: Efficient Implementation of Fractional Sampling Rate Conversion …

a) Direct b) Efficient

c) polyphase

Fig. 5. Realization of SRC with Different Structures

Table 2. FPGA Implementation of SRC Structures

Decimator Interpolator SRC
Device Utilization D1 D2 ED PD E. P.SR
In1 In. 2 E. I P. I SRC
Summary SRC C
Number of slices
973 1930 1435 974 912 941 862 404 988 358 563
register
Number of slices
1143 2071 1036 620 1147 2075 1040 1371 1180 1500 1505
LUTs
Number of LUTs flip-
2034 3832 1945 1484 1948 2566 1612 1571 2064 1618 1776
flop pairs used
Number of unique
3 32 17 5 3 3 3 4 4 9 10
control sets
Total real-time to XST
18 27 10 19 21 21 11 14 11 11 21
completion(s)
Total CPU time to
17.6 26.76 10.59 18.44 21.37 21.20 11.31 14.09 11.77 10.96 20.21
XST completion(s)

Table 3. The comparison of diverse SRC employments on FPGA with related works
Ref. No. Structures Algorithm Application Device
Multi-rate signal
10 SRC (low pass FIR filter) N/A Virtex 6
processing, SDR
SRC (L=2, M=2) & (L=3, M=2) Altera cyclone
12 N/A EEG
Decimator Filter DE II
Multirate Signal
13 Multi-rate filter (half-band FIR & CIC) Hamming Window Altera develop
Processing System
V-FDF
Multi-standard digital ASIC, FPGA
14 ASRC Newton & farrow structures N estimated
front end (Virtex 6)
(Belanger
SRC using Cascaded multi-rate linear Audio &
15 phase FIR(polyphase, folded, systolic) Iterative procedure Communication Altera Quartus II
structures System
16 ASRC Polyphase FIR filter N/A Digital Audio System N/A
17 SRC with multiple parallel output phases N/A N/A Virtex 7
SRC with Direct, efficient, and
Proposed Remez N/A Artix 7
polyphase structures
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a) b)
direct1 direct
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Gadawe NT, Hamad RW, Qaddoori SL.: Efficient Implementation of Fractional Sampling Rate Conversion …

c) efficient

d) polyphase
Fig. 6. Hardware Implementation of the Decimator
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Gadawe NT, Hamad RW, Qaddoori SL.: Efficient Implementation of Fractional Sampling Rate Conversion …

5. CONCLUSIONS
Number of Multiplexers
100 This paper focuses on digital filter design for
multi-rate signal processing using different
50 structures and its performance by synthesizing to
Artix 7(XC7A100T-1CSG3324) FPGA. The
polyphase method of designing the decimator and
0 Interpolator was found to be more advantageous by
D1 D2 Eff. Poly.
providing an enhanced 67% ratio for operational
Decimator Interpolator SRC speed and 46% ratio for hardware utilization
compared to direct and linear phase structures for
a) Number of Multiplexers enhancing signal processing. As for the SRC, an
Total Memory Usage (Mbyte) efficient linear phase design is preferable, as it uses
4,71 fewer resources and is easier to implement.

4,705 Source of funding: This research received no external

funding.
4,7
Author contributions: research concept and design,
N.T.; Collection and/or assembly of data, R.W.; Data
4,695 analysis and interpretation, R.W.; Writing the article,
D1 D2 Eff. Poly. N.T.; Critical revision of the article, S.L.; Final
Decimator Interpolator SRC approval of the article, S.L.

b) Total Memory Usage Declaration of competing interest: The authors declare

that they have no known competing financial interests
Number of Registers/Flip_flops
or personal relationships that could have appeared to
3000 influence the work reported in this paper.

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