MINI-PROJECT

📑 Project Report

Title: VERILOG HDL IMPLEMENTATION OF EXTERNAL RAM CONTROLLER

OBJECTIVE
In practical FPGA systems, memory is often external to the chip, such as
SRAM or SDRAM. To understand how FPGA controls external RAM, we
designed Single-Port and Dual-Port RAM modules in Verilog. These modules
simulate the operation of external RAM, where read/write operations are
performed under control of FPGA signals (Address, Data, WE, and CLK).
Thus, this project demonstrates the principle of external RAM control using
Verilog and Vivado.”

1. Introduction
In modern digital systems, memory plays a vital role in temporarily storing and
retrieving information during computations. Random Access Memory (RAM) is one of
the most commonly used forms of memory because of its speed and ability to perform
both read and write operations efficiently.

Depending on the requirements of a system, RAM can be designed as Single-Port or

Dual-Port.

 A Single-Port RAM has only one port, which is used for both read and write
operations. At any given clock cycle, either data can be written or read, but not
both. It is simple in design and requires fewer resources.

 A Dual-Port RAM, on the other hand, has two independent ports. This allows
two operations (either read or write) to take place simultaneously, which makes
it useful in high-performance systems like digital signal processing, networking
devices, and multiprocessor communication.

The main objective of this project is to design, simulate, and verify both Single-Port
RAM and Dual-Port RAM using Verilog HDL on Xilinx Vivado 2023.1. This project
provides a deeper understanding of memory design concepts, Verilog coding,
simulation, and the difference between single-port and dual-port architectures.
BLOCK-DIAGRAMS:
SINGLE-PORT RAM

2.Dual-Port RAM is a type of Random Access Memory that provides two

independent access ports. Each port has its own:

 Address bus

 Data input bus

 Data output bus

 Control signals (Write Enable, Read Enable, etc.)

Both ports can operate simultaneously and independently. This means one
port can perform a read operation while the other performs a write
operation at the same time, or both can read/write at different addresses
concurrently.
2. Software Tools
The project was implemented using the following tool:

 Xilinx Vivado Design Suite 2023.1

Vivado, developed by Xilinx (now AMD), is an advanced design environment for

FPGA and SoC development. It provides features such as:

 Verilog/VHDL code editing.

 Simulation and waveform analysis.

 Synthesis and implementation.

 Bitstream generation for FPGA programming.

For this project, Vivado was used for writing Verilog code, running simulations,
and verifying functional correctness. Since this is a simulation-based project, no
hardware was required.

IMPLEMENTATION
Design Methodology

The methodology followed for both Single-Port and Dual-Port RAM designs:

1. Problem Specification

o Decide memory size. For this project:

 32 × 8 (32 memory locations, each 8 bits).

 2. Coding in Verilog

o Write Verilog code for Single-Port RAM.

o Write Verilog code for Dual-Port RAM.

o Develop separate testbenches for both modules.

3. Simulation

o Verify functionality through testbenches.

o Check waveforms for read and write operations.

4. Synthesis

o Ensure design is synthesizable and suitable for FPGA implementation.

4. Verilog Codes

4.1 Single-Port RAM

module single_port_ram (
input [7:0] data, // Input data
input [4:0] adr, // Address (32 locations)
input we, // Write enable
input clk, // Clock
output reg [7:0] q // Output data
);

reg [7:0] ram [31:0]; // 32x8 RAM

always @(posedge clk) begin

if (we)
ram[adr] <= data; // Write operation
 else
q <= ram[adr]; // Read operation
end
endmodule

Testbench (Single-Port RAM)

module single_port_ram_tb;

reg [7:0] data;

reg [4:0] adr;

reg we;

reg clk;

wire [7:0] q;

single_port_ram spr1(.data(data), .adr(adr), .we(we), .clk(clk), .q(q));

initial begin

$dumpfile("single_port.vcd");

$dumpvars(1);

clk = 1'b1;

forever #5 clk = ~clk; // Clock generation

end

initial begin

// Write operations

data = 8'h11; adr = 5'd0; we = 1'b1; #10;

data = 8'h22; adr = 5'd1; #10;

data = 8'h33; adr = 5'd2; #10;

// Read operations

we = 1'b0; adr = 5'd0; #10;

 adr = 5'd1; #10;

adr = 5'd2; #10;

$finish;

end

endmodule

4.2 Dual-Port RAM

module dual_port_ram (

input [7:0] data_a, data_b, // Input data for ports A and B

input [4:0] addr_a, addr_b, // Addresses for ports A and B

input we_a, we_b, // Write enable signals

input clk, // Clock

output reg [7:0] q_a, q_b // Outputs for ports A and B

);

reg [7:0] ram [31:0]; // 32x8 RAM

always @(posedge clk) begin

// Port A operations

if (we_a)

ram[addr_a] <= data_a;

else

q_a <= ram[addr_a];

// Port B operations

if (we_b)

ram[addr_b] <= data_b;

else

q_b <= ram[addr_b];

end
endmodule

Testbench (Dual-Port RAM)

module dual_port_ram_tb;

reg [7:0] data_a, data_b;

reg [4:0] addr_a, addr_b;

reg we_a, we_b;

reg clk;

wire [7:0] q_a, q_b;

dual_port_ram dpr1(.data_a(data_a), .addr_a(addr_a), .we_a(we_a), .q_a(q_a),

.data_b(data_b), .addr_b(addr_b), .we_b(we_b), .q_b(q_b),

.clk(clk));

initial begin

$dumpfile("dual_port.vcd");

$dumpvars(1);

clk = 1'b1;

forever #5 clk = ~clk; // Clock generation

end

initial begin

// Write using Port A

data_a = 8'h55; addr_a = 5'd5; we_a = 1'b1; we_b = 1'b0; #10;

data_a = 8'hAA; addr_a = 5'd10; #10;

// Write using Port B

data_b = 8'h77; addr_b = 5'd15; we_b = 1'b1; we_a = 1'b0; #10;

// Simultaneous read from both ports

we_a = 1'b0; we_b = 1'b0;

 addr_a = 5'd5; addr_b = 5'd10; #10;

addr_a = 5'd15; #10;

$finish;

end

endmodule

5. Simulation Results
Single-Port RAM

 Data was successfully written to memory when we=1.

 During we=0, stored data was correctly read from addresses.

 Simulation waveforms confirmed the expected results.

These are the results observed from single port RAM

Dual-Port RAM

 Port A and Port B could independently perform read or write operations.

 Verified simultaneous read from different addresses.

 When one port was writing and another was reading, results were consistent.

6. Comparison

Feature Single-Port RAM Dual-Port RAM

Ports One Two

Read/Write simultaneously
Operations Either Read or Write
possible

Complexit
Simple Higher complexity
y
Feature Single-Port RAM Dual-Port RAM

Application Small memory, DSP, multiprocessors,

s controllers networking

7. Conclusion
In this project, both Single-Port RAM and Dual-Port RAM were designed and
simulated using Verilog HDL in Xilinx Vivado 2023.1. The simulation results
verified the correctness of read and write operations in both cases.

 Single-Port RAM: simple and resource-efficient, but allows only one operation
at a time.

 Dual-Port RAM: allows simultaneous access, making it more suitable for

complex and high-performance applications.

This project enhanced understanding of memory architectures and provided hands-on

experience in using Verilog HDL and the Vivado toolchain.