TS80C54X2/C58X2

TS87C54X2/C58X2
8-bit CMOS Microcontroller 16/32 Kbytes ROM/OTP

1. Description
TS80C54/58X2 is high performance CMOS ROM, OTP The fully static design of the TS80C54/58X2 allows to
and EPROM versions of the 80C51 CMOS single chip reduce system power consumption by bringing the clock
8-bit microcontroller. frequency down to any value, even DC, without loss of
data.
The TS80C54/58X2 retains all features of the Atmel
Wireless & Microcontrollers 80C51 with extended The TS80C54/58X2 has 2 software-selectable modes of
reduced activity for further reduction in power
ROM/EPROM capacity (16/32 Kbytes), 256 bytes of
consumption. In the idle mode the CPU is frozen while
internal RAM, a 6-source , 4-level interrupt system, an the timers, the serial port and the interrupt system are still
on-chip oscilator and three timer/counters. operating. In the power-down mode the RAM is saved
In addition, the TS80C54/58X2 has a Hardware and all other functions are inoperative.
Watchdog Timer, a more versatile serial channel that
facilitates multiprocessor communication (EUART) and
a X2 speed improvement mechanism.

2. Features
● 80C52 Compatible ● Interrupt Structure with
• 8051 pin and instruction compatible • 6 Interrupt sources
• Four 8-bit I/O ports • 4 level priority interrupt system
• Three 16-bit timer/counters ● Full duplex Enhanced UART
• 256 bytes scratchpad RAM • Framing error detection
● High-Speed Architecture • Automatic address recognition
• 40 MHz @ 5V, 30MHz @ 3V ● Low EMI (inhibit ALE)
• X2 Speed Improvement capability (6 clocks/ ● Power Control modes
machine cycle) • Idle mode
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to • Power-down mode
60 MHz @ 5V, 40 MHz @ 3V)
• Power-off Flag
● Dual Data Pointer
● Once mode (On-chip Emulation)
● On-chip ROM/EPROM (16K-bytes, 32K-bytes)
● Power supply: 4.5-5.5V, 2.7-5.5V
● Programmable Clock Out and Up/Down Timer/
Counter 2 ● Temperature ranges: Commercial (0 to 70oC) and
Industrial (-40 to 85oC)
● Hardware Watchdog Timer (One-time enabled with
Reset-Out) ● Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP44
F1, CQPJ44 (window), CDIL40 (window)
● Asynchronous port reset

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Table 1. Memory size

PDIL40
PLCC44
ROM (bytes) EPROM (bytes)
PQFP44 F1
VQFP44 1.4
TS80C54X2 16k 0
TS80C58X2 32k 0
TS87C54X2 0 16k
TS87C58X2 0 32k

3. Block Diagram

T2EX
RxD
TxD

Vcc
Vss

T2
(2) (2) (1) (1)

XTAL1
RAM ROM
XTAL2 EUART /EPROM Timer2
256x8 16/32Kx8

ALE/ PROG C51

CORE IB-bus
PSEN
CPU

EA/VPP

(2) Timer 0 INT Parallel I/O Ports Watch

RD
Timer 1 Ctrl Dog
WR (2) Port 0 Port 1 Port 2 Port 3

(2) (2) (2) (2)

P1

P2

P3
RESET

T0
T1

INT0
INT1

P0

(1): Alternate function of Port 1

(2): Alternate function of Port 3

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4. SFR Mapping
The Special Function Registers (SFRs) of the TS80C54/58X2 fall into the following categories:
• C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
• I/O port registers: P0, P1, P2, P3
• Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H
• Serial I/O port registers: SADDR, SADEN, SBUF, SCON
• Power and clock control registers: PCON
• HDW Watchdog Timer Reset: WDTRST, WDTPRG
• Interrupt system registers: IE, IP, IPH
• Others: AUXR, CKCON
Table 2. All SFRs with their address and their reset value
Bit Non Bit addressable
address-
able

0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F

F8h FFh
B
F0h F7h
0000 0000

E8h EFh
ACC
E0h E7h
0000 0000

D8h DFh
PSW
D0h D7h
0000 0000
T2CON T2MOD RCAP2L RCAP2H TL2 TH2
C8h CFh
0000 0000 XXXX XX00 0000 0000 0000 0000 0000 0000 0000 0000

C0h C7h
IP SADEN
B8h BFh
XX00 0000 0000 0000
P3 IPH
B0h B7h
1111 1111 XX00 0000
IE SADDR
A8h AFh
0X00 0000 0000 0000
P2 AUXR1 WDTRST WDTPRG
A0h A7h
1111 1111 XXXX 0XX0 XXXX XXXX XXXX X000
SCON SBUF
98h 9Fh
0000 0000 XXXX XXXX
P1
90h 97h
1111 1111
TCON TMOD TL0 TL1 TH0 TH1 AUXR CKCON
88h 8Fh
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 XXXX XX00 XXXX XXX0
P0 SP DPL DPH PCON
80h 87h
1111 1111 0000 0111 0000 0000 0000 0000 00X1 0000

0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F

reserved

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5. Pin Configuration

P1.0 / T2 1 40 VCC
P1.1 / T2EX 2 39 P0.0 / A0
P1.2 3 38 P0.1 / A1

VSS1/NIC*
P1.1/T2EX

P0.3/AD3
P0.0/AD0
P0.1/AD1
P0.2/AD2
P1.3 4 37 P0.2 / A2

P1.0/T2
P1.4 P0.3 / A3

VCC
5 36

P1.4
P1.3
P1.2
P1.5 6 35 P0.4 / A4
P1.6 7 34 P0.5 / A5
6 5 4 3 2 1 44 43 42 41 40
P1.7 8 33 P0.6 / A6 P1.5 7 39 P0.4/AD4
RST 9 32 P0.7 / A7 P1.6 38
8 P0.5/AD5
P3.0/RxD 10 31 EA/VPP P1.7 9 37
PDIL/ P0.6/AD6
P3.1/TxD 11 30 ALE/PROG RST 10 36 P0.7/AD7
P3.2/INT0 12 CDIL40 29 PSEN P3.0/RxD 11 35 EA/VPP
P3.3/INT1 13 28 P2.7 / A15 NIC*
P2.6 / A14
12 PLCC/CQPJ 44 34 NIC*
P3.4/T0 14 27 P3.1/TxD 13 33
P2.5 / A13 ALE/PROG
P3.5/T1 15 26 P3.2/INT0 14 32 PSEN
P3.6/WR 16 25 P2.4 / A12
P3.3/INT1 15 31 P2.7/A15
P2.3 / A11
P3.7/RD 17 24 P3.4/T0 16 30 P2.6/A14
XTAL2 18 23 P2.2 / A10 P3.5/T1 17 29 P2.5/A13
XTAL1 19 22 P2.1 / A9
18 19 20 21 22 23 24 25 26 27 28
VSS 20 21 P2.0 / A8

NIC*
XTAL2
XTAL1
P3.6/WR

P2.2/A10
P2.3/A11
P2.4/A12
P2.0/A8
P2.1/A9
P3.7/RD

VSS
VSS1/NIC*
P1.1/T2EX

P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P1.0/T2

VCC
P1.4
P1.3
P1.2

44 43 42 41 40 39 38 37 36 35 34
P1.5 1 33 P0.4/AD4
P1.6 2 32 P0.5/AD5
P1.7 3 31 P0.6/AD6
RST 4 30 P0.7/AD7
P3.0/RxD 5 29 EA/VPP
NIC* 6 28 NIC*
P3.1/TxD 7 PQFP44 F1 27 ALE/PROG
P3.2/INT0 8 VQFP44 1.4 26 PSEN
P3.3/INT1 9 25 P2.7/A15
P3.4/T0 10 24 P2.6/A14
P3.5/T1 11 23 P2.5/A13
12 13 14 15 16 17 18 19 20 21 22
XTAL1

NIC*
XTAL2

P2.3/A11
P2.0/A8
P2.1/A9
VSS

P2.2/A10

P2.4/A12
P3.7/RD
P3.6/WR

*NIC: No Internal Connection

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Table 3. Pin Description for 40/44 pin packages
PIN NUMBER
MNEMONIC TYPE NAME AND FUNCTION
DIL LCC VQFP 1.4
VSS 20 22 16 I Ground: 0V reference
Vss1 1 39 I Optional Ground: Contact the Sales Office for ground connection.
Power Supply: This is the power supply voltage for normal, idle and power-
VCC 40 44 38 I
down operation
P0.0-P0.7 39-32 43-36 37-30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high impedance inputs. Port 0 pins must
be polarized to Vcc or Vss in order to prevent any parasitic current consumption.
Port 0 is also the multiplexed low-order address and data bus during access to
external program and data memory. In this application, it uses strong internal
pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM
programming. External pull-ups are required during program verification during
which P0 outputs the code bytes.
P1.0-P1.7 1-8 2-9 40-44 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1
1-3 pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 1 pins that are externally pulled low will
source current because of the internal pull-ups. Port 1 also receives the low-order
address byte during memory programming and verification.
Alternate functions for Port 1 include:
1 2 40 I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout
2 3 41 I T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control
P2.0-P2.7 21-28 24-31 18-25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 2 pins that are externally pulled low will
source current because of the internal pull-ups. Port 2 emits the high-order address
byte during fetches from external program memory and during accesses to external
data memory that use 16-bit addresses (MOVX @DPTR).In this application, it
uses strong internal pull-ups emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
Some Port 2 pins receive the high order address bits during EPROM programming
and verification:
P2.0 to P2.5 for A8 to A13
P3.0-P3.7 10-17 11, 5, I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
13-19 7-13 pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 3 pins that are externally pulled low will
source current because of the internal pull-ups. Some Port 3 pin P3.4 receive
the high order address bits during EPROM programming and verification for
TS8xC58X2 devices.
Port 3 also serves the special features of the 80C51 family, as listed below.
10 11 5 I RXD (P3.0): Serial input port
11 13 7 O TXD (P3.1): Serial output port
12 14 8 I INT0 (P3.2): External interrupt 0
13 15 9 I INT1 (P3.3): External interrupt 1
14 16 10 I T0 (P3.4): Timer 0 external input
15 17 11 I T1 (P3.5): Timer 1 external input
16 18 12 O WR (P3.6): External data memory write strobe
17 19 13 O RD (P3.7): External data memory read strobe
P3.4 also receives A14 during TS87C58X2 EPROM Programming.
Reset 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal diffused resistor to VSS permits a power-on reset
using only an external capacitor to VCC.

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Table 3. Pin Description for 40/44 pin packages
MNEMONIC PIN NUMBER TYPE NAME AND FUNCTION
ALE/PROG 30 33 27 O (I) Address Latch Enable/Program Pulse: Output pulse for latching the low byte
of the address during an access to external memory. In normal operation, ALE
is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency,
and can be used for external timing or clocking. Note that one ALE pulse is
skipped during each access to external data memory. This pin is also the program
pulse input (PROG) during EPROM programming. ALE can be disabled by
setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal
fetches.
PSEN 29 32 26 O Program Store ENable: The read strobe to external program memory. When
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access
to external data memory. PSEN is not activated during fetches from internal
program memory.
EA/VPP 31 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally
held low to enable the device to fetch code from external program memory
locations 0000H and 3FFFH (54X2) or 7FFFH (58X2). If EA is held high, the
device executes from internal program memory unless the program counter
contains an address greater than 3FFFH (54X2) or 7FFFH (58X2). This pin also
receives the 12.75V programming supply voltage (VPP) during EPROM
programming. If security level 1 is programmed, EA will be internally latched
on Reset.
XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal
clock generator circuits.
XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier

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6. TS80C54/58X2 Enhanced Features
In comparison to the original 80C52, the TS80C54/58X2 implements some new features, which are:
• The X2 option.
• The Dual Data Pointer.
• The Watchdog.
• The 4 level interrupt priority system.
• The power-off flag.
• The ONCE mode.
• The ALE disabling.
• Some enhanced features are also located in the UART and the timer 2.

6.1 X2 Feature
The TS80C54/58X2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the
following advantages:
● Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
● Save power consumption while keeping same CPU power (oscillator power saving).
● Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes.
● Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main
clock input of the core (phase generator). This divider may be disabled by software.

6.1.1 Description
The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and
peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed,
the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 1. shows the clock generation block
diagram. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode.
Figure 2. shows the mode switching waveforms.

XTAL1:2
XTAL1 2 0 state machine: 6 clock cycles.
FXTAL CPU control
1
FOSC

X2

CKCON reg

Figure 1. Clock Generation Diagram

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TS87C54X2/C58X2

XTAL1

XTAL1:2

X2 bit

CPU clock

STD Mode X2 Mode STD Mode

Figure 2. Mode Switching Waveforms

The X2 bit in the CKCON register (See Table 4.) allows to switch from 12 clock cycles per instruction to 6 clock
cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature
(X2 mode).
CAUTION
In order to prevent any incorrect operation while operating in X2 mode, user must be aware that all peripherals
using clock frequency as time reference (UART, timers) will have their time reference divided by two. For example
a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. UART with
4800 baud rate will have 9600 baud rate.

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TS87C54X2/C58X2
Table 4. CKCON Register
CKCON - Clock Control Register (8Fh)
7 6 5 4 3 2 1 0
- - - - - - - X2

Bit Bit
Description
Number Mnemonic
Reserved
7 -
The value read from this bit is indeterminate. Do not set this bit.

Reserved
6 -
The value read from this bit is indeterminate. Do not set this bit.

Reserved
5 -
The value read from this bit is indeterminate. Do not set this bit.

Reserved
4 -
The value read from this bit is indeterminate. Do not set this bit.

Reserved
3 -
The value read from this bit is indeterminate. Do not set this bit.

Reserved
2 -
The value read from this bit is indeterminate. Do not set this bit.

Reserved
1 -
The value read from this bit is indeterminate. Do not set this bit.

CPU and peripheral clock bit

0 X2 Clear to select 12 clock periods per machine cycle (STD mode, FOSC=FXTAL/2).
Set to select 6 clock periods per machine cycle (X2 mode, FOSC=FXTAL).

Reset Value = XXXX XXX0b

Not bit addressable

For further details on the X2 feature, please refer to ANM072 available on the web (http://www.atmel -wm.com)

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TS80C54X2/C58X2
TS87C54X2/C58X2
6.2 Dual Data Pointer Register Ddptr
The additional data pointer can be used to speed up code execution and reduce code size in a number of
ways.
The dual DPTR structure is a way by which the chip will specify the address of an external data memory
location. There are two 16-bit DPTR registers that address the external memory, and a single bit called
DPS = AUXR1/bit0 (See Table 5.) that allows the program code to switch between them (Refer to Figure 3).
External Data Memory

7 0

DPS
DPTR1
DPTR0
AUXR1(A2H)
DPH(83H) DPL(82H)

Figure 3. Use of Dual Pointer

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Table 5. AUXR1: Auxiliary Register 1

7 6 5 4 3 2 1 0
- - - - GF3 0 - DPS

Bit Bit
Description
Number Mnemonic
Reserved
7 -
The value read from this bit is indeterminate. Do not set this bit.

Reserved
6 -
The value read from this bit is indeterminate. Do not set this bit.

Reserved
5 -
The value read from this bit is indeterminate. Do not set this bit.

Reserved
4 -
The value read from this bit is indeterminate. Do not set this bit.

3 GF3 This bit is a general purpose user flag

Reserved
2 0
Always stuck at 0.

Reserved
1 -
The value read from this bit is indeterminate. Do not set this bit.

Data Pointer Selection

0 DPS Clear to select DPTR0.
Set to select DPTR1.

Reset Value = XXXX 00X0

Not bit addressable
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new feature. In that case, the reset
value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

Application
Software can take advantage of the additional data pointers to both increase speed and reduce code size, for
example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’
pointer and the other one as a "destination" pointer.

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ASSEMBLY LANGUAGE

; Block move using dual data pointers

; Destroys DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6 JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS

INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However,
note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it.
In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence
matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1'
on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the
opposite state.

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TS87C54X2/C58X2
6.3 Timer 2
The timer 2 in the TS80C54/58X2 is compatible with the timer 2 in the 80C52.
It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in
cascade. It is controlled by T2CON register (See Table 6) and T2MOD register (See Table 7). Timer 2 operation
is similar to Timer 0 and Timer 1. C/T2 selects FOSC/12 (timer operation) or external pin T2 (counter operation)
as the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input.
Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes are selected by the
combination of RCLK, TCLK and CP/RL2 (T2CON), as described in the Atmel Wireless & Microcontrollers 8-
bit Microcontroller Hardware description.
Refer to the Atmel Wireless & Microcontrollers 8-bit Microcontroller Hardware description for the description of
Capture and Baud Rate Generator Modes.
In TS80C54/58X2 Timer 2 includes the following enhancements:
● Auto-reload mode with up or down counter
● Programmable clock-output

6.3.1 Auto-Reload Mode

The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit
in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the Atmel Wireless & Microcontrollers 8-bit
Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an Up/down timer/counter as shown in
Figure 4. In this mode the T2EX pin controls the direction of count.
When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates
an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded
into the timer registers TH2 and TL2.
When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and
TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh
into the timer registers.
The EXF2 bit toggles when timer 2 overflows or underflows according to the the direction of the count. EXF2
does not generate any interrupt. This bit can be used to provide 17-bit resolution.

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TS87C54X2/C58X2

(:6 in X2 mode)
XTAL1 :12 0
FXTAL FOSC 1

T2
C/T2 TR2
T2CONreg T2CONreg

(DOWN COUNTING RELOAD VALUE) T2EX:

FFh FFh if DCEN=1, 1=UP
(8-bit) (8-bit) if DCEN=1, 0=DOWN
if DCEN = 0, up counting

TOGGLE T2CONreg
EXF2

TL2 TH2 TIMER 2

TF2
(8-bit) (8-bit) INTERRUPT
T2CONreg

RCAP2L RCAP2H
(8-bit) (8-bit)
(UP COUNTING RELOAD VALUE)

Figure 4. Auto-Reload Mode Up/Down Counter (DCEN = 1)

6.3.2 Programmable Clock-Output

In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 5) . The
input clock increments TL2 at frequency FOSC/2. The timer repeatedly counts to overflow from a loaded value.
At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer
2 overflows do not generate interrupts. The formula gives the clock-out frequency as a function of the system
oscillator frequency and the value in the RCAP2H and RCAP2L registers :

F
osc
Clock – OutFrequency = --------------------------------------------------------------------------------------
4 × ( 65536 – RCAP2H ⁄ RCAP2L )

For a 16 MHz system clock, timer 2 has a programmable frequency range of 61 Hz

(FOSC/216) to 4 MHz (FOSC/4). The generated clock signal is brought out to T2 pin (P1.0).
Timer 2 is programmed for the clock-out mode as follows:
● Set T2OE bit in T2MOD register.
● Clear C/T2 bit in T2CON register.
● Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers.
● Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or a different
one depending on the application.
● To start the timer, set TR2 run control bit in T2CON register.

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TS87C54X2/C58X2
It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration,
the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and
RCAP2L registers.

XTAL1 :2
(:1 in X2 mode)

TR2
T2CON reg TL2 TH2
(8-bit) (8-bit)
OVERFLOW

RCAP2L RCAP2H
(8-bit) (8-bit)
Toggle
T2

Q D
T2OE
T2MOD reg
TIMER 2
T2EX EXF2 INTERRUPT
T2CON reg
EXEN2
T2CON reg

Figure 5. Clock-Out Mode C/T2 = 0

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TS80C54X2/C58X2
TS87C54X2/C58X2
Table 6. T2CON Register
T2CON - Timer 2 Control Register (C8h)
7 6 5 4 3 2 1 0
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#

Bit Bit
Description
Number Mnemonic
Timer 2 overflow Flag
7 TF2 Must be cleared by software.
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.

Timer 2 External Flag

Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.
6 EXF2
When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1)

Receive Clock bit

5 RCLK Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.

Transmit Clock bit

4 TCLK Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.

Timer 2 External Enable bit

Clear to ignore events on T2EX pin for timer 2 operation.
3 EXEN2
Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to
clock the serial port.

Timer 2 Run control bit

2 TR2 Clear to turn off timer 2.
Set to turn on timer 2.

Timer/Counter 2 select bit

1 C/T2# Clear for timer operation (input from internal clock system: FOSC).
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode.

Timer 2 Capture/Reload bit

If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow.
0 CP/RL2#
Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.

Reset Value = 0000 0000b

Bit addressable

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 TS80C54X2/C58X2
TS87C54X2/C58X2
Table 7. T2MOD Register
T2MOD - Timer 2 Mode Control Register (C9h)
7 6 5 4 3 2 1 0
- - - - - - T2OE DCEN

Bit Bit
Description
Number Mnemonic
Reserved
7 -
The value read from this bit is indeterminate. Do not set this bit.

Reserved
6 -
The value read from this bit is indeterminate. Do not set this bit.

Reserved
5 -
The value read from this bit is indeterminate. Do not set this bit.

Reserved
4 -
The value read from this bit is indeterminate. Do not set this bit.

Reserved
3 -
The value read from this bit is indeterminate. Do not set this bit.

Reserved
2 -
The value read from this bit is indeterminate. Do not set this bit.

Timer 2 Output Enable bit

1 T2OE Clear to program P1.0/T2 as clock input or I/O port.
Set to program P1.0/T2 as clock output.

Down Counter Enable bit

0 DCEN Clear to disable timer 2 as up/down counter.
Set to enable timer 2 as up/down counter.

Reset Value = XXXX XX00b

Not bit addressable

Rev. C - 15 January, 2001 17

TS80C54X2/C58X2
TS87C54X2/C58X2
6.4 TS80C54/58X2 Serial I/O Port
The serial I/O port in the TS80C54/58X2 is compatible with the serial I/O port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous
Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and
reception can occur simultaneously and at different baud rates
Serial I/O port includes the following enhancements:
● Framing error detection
● Automatic address recognition

6.4.1 Framing Error Detection

Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing
bit error detection feature, set SMOD0 bit in PCON register (See Figure 6).

SM0/FE SM1 SM2 REN TB8 RB8 TI RI SCON (98h)

Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)

SM0 to UART mode control (SMOD = 0)

SMOD1 SMOD0 - POF GF1 GF0 PD IDL PCON (87h)

To UART framing error control

Figure 6. Framing Error Block Diagram

When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop
bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit
is not found, the Framing Error bit (FE) in SCON register (See Table 8.) bit is set.

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 TS80C54X2/C58X2
TS87C54X2/C58X2
Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can
clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled,
RI rises on stop bit instead of the last data bit (See Figure 7. and Figure 8.).

RXD D0 D1 D2 D3 D4 D5 D6 D7

Start Data byte Stop

bit bit
RI
SMOD0=X

FE
SMOD0=1

Figure 7. UART Timings in Mode 1

RXD D0 D1 D2 D3 D4 D5 D6 D7 D8

Start Data byte Ninth Stop

bit bit bit
RI
SMOD0=0

RI
SMOD0=1

FE
SMOD0=1

Figure 8. UART Timings in Modes 2 and 3

6.4.2 Automatic Address Recognition

The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled
(SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by
allowing the serial port to examine the address of each incoming command frame. Only when the serial port
recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that
the CPU is not interrupted by command frames addressed to other devices.
If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit
takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the
device’s address and is terminated by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and a broadcast address.

NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON
register in mode 0 has no effect).

Rev. C - 15 January, 2001 19

TS80C54X2/C58X2
TS87C54X2/C58X2
6.4.3 Given Address
Each device has an individual address that is specified in SADDR register; the SADEN register is a mask byte
that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the
flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111 1111b.
For example:
SADDR 0101 0110b
SADEN 1111 1100b
Given 0101 01XXb

The following is an example of how to use given addresses to address different slaves:
Slave A: SADDR 1111 0001b
SADEN 1111 1010b
Given 1111 0X0Xb

Slave B: SADDR 1111 0011b

SADEN 1111 1001b
Given 1111 0XX1b

Slave C: SADDR 1111 0010b

SADEN 1111 1101b
Given 1111 00X1b

The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A
only, the master must send an address where bit 0 is clear (e.g. 1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but
not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2
clear (e.g. 1111 0001b).

6.4.4 Broadcast Address

A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as
don’t-care bits, e.g.:
SADDR 0101 0110b
SADEN 1111 1100b
Broadcast =SADDR OR SADEN 1111 111Xb

The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a
broadcast address is FFh. The following is an example of using broadcast addresses:
Slave A: SADDR 1111 0001b
SADEN 1111 1010b
Broadcast 1111 1X11b,

Slave B: SADDR 1111 0011b

SADEN 1111 1001b
Broadcast 1111 1X11B,

Slave C: SADDR= 1111 0010b

SADEN 1111 1101b
Broadcast 1111 1111b

For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the
master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send
and address FBh.

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 TS80C54X2/C58X2
TS87C54X2/C58X2
6.4.5 Reset Addresses
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX
XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards
compatible with the 80C51 microcontrollers that do not support automatic address recognition.
SADEN - Slave Address Mask Register (B9h)
7 6 5 4 3 2 1 0

Reset Value = 0000 0000b

Not bit addressable

SADDR - Slave Address Register (A9h)

7 6 5 4 3 2 1 0

Reset Value = 0000 0000b

Not bit addressable

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TS80C54X2/C58X2
TS87C54X2/C58X2
Table 8. SCON Register
SCON - Serial Control Register (98h)
7 6 5 4 3 2 1 0
FE/SM0 SM1 SM2 REN TB8 RB8 TI RI

Bit Bit
Description
Number Mnemonic
Framing Error bit (SMOD0=1)
Clear to reset the error state, not cleared by a valid stop bit.
7 FE Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit

Serial port Mode bit 0

SM0 Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit

Serial port Mode bit 1

SM0 SM1 Mode Description Baud Rate

6 SM1 0 0 0 Shift Register FXTAL/12 (/6 in X2 mode)

0 1 1 8-bit UART Variable
1 0 2 9-bit UART FXTAL/64 or FXTAL/32 (/32, /16 in X2 mode)
1 1 3 9-bit UART Variable

Serial port Mode 2 bit / Multiprocessor Communication Enable bit

Clear to disable multiprocessor communication feature.
5 SM2
Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should
be cleared in mode 0.

Reception Enable bit

4 REN Clear to disable serial reception.
Set to enable serial reception.

Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3.

3 TB8 Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.

Receiver Bit 8 / Ninth bit received in modes 2 and 3

Cleared by hardware if 9th bit received is a logic 0.
2 RB8 Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.

Transmit Interrupt flag

Clear to acknowledge interrupt.
1 TI
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other
modes.

Receive Interrupt flag

0 RI Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 7. and Figure 8. in the other modes.

Reset Value = 0000 0000b

Bit addressable

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 TS80C54X2/C58X2
TS87C54X2/C58X2
Table 9. PCON Register

PCON - Power Control Register (87h)

7 6 5 4 3 2 1 0
SMOD1 SMOD0 - POF GF1 GF0 PD IDL

Bit Bit
Description
Number Mnemonic
Serial port Mode bit 1
7 SMOD1
Set to select double baud rate in mode 1, 2 or 3.

Serial port Mode bit 0

6 SMOD0 Clear to select SM0 bit in SCON register.
Set to to select FE bit in SCON register.

Reserved
5 -
The value read from this bit is indeterminate. Do not set this bit.

Power-Off Flag
4 POF Clear to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.

General purpose Flag

3 GF1 Cleared by user for general purpose usage.
Set by user for general purpose usage.

General purpose Flag

2 GF0 Cleared by user for general purpose usage.
Set by user for general purpose usage.

Power-Down mode bit

1 PD Cleared by hardware when reset occurs.
Set to enter power-down mode.

Idle mode bit

0 IDL Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.

Reset Value = 00X1 0000b

Not bit addressable
Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit.

Rev. C - 15 January, 2001 23

TS80C54X2/C58X2
TS87C54X2/C58X2
6.5 Interrupt System
The TS80C54/58X2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts
(timers 0, 1 and 2) and the serial port interrupt. These interrupts are shown in Figure 9.

High priority
IPH, IP interrupt
3
INT0 IE0
0

3
TF0
0

3 Interrupt
INT1 IE1 polling
0
sequence, decreasing
3 from high to low priority
TF1
0

RI 3
TI 0

TF2 3
EXF2 0

Individual Enable Global Disable Low priority

interrupt

Figure 9. Interrupt Control System

Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt
Enable register (See Table 11.). This register also contains a global disable bit, which must be cleared to disable
all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing
a bit in the Interrupt Priority register (See Table 12.) and in the Interrupt Priority High register (See Table 13.).
shows the bit values and priority levels associated with each combination.

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 TS80C54X2/C58X2
TS87C54X2/C58X2
Table 10. Priority Level Bit Values

IPH.x IP.x Interrupt Level Priority

0 0 0 (Lowest)
0 1 1
1 0 2
1 1 3 (Highest)

A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt.
A high-priority interrupt can’t be interrupted by any other interrupt source.
If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level
is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence
determines which request is serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
Table 11. IE Register
IE - Interrupt Enable Register (A8h)
7 6 5 4 3 2 1 0
EA - ET2 ES ET1 EX1 ET0 EX0

Bit Bit
Description
Number Mnemonic
Enable All interrupt bit
Clear to disable all interrupts.
7 EA Set to enable all interrupts.
If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its own interrupt
enable bit.

Reserved
6 - Reserved
The value read from this bit is indeterminate. Do not set this bit.

Timer 2 overflow interrupt Enable bit

5 ET2 Clear to disable timer 2 overflow interrupt.
Set to enable timer 2 overflow interrupt.

Serial port Enable bit

4 ES Clear to disable serial port interrupt.
Set to enable serial port interrupt.

Timer 1 overflow interrupt Enable bit

3 ET1 Clear to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.

External interrupt 1 Enable bit

2 EX1 Clear to disable external interrupt 1.
Set to enable external interrupt 1.

Timer 0 overflow interrupt Enable bit

1 ET0 Clear to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.

External interrupt 0 Enable bit

0 EX0 Clear to disable external interrupt 0.
Set to enable external interrupt 0.

Reset Value = 0X00 0000b

Bit addressable

Rev. C - 15 January, 2001 25

TS80C54X2/C58X2
TS87C54X2/C58X2
Table 12. IP Register
IP - Interrupt Priority Register (B8h)
7 6 5 4 3 2 1 0
- - PT2 PS PT1 PX1 PT0 PX0

Bit Bit
Description
Number Mnemonic
Reserved
7 -
The value read from this bit is indeterminate. Do not set this bit.

Reserved
6 -
The value read from this bit is indeterminate. Do not set this bit.

Timer 2 overflow interrupt Priority bit

5 PT2
Refer to PT2H for priority level.

Serial port Priority bit

4 PS
Refer to PSH for priority level.

Timer 1 overflow interrupt Priority bit

3 PT1
Refer to PT1H for priority level.

External interrupt 1 Priority bit

2 PX1
Refer to PX1H for priority level.

Timer 0 overflow interrupt Priority bit

1 PT0
Refer to PT0H for priority level.

External interrupt 0 Priority bit

0 PX0
Refer to PX0H for priority level.

Reset Value = XX00 0000b

Bit addressable

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 TS80C54X2/C58X2
TS87C54X2/C58X2
Table 13. IPH Register
IPH - Interrupt Priority High Register (B7h)
7 6 5 4 3 2 1 0
- - PT2H PSH PT1H PX1H PT0H PX0H

Bit Bit
Description
Number Mnemonic
Reserved
7 -
The value read from this bit is indeterminate. Do not set this bit.

Reserved
6 -
The value read from this bit is indeterminate. Do not set this bit.

Timer 2 overflow interrupt Priority High bit

PT2H PT2 Priority Level
0 0 Lowest
5 PT2H
0 1
1 0
1 1 Highest

Serial port Priority High bit

PSH PS Priority Level
0 0 Lowest
4 PSH
0 1
1 0
1 1 Highest

Timer 1 overflow interrupt Priority High bit

PT1H PT1 Priority Level
0 0 Lowest
3 PT1H
0 1
1 0
1 1 Highest

External interrupt 1 Priority High bit

PX1H PX1 Priority Level
0 0 Lowest
2 PX1H
0 1
1 0
1 1 Highest

Timer 0 overflow interrupt Priority High bit

PT0H PT0 Priority Level
0 0 Lowest
1 PT0H
0 1
1 0
1 1 Highest

External interrupt 0 Priority High bit

PX0H PX0 Priority Level
0 0 Lowest
0 PX0H
0 1
1 0
1 1 Highest

Reset Value = XX00 0000b

Not bit addressable

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TS80C54X2/C58X2
TS87C54X2/C58X2
6.6 Idle mode
An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode.
In the Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port
functions. The CPU status is preserved in its entirely : the Stack Pointer, Program Counter, Program Status Word,
Accumulator and all other registers maintain their data during Idle. The port pins hold the logical states they had
at the time Idle was activated. ALE and PSEN hold at logic high levels.
There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0 to be cleared by
hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to
be executed will be the one following the instruction that put the device into idle.
The flag bits GF0 and GF1 can be used to give an indication if an interrupt occured during normal operation or
during an Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is
terminated by an interrupt, the interrupt service routine can examine the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running,
the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset.

6.7 Power-Down Mode

To save maximum power, a power-down mode can be invoked by software (Refer to Table 9., PCON register).
In power-down mode, the oscillator is stopped and the instruction that invoked power-down mode is the last
instruction executed. The internal RAM and SFRs retain their value until the power-down mode is terminated.
VCC can be lowered to save further power. Either a hardware reset or an external interrupt can cause an exit from
power-down. To properly terminate power-down, the reset or external interrupt should not be executed before VCC
is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize.
Only external interrupts INT0 and INT1 are useful to exit from power-down. For that, interrupt must be enabled
and configured as level or edge sensitive interrupt input.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 10.
When both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power
down exit will be completed when the first input will be released. In this case the higher priority interrupt service
routine is executed.
Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction
that put TS80C54/58X2 into power-down mode.

INT0

INT1

XTAL1

Active phase Power-down phase Oscillator restart phase Active phase

Figure 10. Power-Down Exit Waveform

Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect
the SFRs.
Exit from power-down by either reset or external interrupt does not affect the internal RAM content.
NOTE: If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is unchanged, when execution is vectored to interrupt,
PD and IDL bits are cleared and idle mode is not entered.

28 Rev. C - 15 January, 2001

 TS80C54X2/C58X2
TS87C54X2/C58X2
Table 14. The state of ports during idle and power-down modes

Program
Mode ALE PSEN PORT0 PORT1 PORT2 PORT3
Memory
Idle Internal 1 1 Port Data* Port Data Port Data Port Data
Idle External 1 1 Floating Port Data Address Port Data
Power Down Internal 0 0 Port Data* Port Data Port Data Port Data
Power Down External 0 0 Floating Port Data Port Data Port Data
* Port 0 can force a "zero" level. A "one" Level will leave port floating.

Rev. C - 15 January, 2001 29

TS80C54X2/C58X2
TS87C54X2/C58X2
6.8 Hardware Watchdog Timer
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The
WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default
disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST,
SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator is running
and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will drive an output RESET HIGH pulse at the RST-pin.

6.8.1 Using the WDT

To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When
WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow.
The 14-bit counter overflows when it reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled,
it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at
least every 16383 machine cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST
is a write only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an
output RESET pulse at the RST-pin. The RESET pulse duration is 96 x TOSC , where TOSC = 1/FOSC . To make
the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within
the time required to prevent a WDT reset.
To have a more powerful WDT, a 27 counter has been added to extend the Time-out capability, ranking from
16ms to 2s @ FOSC = 12MHz. To manage this feature, refer to WDTPRG register description, Table 16. (SFR0A7h).

Table 15. WDTRST Register

WDTRST Address (0A6h)

7 6 5 4 3 2 1
Reset value X X X X X X X

Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence.

30 Rev. C - 15 January, 2001

 TS80C54X2/C58X2
TS87C54X2/C58X2
Table 16. WDTPRG Register
WDTPRG Address (0A7h)
7 6 5 4 3 2 1 0
T4 T3 T2 T1 T0 S2 S1 S0

Bit Bit
Description
Number Mnemonic
7 T4

6 T3
Reserved
5 T2
Do not try to set or clear this bit.
4 T1

3 T0

2 S2 WDT Time-out select bit 2

1 S1 WDT Time-out select bit 1

0 S0 WDT Time-out select bit 0

S2 S1 S0 Selected Time-out
0 0 0 (214 - 1) machine cycles, 16.3 ms @ 12 MHz
0 0 1 (215 - 1) machine cycles, 32.7 ms @ 12 MHz
0 1 0 (216 - 1) machine cycles, 65.5 ms @ 12 MHz
0 1 1 (217 - 1) machine cycles, 131 ms @ 12 MHz
1 0 0 (218 - 1) machine cycles, 262 ms @ 12 MHz
1 0 1 (219 - 1) machine cycles, 542 ms @ 12 MHz
1 1 0 (220 - 1) machine cycles, 1.05 s @ 12 MHz
1 1 1 (221 - 1) machine cycles, 2.09 s @ 12 MHz

Reset value XXXX X000

6.8.2 WDT during Power Down and Idle

In Power Down mode the oscillator stops, which means the WDT also stops. While in Power Down mode the
user does not need to service the WDT. There are 2 methods of exiting Power Down mode: by a hardware reset
or via a level activated external interrupt which is enabled prior to entering Power Down mode. When Power
Down is exited with hardware reset, servicing the WDT should occur as it normally should whenever the TS80C54/
58X2 is reset. Exiting Power Down with an interrupt is significantly different. The interrupt is held low long
enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the
WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is
pulled high. It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is best to reset the
WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the TS80C54/58X2 while in
Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter
Idle mode.

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TS80C54X2/C58X2
TS87C54X2/C58X2
6.9 ONCETM Mode (ON Chip Emulation)
The ONCE mode facilitates testing and debugging of systems using TS80C54/58X2 without removing the circuit
from the board. The ONCE mode is invoked by driving certain pins of the TS80C54/58X2; the following sequence
must be exercised:
● Pull ALE low while the device is in reset (RST high) and PSEN is high.
● Hold ALE low as RST is deactivated.
While the TS80C54/58X2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit Table 26.
shows the status of the port pins during ONCE mode.
Normal operation is restored when normal reset is applied.
Table 17. External Pin Status during ONCE Mode
ALE PSEN Port 0 Port 1 Port 2 Port 3 XTAL1/2
Weak pull-up Weak pull-up Float Weak pull-up Weak pull-up Weak pull-up Active

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 TS80C54X2/C58X2
TS87C54X2/C58X2
6.10 Power-Off Flag
The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset.
A cold start reset is the one induced by VCC switch-on. A warm start reset occurs while VCC is still applied to
the device and could be generated for example by an exit from power-down.
The power-off flag (POF) is located in PCON register (See Table 18.). POF is set by hardware when VCC rises
from 0 to its nominal voltage. The POF can be set or cleared by software allowing the user to determine the type
of reset.
The POF value is only relevant with a Vcc range from 4.5V to 5.5V. For lower Vcc value, reading POF bit will
return indeterminate value.

Table 18. PCON Register

PCON - Power Control Register (87h)
7 6 5 4 3 2 1 0
SMOD1 SMOD0 - POF GF1 GF0 PD IDL

Bit Bit
Description
Number Mnemonic
Serial port Mode bit 1
7 SMOD1
Set to select double baud rate in mode 1, 2 or 3.

Serial port Mode bit 0

6 SMOD0 Clear to select SM0 bit in SCON register.
Set to to select FE bit in SCON register.

Reserved
5 -
The value read from this bit is indeterminate. Do not set this bit.

Power-Off Flag
4 POF Clear to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.

General purpose Flag

3 GF1 Cleared by user for general purpose usage.
Set by user for general purpose usage.

General purpose Flag

2 GF0 Cleared by user for general purpose usage.
Set by user for general purpose usage.

Power-Down mode bit

1 PD Cleared by hardware when reset occurs.
Set to enter power-down mode.

Idle mode bit

0 IDL Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.

Reset Value = 00X1 0000b

Not bit addressable

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6.11 Reduced EMI Mode
The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data
memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE
signal can be disabled by setting AO bit.
The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer output but
remains active during MOVX and MOVC instructions and external fetches. During ALE disabling, ALE pin is
weakly pulled high.
Table 19. AUXR Register
AUXR - Auxiliary Register (8Eh)
7 6 5 4 3 2 1 0
- - - - - - RESERVED AO

Bit Bit
Description
Number Mnemonic
Reserved
7 -
The value read from this bit is indeterminate. Do not set this bit.

Reserved
6 -
The value read from this bit is indeterminate. Do not set this bit.

Reserved
5 -
The value read from this bit is indeterminate. Do not set this bit.

Reserved
4 -
The value read from this bit is indeterminate. Do not set this bit.

Reserved
3 -
The value read from this bit is indeterminate. Do not set this bit.

Reserved
2 -
The value read from this bit is indeterminate. Do not set this bit.

This bit must be set for normal operation

1 RESERVED For ALE disabling, program 03H in AUXR register.
For standard operation, program 02H in AUXR register.

ALE Output bit

0 AO Clear to restore ALE operation during internal fetches.
Set to disable ALE operation during internal fetches.

Reset Value = XXXX XX00b

Not bit addressable

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7. TS80C54/58X2 ROM

7.1 ROM Structure

The TS80C54/58X2 ROM memory is in three different arrays:
● the code array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16/32 Kbytes.
● the encryption array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 bytes.
● the signature array:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 bytes.

7.2 ROM Lock System

The program Lock system, when programmed, protects the on-chip program against software piracy.

7.2.1 Encryption Array

Within the ROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s). Every time a
byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This
byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with
the encryption array in the unprogrammed state, will return the code in its original, unmodified form.
When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying
the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a
verification routine will display the content of the encryption array. For this reason all the unused code bytes
should be programmed with random values. This will ensure program protection.

7.2.2 Program Lock Bits

The lock bits when programmed according to Table 20. will provide different level of protection for the on-chip
code and data.
Table 20. Program Lock bits
Program Lock Bits
Securi- Protection description
LB1 LB2 LB3
ty level
No program lock features enabled. Code verify will still be encrypted by the encryption
1 U U U array if programmed. MOVC instruction executed from external program memory returns
non encrypted data.
MOVC instruction executed from external program memory are disabled from fetching
2 P U U
code bytes from internal memory, EA is sampled and latched on reset.

U: unprogrammed
P: programmed

7.2.3 Signature bytes

The TS80C54/58X2 contains 4 factory programmed signatures bytes. To read these bytes, perform the process
described in section 8.3.

7.2.4 Verify Algorithm

Refer to 8.3.4

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8. TS87C54/58X2 EPROM

8.1 EPROM Structure

The TS87C54/58X2 EPROM is divided in two different arrays:
● the code array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16/32 Kbytes.
● the encryption array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 bytes.
In addition a third non programmable array is implemented:
● the signature array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 bytes.

8.2 EPROM Lock System

The program Lock system, when programmed, protects the on-chip program against software piracy.

8.2.1 Encryption Array

Within the EPROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s). Every time
a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This
byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with
the encryption array in the unprogrammed state, will return the code in its original, unmodified form.
When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying
the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a
verification routine will display the content of the encryption array. For this reason all the unused code bytes
should be programmed with random values. This will ensure program protection.

8.2.2 Program Lock Bits

The three lock bits, when programmed according to Table 21., will provide different level of protection for the
on-chip code and data.
Table 21. Program Lock bits
Program Lock Bits
Security Protection description
LB1 LB2 LB3
level
No program lock features enabled. Code verify will still be encrypted by the encryption
1 U U U array if programmed. MOVC instruction executed from external program memory
returns non encrypted data.
MOVC instruction executed from external program memory are disabled from fetching
2 P U U code bytes from internal memory, EA is sampled and latched on reset, and further
programming of the EPROM is disabled.
3 U P U Same as 2, also verify is disabled.
4 U U P Same as 3, also external execution is disabled.

U: unprogrammed,
P: programmed
WARNING: Security level 2 and 3 should only be programmed after EPROM and Core verification.

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8.2.3 Signature bytes
The TS87C54/58X2 contains 4 factory programmed signatures bytes. To read these bytes, perform the process
described in section 8.3.

8.3 EPROM Programming

8.3.1 Set-up modes

In order to program and verify the EPROM or to read the signature bytes, the TS87C54/58X2 is placed in specific
set-up modes (See Figure 11.).
Control and program signals must be held at the levels indicated in Table 22.

8.3.2 Definition of terms

Address Lines:P1.0-P1.7, P2.0-P2.5, P3.4 respectively for A0-A14 (P2.5 (A13) for TS87C54X2, P3.4 (A14) for
TS87C58X2).
Data Lines:P0.0-P0.7 for D0-D7
Control Signals:RST, PSEN, P2.6, P2.7, P3.3, P3.6, P3.7.
Program Signals:ALE/PROG, EA/VPP.
Table 22. EPROM Set-Up Modes
ALE/ EA/
Mode RST PSEN P2.6 P2.7 P3.3 P3.6 P3.7
PROG VPP

Program Code data 1 0 12.75V 0 1 1 1 1

Verify Code data 1 0 1 1 0 0 1 1

Program Encryption Array

1 0 12.75V 0 1 1 0 1
Address 0-3Fh

Read Signature Bytes 1 0 1 1 0 0 0 0

Program Lock bit 1 1 0 12.75V 1 1 1 1 1

Program Lock bit 2 1 0 12.75V 1 1 1 0 0

Program Lock bit 3 1 0 12.75V 1 0 1 1 0

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TS87C54X2/C58X2

+5V

PROGRAM EA/VPP VCC

SIGNALS* ALE/PROG

P0.0-P0.7 D0-D7

RST
PSEN P1.0-P1.7 A0-A7
P2.6
CONTROL
P2.7
SIGNALS* P2.0-P2.5, A8-A14
P3.3
P3.4
P3.6
P3.7

4 to 6 MHz XTAL1 VSS

GND

* See Table 31. for proper value on these inputs

Figure 11. Set-Up Modes Configuration

8.3.3 Programming Algorithm

The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and decreases the number of pulses
applied during byte programming from 25 to 1.
To program the TS80C54/58X2 the following sequence must be exercised:
● Step 1: Activate the combination of control signals.
● Step 2: Input the valid address on the address lines.
● Step 3: Input the appropriate data on the data lines.
● Step 4: Raise EA/VPP from VCC to VPP (typical 12.75V).
● Step 5: Pulse ALE/PROG once.
● Step 6: Lower EA/VPP from VPP to VCC
Repeat step 2 through 6 changing the address and data for the entire array or until the end of the object file is
reached (See Figure 12.).

8.3.4 Verify algorithm

Code array verify must be done after each byte or block of bytes is programmed. In either case, a complete verify
of the programmed array will ensure reliable programming of the TS87C54/58X2.
P 2.7 is used to enable data output.
To verify the TS87C54/58X2 code the following sequence must be exercised:
● Step 1: Activate the combination of program and control signals.
● Step 2: Input the valid address on the address lines.
● Step 3: Read data on the data lines.
Repeat step 2 through 3 changing the address for the entire array verification (See Figure 12.)
The encryption array cannot be directly verified. Verification of the encryption array is done by observing that the
code array is well encrypted.

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TS87C54X2/C58X2
Programming Cycle Read/Verify Cycle

A0-A12

D0-D7 Data In Data Out

100µs
ALE/PROG

12.75V
EA/VPP 5V
0V
Control sig-
nals

Figure 12. Programming and Verification Signal’s Waveform

8.4 EPROM Erasure (Windowed Packages Only)

Erasing the EPROM erases the code array, the encryption array and the lock bits returning the parts to full
functionality.
Erasure leaves all the EPROM cells in a 1’s state (FF).

8.4.1 Erasure Characteristics

The recommended erasure procedure is exposure to ultraviolet light (at 2537 Å) to an integrated dose at least 15
W-sec/cm2. Exposing the EPROM to an ultraviolet lamp of 12,000 µW/cm2 rating for 30 minutes, at a distance
of about 25 mm, should be sufficient. An exposure of 1 hour is recommended with most of standard erasers.
Erasure of the EPROM begins to occur when the chip is exposed to light with wavelength shorter than approximately
4,000 Å. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources
over an extended time (about 1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause
inadvertent erasure. If an application subjects the device to this type of exposure, it is suggested that an opaque
label be placed over the window.

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TS87C54X2/C58X2
9. Signature Bytes
The TS87C54/58X2 has four signature bytes in location 30h, 31h, 60h and 61h. To read these bytes follow the
procedure for EPROM verify but activate the control lines provided in Table 31. for Read Signature Bytes. Table
23. shows the content of the signature byte for the TS80C54/58X2.
Table 23. Signature Bytes Content
Location Contents Comment
30h 58h Manufacturer Code: Atmel Wireless & Microcontrollers
31h 57h Family Code: C51 X2
60h 37h Product name: TS80C58X2
60h B7h Product name: TS87C58X2
60h 3Bh Product name: TS80C54X2
60h BBh Product name: TS87C54X2
61h FFh Product revision number

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 TS80C54X2/C58X2
TS87C54X2/C58X2
10. Electrical Characteristics

10.1 Absolute Maximum Ratings (1)

Ambiant Temperature Under Bias:
C = commercial 0°C to 70°C
I = industrial -40°C to 85°C
Storage Temperature -65°C to + 150°C
Voltage on VCC to VSS -0.5 V to + 7 V
Voltage on VPP to VSS -0.5 V to + 13 V
Voltage on Any Pin to VSS -0.5 V to VCC + 0.5 V
Power Dissipation 1 W(2)

NOTES
1. Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions may affect device reliability.
2. This value is based on the maximum allowable die temperature and the thermal resistance of the package.

10.2 Power consumption measurement

Since the introduction of the first C51 devices, every manufacturer made operating Icc measurements under reset,
which made sense for the designs were the CPU was running under reset. In Atmel new devices, the CPU is no
more active during reset, so the power consumption is very low but is not really representative of what will happen
in the customer system. That’s why, while keeping measurements under Reset, Atmel presents a new way to
measure the operating Icc:
Using an internal test ROM, the following code is executed:
Label: SJMP Label (80 FE)
Ports 1, 2, 3 are disconnected, Port 0 is tied to FFh, EA = Vcc, RST = Vss, XTAL2 is not connected and XTAL1
is driven by the clock.
This is much more representative of the real operating Icc.

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10.3 DC Parameters for Standard Voltage
TA = 0°C to +70°C; VSS = 0 V; VCC = 5 V ± 10%; F = 0 to 40 MHz.
TA = -40°C to +85°C; VSS = 0 V; VCC = 5 V ± 10%; F = 0 to 40 MHz.
Table 24. DC Parameters in Standard Voltage

Symbol Parameter Min Typ Max Unit Test Conditions

VIL Input Low Voltage -0.5 0.2 VCC - 0.1 V

VIH Input High Voltage except XTAL1, RST 0.2 VCC + 0.9 VCC + 0.5 V

VIH1 Input High Voltage, XTAL1, RST 0.7 VCC VCC + 0.5 V

VOL Output Low Voltage, ports 1, 2, 3 (6) 0.3 V IOL = 100 µA(4)
0.45 V
IOL = 1.6 mA(4)
1.0 V
IOL = 3.5 mA(4)

VOL1 Output Low Voltage, port 0 (6) 0.3 V IOL = 200 µA(4)
0.45 V
IOL = 3.2 mA(4)
1.0 V
IOL = 7.0 mA(4)

VOL2 Output Low Voltage, ALE, PSEN 0.3 V IOL = 100 µA(4)
0.45 V
IOL = 1.6 mA(4)
1.0 V
IOL = 3.5 mA(4)

VOH Output High Voltage, ports 1, 2, 3 VCC - 0.3 V IOH = -10 µA

VCC - 0.7 V IOH = -30 µA
VCC - 1.5 V IOH = -60 µA
VCC = 5 V ± 10%

VOH1 Output High Voltage, port 0 VCC - 0.3 V IOH = -200 µA

VCC - 0.7 V IOH = -3.2 mA
VCC - 1.5 V IOH = -7.0 mA
VCC = 5 V ± 10%

VOH2 Output High Voltage,ALE, PSEN VCC - 0.3 V IOH = -100 µA

VCC - 0.7 V IOH = -1.6 mA
VCC - 1.5 V IOH = -3.5 mA
VCC = 5 V ± 10%

RRST RST Pulldown Resistor 50 90 (5) 200 kΩ

IIL Logical 0 Input Current ports 1, 2 and 3 -50 µA Vin = 0.45 V

ILI Input Leakage Current ±10 µA 0.45 V < Vin < VCC

ITL Logical 1 to 0 Transition Current, ports 1, 2, 3 -650 µA Vin = 2.0 V

CIO Capacitance of I/O Buffer 10 pF Fc = 1 MHz

TA = 25°C

IPD Power Down Current 20 (5) 50 µA 2.0 V < VCC < 5.5 V(3)

ICC Power Supply Current Maximum values, X1 1 + 0.4 Freq

under mode: (7) (MHz) VCC = 5.5 V(1)
@12MHz 5.8 mA
RESET
@16MHz 7.4

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TS87C54X2/C58X2
Symbol Parameter Min Typ Max Unit Test Conditions

ICC Power Supply Current Maximum values, X1 3 + 0.6 Freq

mode: (7) (MHz)
operating @12MHz 10.2
mA VCC = 5.5 V(8)
@16MHz 12.6

ICC Power Supply Current Maximum values, X1 0.25+0.3Freq

mode: (7) (MHz)
idle mA VCC = 5.5 V(2)
@12MHz 3.9
@16MHz 5.1

10.4 DC Parameters for Low Voltage

TA = 0°C to +70°C; VSS = 0 V; VCC = 2.7 V to 5.5 V ± 10%; F = 0 to 30 MHz.
TA = -40°C to +85°C; VSS = 0 V; VCC = 2.7 V to 5.5 V ± 10%; F = 0 to 30 MHz.
Table 25. DC Parameters for Low Voltage

Symbol Parameter Min Typ Max Unit Test Conditions

VIL Input Low Voltage -0.5 0.2 VCC - 0.1 V

VIH Input High Voltage except XTAL1, RST 0.2 VCC + 0.9 VCC + 0.5 V

VIH1 Input High Voltage, XTAL1, RST 0.7 VCC VCC + 0.5 V

VOL Output Low Voltage, ports 1, 2, 3 (6) 0.45 V IOL = 0.8 mA(4)

VOL1 Output Low Voltage, port 0, ALE, PSEN (6) 0.45 V IOL = 1.6 mA(4)

VOH Output High Voltage, ports 1, 2, 3 0.9 VCC V IOH = -10 µA

VOH1 Output High Voltage, port 0, ALE, PSEN 0.9 VCC V IOH = -40 µA

IIL Logical 0 Input Current ports 1, 2 and 3 -50 µA Vin = 0.45 V

ILI Input Leakage Current ±10 µA 0.45 V < Vin < VCC

ITL Logical 1 to 0 Transition Current, ports 1, 2, 3 -650 µA Vin = 2.0 V

RRST RST Pulldown Resistor 50 90 (5) 200 kΩ

CIO Capacitance of I/O Buffer 10 pF Fc = 1 MHz

TA = 25°C

IPD Power Down Current 20 (5) 50 µA VCC = 2.0 V to 5.5 V(3)

(5)
10 30 VCC = 2.0 V to 3.3 V(3)

ICC Power Supply Current Maximum values, X1 1 + 0.2 Freq

under mode: (7) (MHz) VCC = 3.3 V(1)
@12MHz 3.4 mA
RESET
@16MHz 4.2

ICC Power Supply Current Maximum values, X1 1 + 0.3 Freq

operating mode: (7) (MHz) VCC = 3.3 V(8)
@12MHz 4.6 mA
@16MHz 5.8

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TS87C54X2/C58X2
Symbol Parameter Min Typ Max Unit Test Conditions

ICC Power Supply Current Maximum values, X1 0.15 Freq

idle mode: (7) (MHz) + 0.2 mA VCC = 3.3 V(2)
@12MHz 2
@16MHz 2.6

NOTES
1. ICC under reset is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 17.), VIL = VSS + 0.5 V,
VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used..
2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL2
N.C; Port 0 = VCC; EA = RST = VSS (see Figure 15.).
3. Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Figure 16.).
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise is
due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst
cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
7. For other values, please contact your sales office.
8. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 17.), VIL = VSS + 0.5 V,
VIH = VCC - 0.5V; XTAL2 N.C.; EA = Port 0 = VCC; RST = VSS. The internal ROM runs the code 80 FE (label: SJMP label). ICC would be slightly
higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is the worst case.

VCC

ICC
VCC VCC
P0
VCC

RST EA

(NC) XTAL2
CLOCK XTAL1
SIGNAL
VSS

All other pins are disconnected.

Figure 13. ICC Test Condition, under reset

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 TS80C54X2/C58X2
TS87C54X2/C58X2

VCC

ICC
VCC VCC

Reset = Vss after a high pulse P0

during at least 24 clock cycles
RST EA

(NC) XTAL2
CLOCK XTAL1
SIGNAL All other pins are disconnected.
VSS

Figure 14. Operating ICC Test Condition

VCC

ICC
VCC VCC

Reset = Vss after a high pulse P0

during at least 24 clock cycles
RST EA

(NC) XTAL2
CLOCK XTAL1
SIGNAL All other pins are disconnected.
VSS

Figure 15. ICC Test Condition, Idle Mode

VCC
ICC
VCC VCC

P0
Reset = Vss after a high pulse
during at least 24 clock cycles
RST EA

(NC) XTAL2
XTAL1
VSS All other pins are disconnected.

Figure 16. ICC Test Condition, Power-Down Mode

VCC-0.5V 0.7VCC
0.45V 0.2VCC-0.1
TCHCL TCLCH
TCLCH = TCHCL = 5ns.

Figure 17. Clock Signal Waveform for ICC Tests in Active and Idle Modes

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TS80C54X2/C58X2
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10.5 AC Parameters

10.5.1 Explanation of the AC Symbols

Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters,
depending on their positions, stand for the name of a signal or the logical status of that signal. The following is
a list of all the characters and what they stand for.
Example:TAVLL = Time for Address Valid to ALE Low.
TLLPL = Time for ALE Low to PSEN Low.
TA = 0 to +70°C (commercial temperature range); VSS = 0 V; VCC = 5 V ± 10%; -M and -V ranges.
TA = -40°C to +85°C (industrial temperature range); VSS = 0 V; VCC = 5 V ± 10%; -M and -V ranges.
TA = 0 to +70°C (commercial temperature range); VSS = 0 V; 2.7 V < VCC < 5.5 V; -L range.
TA = -40°C to +85°C (industrial temperature range); VSS = 0 V; 2.7 V < VCC < 5.5 V; -L range.

Table 26. gives the maximum applicable load capacitance for Port 0, Port 1, 2 and 3, and ALE and PSEN signals.
Timings will be guaranteed if these capacitances are respected. Higher capacitance values can be used, but timings
will then be degraded.

Table 26. Load Capacitance versus speed range, in pF

-M -V -L
Port 0 100 50 100
Port 1, 2, 3 80 50 80
ALE / PSEN 100 30 100

Table 28., Table 31. and Table 34. give the description of each AC symbols.

Table 29., Table 32. and Table 35. give for each range the AC parameter.

Table 30., Table 33. and Table 36. give the frequency derating formula of the AC parameter. To calculate each
AC symbols, take the x value corresponding to the speed grade you need (-M, -V or -L) and replace this value
in the formula. Values of the frequency must be limited to the corresponding speed grade:
Table 27. Max frequency for derating formula regarding the speed grade
-M X1 mode -M X2 mode -V X1 mode -V X2 mode -L X1 mode -L X2 mode
Freq (MHz) 40 20 40 30 30 20
T (ns) 25 50 25 33.3 33.3 50

Example:
TLLIV in X2 mode for a -V part at 20 MHz (T = 1/20E6 = 50 ns):
x= 22 (Table 30.)
T= 50ns
TLLIV= 2T - x = 2 x 50 - 22 = 78ns

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10.5.2 External Program Memory Characteristics

Table 28. Symbol Description

Symbol Parameter
T Oscillator clock period

TLHLL ALE pulse width

TAVLL Address Valid to ALE

TLLAX Address Hold After ALE

TLLIV ALE to Valid Instruction In

TLLPL ALE to PSEN

TPLPH PSEN Pulse Width

TPLIV PSEN to Valid Instruction In

TPXIX Input Instruction Hold After PSEN

TPXIZ Input Instruction FloatAfter PSEN

TPXAV PSEN to Address Valid

TAVIV Address to Valid Instruction In

TPLAZ PSEN Low to Address Float

Table 29. AC Parameters for Fix Clock

Speed -M -V -V -L -L Units
40 MHz X2 mode standard mode X2 mode standard mode
30 MHz 40 MHz 20 MHz 30 MHz
60 MHz equiv. 40 MHz equiv.

Symbol Min Max Min Max Min Max Min Max Min Max
T 25 33 25 50 33 ns

TLHLL 40 25 42 35 52 ns

TAVLL 10 4 12 5 13 ns

TLLAX 10 4 12 5 13 ns

TLLIV 70 45 78 65 98 ns

TLLPL 15 9 17 10 18 ns

TPLPH 55 35 60 50 75 ns

TPLIV 35 25 50 30 55 ns

TPXIX 0 0 0 0 0 ns

TPXIZ 18 12 20 10 18 ns

TAVIV 85 53 95 80 122 ns

TPLAZ 10 10 10 10 10 ns

Rev. C - 15 January, 2001 47

TS80C54X2/C58X2
TS87C54X2/C58X2
Table 30. AC Parameters for a Variable Clock: derating formula

Symbol Type Standard X2 Clock -M -V -L Units

Clock

TLHLL Min 2T-x T-x 10 8 15 ns

TAVLL Min T-x 0.5 T - x 15 13 20 ns

TLLAX Min T-x 0.5 T - x 15 13 20 ns

TLLIV Max 4T-x 2T-x 30 22 35 ns

TLLPL Min T-x 0.5 T - x 10 8 15 ns

TPLPH Min 3T-x 1.5 T - x 20 15 25 ns

TPLIV Max 3T-x 1.5 T - x 40 25 45 ns

TPXIX Min x x 0 0 0 ns

TPXIZ Max T-x 0.5 T - x 7 5 15 ns

TAVIV Max 5T-x 2.5 T - x 40 30 45 ns

TPLAZ Max x x 10 10 10 ns

10.5.3 External Program Memory Read Cycle

12 TCLCL
TLHLL TLLIV
ALE TLLPL
TPLPH
PSEN TPXAV
TLLAX TPXIZ
TPLIV
TAVLL TPLAZ TPXIX
PORT 0 INSTR IN A0-A7 INSTR IN A0-A7 INSTR IN

TAVIV
PORT 2 ADDRESS
OR SFR-P2 ADDRESS A8-A15 ADDRESS A8-A15

Figure 18. External Program Memory Read Cycle

48 Rev. C - 15 January, 2001

 TS80C54X2/C58X2
TS87C54X2/C58X2
10.5.4 External Data Memory Characteristics
Table 31. Symbol Description
Symbol Parameter

TRLRH RD Pulse Width

TWLWH WR Pulse Width

TRLDV RD to Valid Data In

TRHDX Data Hold After RD

TRHDZ Data Float After RD

TLLDV ALE to Valid Data In

TAVDV Address to Valid Data In

TLLWL ALE to WR or RD

TAVWL Address to WR or RD

TQVWX Data Valid to WR Transition

TQVWH Data set-up to WR High

TWHQX Data Hold After WR

TRLAZ RD Low to Address Float

TWHLH RD or WR High to ALE high

Rev. C - 15 January, 2001 49

TS80C54X2/C58X2
TS87C54X2/C58X2
Table 32. AC Parameters for a Fix Clock

Speed -M -V -V -L -L Units
40 MHz X2 mode standard mode X2 mode standard mode
30 MHz 40 MHz 20 MHz 30 MHz
60 MHz equiv. 40 MHz equiv.

Symbol Min Max Min Max Min Max Min Max Min Max

TRLRH 130 85 135 125 175 ns

TWLWH 130 85 135 125 175 ns

TRLDV 100 60 102 95 137 ns

TRHDX 0 0 0 0 0 ns

TRHDZ 30 18 35 25 42 ns

TLLDV 160 98 165 155 222 ns

TAVDV 165 100 175 160 235 ns

TLLWL 50 100 30 70 55 95 45 105 70 130 ns

TAVWL 75 47 80 70 103 ns

TQVWX 10 7 15 5 13 ns

TQVWH 160 107 165 155 213 ns

TWHQX 15 9 17 10 18 ns

TRLAZ 0 0 0 0 0 ns

TWHLH 10 40 7 27 15 35 5 45 13 53 ns

50 Rev. C - 15 January, 2001

 TS80C54X2/C58X2
TS87C54X2/C58X2
Table 33. AC Parameters for a Variable Clock: derating formula

Symbol Type Standard X2 Clock -M -V -L Units

Clock

TRLRH Min 6T-x 3T-x 20 15 25 ns

TWLWH Min 6T-x 3T-x 20 15 25 ns

TRLDV Max 5T-x 2.5 T - x 25 23 30 ns

TRHDX Min x x 0 0 0 ns

TRHDZ Max 2T-x T-x 20 15 25 ns

TLLDV Max 8T-x 4T -x 40 35 45 ns

TAVDV Max 9T-x 4.5 T - x 60 50 65 ns

TLLWL Min 3T-x 1.5 T - x 25 20 30 ns

TLLWL Max 3T+x 1.5 T + x 25 20 30 ns

TAVWL Min 4T-x 2T-x 25 20 30 ns

TQVWX Min T-x 0.5 T - x 15 10 20 ns

TQVWH Min 7T-x 3.5 T - x 15 10 20 ns

TWHQX Min T-x 0.5 T - x 10 8 15 ns

TRLAZ Max x x 0 0 0 ns

TWHLH Min T-x 0.5 T - x 15 10 20 ns

TWHLH Max T+x 0.5 T + x 15 10 20 ns

10.5.5 External Data Memory Write Cycle

TWHLH
ALE

PSEN
TLLWL TWLWH

WR
TQVWX
TLLAX TQVWH TWHQX
PORT 0 A0-A7 DATA OUT

TAVWL
PORT 2 ADDRESS
OR SFR-P2 ADDRESS A8-A15 OR SFR P2

Figure 19. External Data Memory Write Cycle

Rev. C - 15 January, 2001 51

TS80C54X2/C58X2
TS87C54X2/C58X2
10.5.6 External Data Memory Read Cycle

TWHLH
ALE TLLDV

PSEN
TLLWL TRLRH
TRLDV
RD TRHDZ
TAVDV
TLLAX TRHDX
PORT 0 A0-A7 DATA IN
TRLAZ
TAVWL
PORT 2 ADDRESS
OR SFR-P2 ADDRESS A8-A15 OR SFR P2

Figure 20. External Data Memory Read Cycle

10.5.7 Serial Port Timing - Shift Register Mode

Table 34. Symbol Description
Symbol Parameter
TXLXL Serial port clock cycle time

TQVHX Output data set-up to clock rising edge

TXHQX Output data hold after clock rising edge

TXHDX Input data hold after clock rising edge

TXHDV Clock rising edge to input data valid

Table 35. AC Parameters for a Fix Clock

Speed -M -V -V -L -L Units
40 MHz X2 mode standard mode X2 mode standard mode
30 MHz 40 MHz 20 MHz 30 MHz
60 MHz equiv. 40 MHz equiv.

Symbol Min Max Min Max Min Max Min Max Min Max

TXLXL 300 200 300 300 400 ns

TQVHX 200 117 200 200 283 ns

TXHQX 30 13 30 30 47 ns

TXHDX 0 0 0 0 0 ns

TXHDV 117 34 117 117 200 ns

52 Rev. C - 15 January, 2001

 TS80C54X2/C58X2
TS87C54X2/C58X2
Table 36. AC Parameters for a Variable Clock: derating formula

Symbol Type Standard X2 Clock -M -V -L Units

Clock

TXLXL Min 12 T 6T ns

TQVHX Min 10 T - x 5T-x 50 50 50 ns

TXHQX Min 2T-x T-x 20 20 20 ns

TXHDX Min x x 0 0 0 ns

TXHDV Max 10 T - x 5 T- x 133 133 133 ns

10.5.8 Shift Register Timing Waveforms

INSTRUCTION 0 1 2 3 4 5 6 7 8

ALE
TXLXL
CLOCK
TXHQX
TQVXH
OUTPUT DATA 0 1 2 3 4 5 6 7

TXHDX SET TI
WRITE to SBUF TXHDV

INPUT DATA VALID VALID VALID VALID VALID VALID VALID VALID

SET RI
CLEAR RI

Figure 21. Shift Register Timing Waveforms

Rev. C - 15 January, 2001 53

TS80C54X2/C58X2
TS87C54X2/C58X2
10.5.9 EPROM Programming and Verification Characteristics
TA = 21°C to 27°C; VSS = 0V; VCC = 5V ± 10% while programming. VCC = operating range while verifying
Table 37. EPROM Programming Parameters
Symbol Parameter Min Max Units
VPP Programming Supply Voltage 12.5 13 V

IPP Programming Supply Current 75 mA

1/TCLCL Oscillator Frquency 4 6 MHz

TAVGL Address Setup to PROG Low 48 TCLCL

TGHAX Adress Hold after PROG 48 TCLCL

TDVGL Data Setup to PROG Low 48 TCLCL

TGHDX Data Hold after PROG 48 TCLCL

TEHSH (Enable) High to VPP 48 TCLCL

TSHGL VPP Setup to PROG Low 10 µs

TGHSL VPP Hold after PROG 10 µs

TGLGH PROG Width 90 110 µs

TAVQV Address to Valid Data 48 TCLCL

TELQV ENABLE Low to Data Valid 48 TCLCL

TEHQZ Data Float after ENABLE 0 48 TCLCL

10.5.10 EPROM Programming and Verification Waveforms

PROGRAMMING VERIFICATION
P1.0-P1.7
ADDRESS ADDRESS
P2.0-P2.5
P3.4-P3.5* TAVQV

P0 DATA IN DATA OUT

TDVGL TGHDX
TAVGL TGHAX
ALE/PROG
TSHGL TGHSL
TGLGH
EA/VPP VCC VPP VCC
TEHSH TELQV TEHQZ
CONTROL
SIGNALS
(ENABLE)
* 8KB: up to P2.4, 16KB: up to P2.5, 32KB: up to P3.4, 64KB: up to P3.5

Figure 22. EPROM Programming and Verification Waveforms

54 Rev. C - 15 January, 2001

 TS80C54X2/C58X2
TS87C54X2/C58X2
10.5.11 External Clock Drive Characteristics (XTAL1)
Table 38. AC Parameters
Symbol Parameter Min Max Units

TCLCL Oscillator Period 25 ns

TCHCX High Time 5 ns

TCLCX Low Time 5 ns

TCLCH Rise Time 5 ns

TCHCL Fall Time 5 ns

TCHCX/TCLCX Cyclic ratio in X2 mode 40 60 %

10.5.12 External Clock Drive Waveforms

VCC-0.5 V
0.7VCC
0.45 V 0.2VCC-0.1 V TCHCX
TCHCL TCLCX TCLCH
TCLCL

Figure 23. External Clock Drive Waveforms

10.5.13 AC Testing Input/Output Waveforms

VCC-0.5 V
0.2VCC+0.9
INPUT/OUTPUT 0.2VCC-0.1
0.45 V

Figure 24. AC Testing Input/Output Waveforms

AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement
are made at VIH min for a logic “1” and VIL max for a logic “0”.

10.5.14 Float Waveforms

FLOAT
VOH-0.1 V VLOAD VLOAD+0.1 V
VOL+0.1 V VLOAD-0.1 V

Figure 25. Float Waveforms

Rev. C - 15 January, 2001 55

TS80C54X2/C58X2
TS87C54X2/C58X2
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins
to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH ≥ ± 20mA.

10.5.15 Clock Waveforms

Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two.

STATE4 STATE5 STATE6 STATE1 STATE2 STATE3 STATE4 STATE5

INTERNAL
CLOCK P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2

XTAL2

ALE
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXTERNAL PROGRAM MEMORY FETCH EXECUTION OF A MOVX INSTRUCTION
PSEN

P0 DATA PCL OUT DATA PCL OUT DATA PCL OUT

SAMPLED SAMPLED SAMPLED
FLOAT FLOAT FLOAT

P2 (EXT) INDICATES ADDRESS TRANSITIONS

READ CYCLE
RD
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
P0 DPL OR Rt OUT

FLOAT
P2 INDICATES DPH OR P2 SFR TO PCH TRANSITION

WRITE CYCLE
WR PCL OUT (EVEN IF PROGRAM
MEMORY IS INTERNAL)
P0 DPL OR Rt OUT

DATA OUT PCL OUT (IF PROGRAM

MEMORY IS EXTERNAL)
P2 INDICATES DPH OR P2 SFR TO PCH TRANSITION

PORT OPERATION

OLD DATA NEW DATA

P0 PINS SAMPLED P0 PINS SAMPLED
MOV DEST P0
MOV DEST PORT (P1, P2, P3) P1, P2, P3 PINS SAMPLED P1, P2, P3 PINS SAMPLED
(INCLUDES INT0, INT1, TO, T1)

SERIAL PORT SHIFT CLOCK RXD SAMPLED RXD SAMPLED

TXD (MODE 0)

Figure 26. Clock Waveforms

This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins,
however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin
loading. Propagation also varies from output to output and component. Typically though (TA=25°C fully loaded)
RD and WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays
are incorporated in the AC specifications.

56 Rev. C - 15 January, 2001

 TS80C54X2/C58X2
TS87C54X2/C58X2
11. Ordering Information

TS 87C58X2 -M C B R

-M: VCC: 5V +/- 10%

40 MHz, X1 mode Packages:
20 MHz, X2 mode A: PDIL 40
-V: VCC: 5V +/- 10% B: PLCC 44
40 MHz, X1 mode C: PQFP F1 (13.9mm footprint)
30 MHz, X2 mode E: VQFP 44 (1.4mm)
-L: VCC: 2.7 to 5.5 V
30 MHz, X1 mode J: Window CDIL 40*
20 MHz, X2 mode K: Window CQPJ 44*
-E: Samples

Part Number
TS80C54X2yyy: 16k ROM, yyy is the customer code
TS80C58X2yyy: 32k ROM, yyy is the customer code
TS87C54X2: 16k OTP EPROM
TS87C58X2: 32k OTP EPROM
Conditioning
R: Tape & Reel
D: Dry Pack
B: Tape & Reel and
Temperature Range Dry Pack
C: Commercial 0 to 70oC
I: Industrial -40 to 85oC

(*) Check with Atmel Wireless & Microcontrollers Sales Office for availability. Ceramic packages (J, K) are available for proto-
typing, not for volume production. Ceramic packages are available for OTP only (TS87C54/58X2).

Table 39. Maximum Clock Frequency

Code -M -V -L Unit
Standard Mode, oscillator frequency 40 40 30
MHz
Standard Mode, internal frequency 40 40 30
X2 Mode, oscillator frequency 20 30 20
MHz
X2 Mode, internal equivalent frequency 40 60 40

Rev. C - 15 January, 2001 57

TS80C54X2/C58X2
TS87C54X2/C58X2
Table 40. Possible Ordering Entries

TS80C54/58zzz ROM TS87C54/58 OTP

-MCA X X
-MCB X X
-MCC X X
-MCE X X
-VCA X X
-VCB X X
-VCC X X
-VCE X X
-LCA X X
-LCB X X
-LCC X X
-LCE X X
-MIA X X
-MIB X X
-MIC X X
-MIE X X
-VIA X X
-VIB X X
-VIC X X
-VIE X X
-LIA X X
-LIB X X
-LIC X X
-LIE X X
-EA X
-EB X
-EC X
-EE X
-EJ C58X2 only
-EK C58X2 only

● -Ex for samples

● Tape and Reel available for B, C and E packages
● Dry pack mandatory for E packages

58 Rev. C - 15 January, 2001