Key Features:

 Spartan-3A XC3S50A/ XC3S200A FPGA

 Up to 68 user-I/O pins

 VQ-100 package

 Over 50,000/200,000 logic cells

Key components:
USB-POWER TWO UART
 XC3S50A/ XC3S200A

 OSCILLATOR – 12MHz
USB-UART
 FLASH – M25P20
USB-JTAG
XILINX
 USB Power
FREE I/O-28 SPARTAN - 3A CLOCK-12MHz
 On board USB Jtag
XC3S50A/XC3S200A
 USB to serial
SPI-ADC VQ100 FLASH-2Mb
 Two Rs232 I/O
 10bit SPI ADC
 8bit SPI DAC SPI-DAC 5 PUSH
 8LED & DIP SWITCH BUTTON

 5 PUSH BUTTON
 28 user I/O LCD 8 LED
DIP SWITCH
 LCD 16By2
BOARD POWERING

The3A-KIT-V2 board can work on USB power you can also connect external 5VDc.
supply. When J5 jumper is placed power is used from USB connector. When user
want to use external 5VDC supply remove J5 jumper.

LED’s and DIP Switches Interface

The3A-KIT-V2 board has 8 individual bidirectional I/O’s. Each I/O is connected

with a surface-mount LED and aDIP switch. A LED is assigned to each I/O to
indicate its data status when I/O is configured as input. DIP switch is used to
provide digital input (i.e. logic 0 and logic 1) to the FPGA.

The LED can display the output data value of I/O by configuring it as output and
keeping its corresponding DIP switch at 0 positions.

Pin Assignment (UCF Location) for IOs:

DIP Signal XC3S50A-

Switch Name VQ100
TL1 P40
TL2 P37
TL3 P36
TL4 P35
SW5
TL5 P34
TL6 P33
TL7 P32
TL8 P28
Pushbuttons Interface

The 3A-KIT-V2 board has 5 individual pushbuttons for input purpose.The

pushbuttons are read as 1 when pushed. They are read as 0 in normal (un pressed)
condition. Pushbuttons are labeled as SW1 TO SW4 & RESET.

Pin Assignment (UCF Location) for Pushbuttons:

Signal XC3S50A
Active
Name -VQ100

SW1 P97 HI
SW2 P7 HI
SW3 P24 HI
SW4 P21 HI
RESET P48 LOW
ADC Interface

The 3A-KIT-V2 board includes anADC MCP3004. The ADC has 4 analog input
channels. The channels are selected by setting the address pins of ADC. The analog
input to all channels is given by external circuit through relimate pins. The other
controlling signals of ADC are interfaced with FPGA board as shown in following
figure. VREF is connected to 3.3V, so analog voltage input rang of all channel is 0 to
3.3V.

Pin assignment (UCF Location) for ADC:

XC3S50A-
Signal Name VQ100
CLK P53
CS P61
DIN P46
DOUT P51
DAC Interface

The 3A-KIT-V2 board includes 8-bit 4 channels, digital-to-analog converter

(DACs)DAC084S085. DAC allows easy interface to most popular microprocessor
buses and output ports. DAC works on 3.3V. The following figure shows the
interfacing diagram of DAC with FPGA Board.VREF is connected to 3.3V, so analog
voltage output rang of all channel is 0 to 3.3V.

Pin Assignment (UCF Location) DAC084S085:

XC3S50A-
Signal Name VQ100
CS P31
CLK P53
DIN P46
RS232 Serial Port

The 3A-KIT-V2board has two RS-232 serial ports:

 J2 connector
 J4 connector
The J2 & J4 connector connects directly to the serial port connector available on
most personal computers and Workstations via a standard straight-through serial
cable.

TheFPGA supplies serial output data using LVTTL or LVCMOS levels to the RS-232
voltage converterwhich converts the logic value provided by FPGA Board to the
appropriate RS-232 voltage level and vice-versa. MAX 3232 is used as voltage
converter which has as 3.3V as logic high.

Pin Assignment (UCF Location) for RS232 Serial Ports:

Signal J2 J4
Name
TxD_F P62 P64
RxD_F P39 P68
USB Interface

The 3A-KIT-V2boardhas USB interface using device FT2232HL from FTDI. This act
as USB to UART converter so that Communication with FPGA can accomplished by
USB port.

Pin Assignment (UCF Location) for USB interface:

Signal XC3S50A-
Name VQ100
USB_Rx P82
USB_TX P78

Clock Sources

The 3A-KIT-V2board supports clock input sources which are listed below.
 The board includes an on-board 12 MHz clock oscillator

Signal XC3S50A-
Name VQ100

clock P71
LCD Interface

The 3A-KIT-V2 includes 2 lines by 16 characters LCD (liquid crystal display)

Module. The dot matrix LCD displays alphanumeric characters, numbers and
symbols. For displaying characters, numbers and symbol, user needs to send
8 bit ASCII value on data pins (Data0-Data8). The user can control the LCD
display by controlling control lines (RS, EN) and sending command codes on
data pins. All the functions required for controlling LCD backlight are
provided internally on board. Internal refresh is provided by the controller.
The Interface details of the LCD display are as shown in figure 1.
UCF Location:
UCF location for LCD

Pin Description Location

RS P60
EN P59
Data0 P57
Data1 P56
Data2 P52
Data3 P50
Data4 P49
Data5 P44
Data6 P43
Data7 P41