IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO.

8, AUGUST 2018 3521

Characterization and Optimization of Inverted-T

FinFET Under Nanoscale Dimensions
Eunseon Yu , Student Member, IEEE , Keun Heo , and Seongjae Cho , Member, IEEE

Abstract — In this paper, a p-type inverted-T FinFET As the scaling technology reaches the nanoscale range,
(IT FinFET) has been optimally structured. Focus is made reduced ON-state current (ION ) and severe short-channel effects
on analyzing the inferior characteristics reported from the (SCEs) cause performance degradation. Due to the diffi-
previously fabricated IT FinFETs, and obtaining better per-
formances through a novel structure. IT FinFET has a higher culty in simply shrinking the device size, various configu-
layout efficiency and can thus provide larger drain cur- rations of electronic devices have been introduced in order
rent (ID ) under the same dimension as that of a silicon-on- to overcome and mitigate the SCEs, for example, silicon-on-
insulator (SOI) FinFET by securing the extended channels insulator (SOI) metal–oxide–semiconductor field-effect tran-
of ultrathin body (UTB) on the field region. We closely sistors (MOSFETs), double-gate MOSFET, FinFET, and gate-
observe the leverages of fin width (Wfin ), UTB height (HUTB ),
and gate length (Lg ) on the operation characteristics using all-around MOSFET [1]–[10]. Since 2011, FinFET as one of
a 3-D technology computer-aided design simulation with the 3-D channel transistors has been utilized for mass produc-
quantum-mechanical models. Wfin below 10 nm is evaluated tion of microchips [11]. Owing to the merits by 3-D device
to be suitable for strong gate controllability. We first examine structure, gate controllability can be improved. However, there
a critical HUTB , beyond which a higher drive current is not are some challenges related to electrical characteristics and
obtained even with a greater channel width than that of
FinFET. When HUTB = 3 and 10 nm, IT FinFET yields 13.3% fabrication, following the scaling technology node. Although
and 142% of saturation current improvement compared with reducing the number of fins per area can be one solution
SOI FinFET under the same footprint. At extremely scaled for area scaling, there is a tradeoff relationship between area
Lg , although the immunity against short-channel effects is scaling and performance, because area scaling induces effec-
slightly weaker than that of SOI FinFET, optimally designed tive channel width (Wchannel ) reduction. Degradation of ION
IT FinFET can produce a higher current and demonstrates
shorter intrinsic delay times. results in increased gate delay time and overall performance
degradation of the circuit system. Instead of reducing the
Index Terms — 3-D technology computer-aided design
(TCAD) simulation, high current drive, high performance number of fins, higher fin height (Hfin ) and narrower fin width
(HP), intrinsic gate delay, inverted-T FinFET (IT Fin- (Wfin ) can be used to realize higher ION in a limited cell area
FET), low power operation, short-channel effects (SCEs), [9]. Unfortunately, there are some drawbacks with FinFETs:
silicon-on-insulator (SOI) FinFET, wavy FinFET. inferior uniformity between fin shapes, fin bottom erosion,
gate buckling, structural instability while etching and cleaning
I. I NTRODUCTION
owing to the high aspect ratio (Hfin /Wfin ), and low ION due
S EMICONDUCTOR devices have been deeply scaled
down from the micrometer range to tens of nanometers
to achieve high-speed and low-power operation capabilities.
to the stronger quantum-mechanical effects with channel area
reduction [12], [13]. In order to achieve a high drive current
with the limited size and to lessen the burden on the process
Manuscript received February 27, 2018; revised April 18, 2018; architecture, inverted-T FinFET (IT FinFET) can be a solution.
accepted June 5, 2018. Date of publication June 26, 2018; date of Note that the upper case “T” is from the configuration of the
current version July 23, 2018. This work was supported in part by
the Ministry of Trade, Industry and Energy and Korea Semiconductor inverted channel. To the best of our knowledge, IT FinFET
Research Consortium support program for the development of the future was first introduced in 2002 by a patent and in 2005 by a
semiconductor devices under Grant 10052928 and Grant 10080513, paper [14], [15]. IT FinFET uses a field region, between the
in part by the Ministry of Science, ICT and Future Planning under Grant
NRF-2017R1A2B2011570, and in part by the IDEC Program. The review fins in FinFET, as the active area. Thereby, IT FinFET can
of this paper was arranged by Editor M. M. Cahay. (Corresponding author: secure a larger Wchannel with higher ION than FinFET under
Seongjae Cho.) the same footprint for higher area efficiency. IT FinFET also
E. Yu is with the Graduate School of IT Convergence Engineering,
Gachon University, Seongnam 13120, South Korea. has advantages over SOI FinFET. IT FinFET requires a lower
K. Heo is with the College of Information and Communication Engi- Hfin and wider Wfin than those required by SOI FinFET, which
neering, Sungkyunkwan University, Seoul 16419, South Korea (e-mail: alleviates the difficulty in etching and gate buckling owing
keunheo@skku.edu).
S. Cho is with the Department of Electronics Engineering, Graduate to the mechanically stable structure. In addition, it mitigates
School of IT Convergence Engineering, Gachon University, Seongnam the fin bottom erosion and random dopant fluctuation (RDF),
13120, South Korea (e-mail: felixcho@gachon.ac.kr). which allow small perturbations in the performance between
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. each device. Although IT FinFET has these many advantages,
Digital Object Identifier 10.1109/TED.2018.2846478 only a few previous empirical literatures have been reported

0018-9383 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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3522 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO. 8, AUGUST 2018

Fig. 1. Schematics of p-type IT FinFET. (a) Bird’s eyes view having

a single fin and three fins, respectively. (b) Cross-sectional view on the
xz plane.

and inferior performances including rather high OFF-state cur- Fig. 2. Transfer curves of IT FinFETs having different Wfin with a planar
SOI MOSFET. Hole-current density contours are inserted with respect to
rent (IOFF ) have not been satisfactorily suppressed [15], [16]. Wfin = 40 nm at VGS = 0 and −1.4 V, respectively.
Therefore, in this paper, we perform optimization of the
p-type IT FinFET by controlling various design parame-
ters, and find out the source of performance deterioration technology roadmap for semiconductors (ITRS) and media
observed in the previous experiments, which has been seldom press [22], [24]. In this paper, the driving voltage (VDD ) is
reported yet. Owing to the structural complexity, it is worth set as −0.7 V, following the roadmap target for 2023. The
understanding each geometrical parameter. We carried out a channel and source/drain (S/D) doping concentrations are as
close examination on the dependence of performance on Wfin , low as 1015 cm−3 for n-type and 5 × 1018 cm−3 for p-type
ultrathin body (UTB) height (HUTB), and gate length (L g ) in order to minimize Vth fluctuation caused by RDF, which is
as independent variables. The examination of the dependence one of the major scaling issues [25]. The quantum-mechanical
on Wfin was conducted for the first time. In addition, this models are reflected in the simulations of bandgap narrowing
paper first reports a critical value of HUTB and the scaling and Schrödinger–Poisson model coupled with density-gradient
effects of each parameter over a wide spectrum. Optimal drift–diffusion mode space. The mobilities and saturation
structuring is carried out through 3-D technology computer- velocities for the electrons and holes of Si at room temperature
aided design (TCAD) simulation with calibrated electrical are from empirical data [26]–[29], and these values are fed
parameters, reflecting the quantum-mechanical effects [17]. into the simulation coupled with mobility models, reflecting
the transverse field-dependent mobility effect.
II. D EVICE S TRUCTURE AND S IMULATION A PPROACH
Fig. 1(a) shows the schematics of p-type IT FinFETs with III. R ESULTS AND D ISCUSSION
triple fins and a single fin and their design variables, along In this paper, optimization is carried out for a single fin
with a cross-sectional view with respect to the xz plane in device. To date, most of the literatures related to IT FinFET
Fig. 1(b). The cross section illustrates the “ungated region” deal with HUTB but not with Wfin . This is the first time that
which is vulnerable to SCEs because of the lack of any face a close examination is conducted on the effect of Wfin as an
meeting directly with the gate electrode. The buried oxide independent variable on the performance characteristics. The
(BOX) thickness is considered to be 100 nm, by referring to effects of Wfin are examined by varying Wfin from extremely
a commercial SOI product. Considering a high-κ metal-gate scaled 3 to 40 nm, while HUTB is fixed at 10 nm. Fig. 2 shows
technology, high-κ HfO2 is used as the gate insulator. The the transfer curves of IT FinFETs having different values of
gate work function (WF) is controlled to adjust the threshold Wfin , where L g and drain voltage (VDS ) are 20 nm and −0.7 V,
voltage (Vth ) to 4 and 4.4 eV for simulations on Wfin and respectively. Here, I D is normalized with Wchannel as given in
HUTB, respectively. We have adopted various empirical data the following equation:
and have reflected the recent technology trends to achieve ID
highly reliable results and practicality. For the simulation
( p − Wfin ) + (2 × Hfin + Wfin )
of L g scaling, gate WF is taken as 4.6 eV to obtain the  
μeff Cox 1 2
effective value from HfO2 /TiN or TaN scheme [18]–[21]. = (VGS − Vth ) VDS − VDS . (1)
The thickness of HfO2 is designed to be 3 nm in order to Lg 2
meet the 0.47-nm equivalent oxide thickness (EOT) from the Here, μeff and Cox are the effective channel mobility and
technology roadmap for 2025 [22]. The dielectric constant oxide capacitance per unit area, respectively. The log-scale
(εr ) of HfO2 is obtained from the experimental results having I D shows a significant increase in OFF-state current (IOFF )
similar thickness [23]. Fin pitch ( p) and Hfin are set to be and degrading switch characteristics when Wfin = 20 nm
35 and 25 nm, respectively, by referring to the international and above. IT FinFET has a combined structure of 2-D SOI

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YU et al.: CHARACTERIZATION AND OPTIMIZATION OF IT FinFET 3523

Fig. 3. ION /IOFF ratio and DIBL as a function of Wfin .

planar MOSFET and 3-D FinFET. Hence, it is considered that

a single IT FinFET has two parasitic transistors of p-type
trigate SOI FinFET and p-type planar SOI MOSFET. A small
kink effect is observed with 30- and 40-nm Wfin due to the
relatively large Vth mismatch between two parasitic devices.
In Fig. 2, it can be seen that there are two inserted hole current
density contours for Wfin = 40 nm at gate voltages (VGS ) of 0
and −1.4 V, corresponding to the lower one and the other,
respectively, which confirms the presence of a kink-effect.
The contours also illustrate two different configurations of the
parasitic devices having different values of Vth in a single
p-type IT FinFET. Due to the higher field concentration
through the 3-D channel, a trigate FinFET switches faster
with the first trajectory (bright at the center). Subsequently,
higher | − VGS | is applied further beyond Vth , and the planar
SOI MOSFET turns ON with the second one (along the
channel surfaces). Linear-scale I D –VGS indicates pure I D (not
normalized with Wchannel ) under the same area. The 2-D SOI
MOSFET having 35-nm Wchannel and 10-nm HUTB is also
simulated as a comparison group. The drain currents, I D ’s,
of the IT FinFETs indicate higher saturation current (I D,sat )
than the planar device and lower Vth with increasing Wfin .
ION /IOFF ratio and drain-induced barrier lowering (DIBL) are
Fig. 4. Electrical characteristics for various values of Wfin under off-
shown in Fig. 3 as a function of Wfin . Here, ION and IOFF are state bias condition of VDS = −0.7 V and VGS = 0.6 V. (a) Energy-band
evaluated at VDD = VGS = VDS = −0.7 and VGS = 0 V diagrams in the range from 3 to 40 nm with their gradients. Magnified
and VDS = −0.7 V (standby state), respectively. DIBL is active region for Si island: (b) Potential contours and (c) hole current
densities along the channel direction at Wfin = 10 and 20 nm.
extracted by the constant current method at I D = 10−8 A
under low and high VDS ’s of −0.05 and −0.7 V. Since the
volume out of gate control increases with Wfin , the deteriorated
gate controllability is examined. ION /IOFF has a maxima of where all the simulated devices are under OFF state. Fig. 4(a)
around 107 at Wfin = 10 nm, and above the width, sub- illustrates the energy band diagram from the top end of the
threshold swing (S) degrades along with abrupt increase in Si fin to the bottom end at OFF state. From Fig. 4(a), it can
IOFF . Thereby, not only ION /IOFF ratio but also DIBL degrades be seen that when Wfin ’s from 3 to 10 nm, d V /d x shows a
rapidly due to the emergence of significant SCEs. plateau outside the ungated region, while the ungated region
In order to confirm the presence of high leakage current, has a gradient for all IT FinFETs due to the weakening of
the OFF-state device configurations are examined by means the gate-fringing field and the field fringing in the BOX [30].
of energy-band diagram, potential, and hole current density The former shows a fully depleted (FD) channel while the
contours, as depicted in Fig. 4(a)–(c), in sequence. The bias latter shows a partially depleted (PD) channel despite the
condition in Fig. 4 is (VDS , VGS ) = (−0.6 V, −0.7 V), extremely thin Wfin of 3 nm. Energy-band diagram for the

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3524 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO. 8, AUGUST 2018

Fig. 6. DC characteristics of SOI FinFETs and IT FinFETs having the

same dimensions as functions of HUTB . (a) gm,Max and S. (b) DIBL.

Fig. 5. ID –VGS curves for IT FinFETs for different values of HUTB (from
ultrathin 1 to 10 nm) and for an SOI FinFET with the same dimensions 36.1%, 55.6%, 92%, and 142% at VGS = −1.4 V, compared
as that of the IT FinFETs.
with SOI FinFET. As shown in Fig. 2, the amount of Vth shifts
when Wfin and HUTB are varied from 3 to 10 nm is 0.069 and
0.259 V, respectively. Here, Vth is defined by using the constant
ungated region, PD channel, has been formed in the way current method where I D is 10−8 A. The values of I D,sat with
of accumulating holes. An FD channel is even broken when different values of HUTB have a wider range compared with
Wfin is above 20 nm, and the area becomes the primary those for different values of Wfin . Thus, in order to obtain the
source of SCEs as depicted in the inset of Fig. 4(a). Fig. 4(b) intended device performance, precise HUTB controlling is very
and (c) depict the isopotential lines and hole current density important during fabrication. In the fabrication process for IT
along the channel direction − →
y with respect to Wfin of 10 FinFET, delicate etch control of HUTB is required owing to
and 20 nm, respectively. In Fig. 4(b) and (c), the active the large range of performance fluctuation as shown in Fig. 5
part of the Si island is magnified. In the ungated region, a and Hfin is defined by the total amount of etch as (initial
large hole-current path is formed when Wfin = 20 nm. This SOI height)—HUTB. In particular, HUTB thinner than 2 nm
is caused by the encroaching S/D potential on the channel, is undesirable to ensure high-performance (HP) characteristics
known as punchthrough [31]. Thereby, even under the OFF- from IT FinFET. In addition, the Vth values between 2-D and
state condition, a large hole current flows when Wfin = 20 nm. 3-D channels in an IT FinFET should be minimized since a
To mitigate the large leakage current, higher channel and S/D large Vth mismatch induces degradation in ION /IOFF ratio and
doping concentrations can be a solution. In the light of device switching characteristic. Since IT FinFET is expected to have
structuring, the minimization of the ungated region should be narrow fin pitch and loading effect can be raised, dry etch
paramounted, so that the SCEs can be effectively suppressed. conditions need to be precisely set up in defining HTUB as
In order for less performance degradation, Wfin below 10 nm designed. Also, additional masks are required to isolate the
and higher channel doping can be a solution for decelerating unit cell in fabricating single-channel IT FinFET and multiple-
the reduction in depletion region width. channel one.
Considering the optimum range of Wfin around 5 nm Figs. 6(a) and (b) shows the dc characteristics and SCEs
suggested by the technology node for 2025 [22], HUTB is of IT FinFETs as functions of HUTB. The maximum available
controlled from 10 down to 1 nm, with a fixed Wfin of transconductance (gm,Max ), subthreshold swing (S), and DIBL
5 nm. Fig. 5 shows the transfer curves at VDS = −0.7 V increases with increase in HUTB. As shown in Fig. 6(a),
with different HUTB IT FinFETs and an SOI FinFET having FinFET has higher gm,Max and S than those of 1- and 2-nm IT
5-nm Wfin and 27-nm Hfin (coextensive IT FinFETs). As HUTB FinFETs, and the higher gate controllability causes a decent
becomes thinner, the switching characteristics become sharp S values near subthermal S. Regardless of the aforementioned
and Vth shifts to the left side resulting in an increase in Vth . physical properties, linearly increasing gm,Max with HUTB
Both ION and IOFF become high because of increased chan- can also be confirmed mathematically using the following
nel volume and widening of the gate-uncontrollable region, equation, which is the first derivative I D equation of planar
respectively. IT FinFET has higher ION than coextensive SOI MOSFET
FinFET with the same dimensions, which is a significant 
∂i d 
advantage; however, a critical HUTB less than 3 nm neutralizes gm =
the advantage of IT FinFET, which has a lower drive current ∂v gs VGS
compared with that of SOI FinFET. For HUTB of 3, 4, 5, 7, ( p − Wfin )+(2 × Hfin +Wfin )
= μeff Cox (VGS −Vth ). (2)
and 10 nm, I D,sat ’s of IT FinFETs are enhanced by 13.3%, Lg

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YU et al.: CHARACTERIZATION AND OPTIMIZATION OF IT FinFET 3525

Fig. 7. Potential along the x-direction of the UTB underneath the gate Fig. 8. Transfer curves at VDS = −0.7 V with different values of Lg for
center with isosurface of hole current density at 1.38 × 106 A/cm2 under IT FinFETs and coextensive SOI FinFETs.
fully turned-on-state condition of VDS = −0.7 V and VGS = −1.4 V.

Here, i d and v gs are the small-signal current and voltage added

on the dc quantities of I D and VGS for high-frequency ac
operation. Note that the transconductance (gm ) has a positive
relationship with Wchannel . Higher values of HUTB provide a
larger number of carriers, thus enabling gm to become high.
Therefore, gm,Max follows a linear positive tendency with
HUTB; however, it shows a small discrepancy around 2 nm
because of the strong quantum-mechanical effects. Fig. 6(b)
shows that DIBL is smaller than that of SOI FinFET, when
HUTB is less than 3 nm. In order to analyze the lower ION
characteristics for the ultrathin HUTB of IT FinFET, compared Fig. 9. Scaling effects on S, Vth roll-off, and gm,Max in IT FinFETs.
with SOI FinFET, the potentials with isosurface hole current
densities of 1.38×106 A/cm2 are observed under fully turned-
ON state (VDS = −0.7 V and VGS = −1.4 V) as graphically teristics and current drivability, taking into account the ITRS
described in Fig. 7. Generally, the peak of wave function in requirements. Fig. 8 shows the dependence of L g on the I D –
the inversion layer is around 20 Å away from the oxide– VGS curves. Here, SOI FinFETs with L g of 20 and 5 nm are
semiconductor interface [31]–[33]. Thus, the large potential used to compare the performances between IT FinFETs and
window between 2 and 3 nm causes higher electric field SOI FinFETs. IT FinFETs demonstrate a higher current drive
with a thinner body, which results in the increase in energy with the same dimensions because HUTB is designed to be
level quantization and available energy states. While HUTB of thicker than 2 nm. Thereby, we can achieve higher ION for
less than 2 nm is required for effectively suppressing SCEs, any IT FinFET with the same footprint. IOFF increases with
a low current drivability is somehow inevitable. However, the L g scaling due to the degradation in the power of the gate
previously fabricated IT FinFETs had thick Wfin of around through the channel. In Fig. 9, the dc characteristics of IT
63 nm and 2 μm, when HUTB was 15 nm and around FinFETs in terms of S, Vth roll-off, and gm,Max are shown with
15 nm, respectively. The inferior performances were caused a 5-nm SOI FinFET. The devices show decent short-channel
by improperly designed geometric parameters, and an inap- characteristics: S around 60 mV/dec and Vth roll-off below
propriate bias condition and extremely high leakage current 100 mV, except for the 5-nm IT FinFET. While IT FinFET has
were obtained [15], [16]. It is seen that only an optimally higher ION than SOI FinFET, it has a lower immunity against
designed IT FinFET can achieve a higher drive current than SCEs. IT FinFET is suitable for applications requiring high
SOI FinFET. From the results, it is seen that HUTB above current; however, SCEs become exacerbated compared with
the critical thickness of 3 nm (ITRS HP target for 2025) is SOI FinFET. To obtain larger current, the design parameters of
reasonable for ensuring higher current drive; however, severe the device can be changed so that it has thicker Wfin and HUTB
SCEs will be inevitable. under the permissible range provided in this paper. In addition,
Examination of the scaling leverage of IT FinFET is carried a multifinger scheme can be used to obtain much larger current
out from 20 down to 5 nm. Wfin and HUTB are determined to along with a reduction in gate resistance. Fig. 10(a) defines
be 5 and 3 nm, respectively, for both short-channel charac- the rising delay time (trd ) and falling delay time (tfd ) of an

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3526 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO. 8, AUGUST 2018

function of IT FinFET L g . At L g = 20 nm, trd = 0.656 ps, and

tfd = 0.262 ps, which are smaller than those of SOI FinFET,
trf = 0.703 ps and tfd = 0.301 ps. Both trd and tfd show a
monotonic decrease as L g gets shorter. It is confirmed from
the results in Figs. 10 and 11 that IT FinFET would have
the superior performances in digital applications along with
the strong potential toward the high-frequency analog circuits
requiring transistor with high transconductance.

IV. C ONCLUSION
In this paper, we investigated the performance issues in
IT FinFETs which can result from geometrical conditions in
the previous studies and provide the concrete design criteria
with a wider range of design parameters, which has been sel-
dom reported. Furthermore, based on the optimally designed
structure, the scalability of IT FinFET was vigorously studied
down to 5 nm toward the upcoming technology nodes. The
performance optimization of IT FinFET was carried out with
respect to Wfin and HUTB. We figured out the problem of
inferior dc characteristics on fabricated IT FinFETs having
much larger Wfin (exceeding 10 nm). There seems to be a
punchthrough event. Wfin should be lower than 10 nm for
higher immunity against SCEs. Above the critical thickness
of HUTB = 3 nm, the morphological advantages of a higher
layout efficiency with higher I D than those of FinFET are
ensured. IT FinFETs with HUTB of 3 and 10 nm achieve 13.3%
and 142% enhancement with respect to I D,sat compared with
coextensive SOI FinFETs. Although there can be inevitable
Fig. 10. Transient simulation for evaluating the intrinsic gate delay. SCEs owing to its structurally inherent configuration, it is
(a) Definition of rising delay time (trd ) and falling delay time (tfd ). confirmed that optimally designed IT FinFET is superior to
(b) Timing diagrams for the input versus output signal delays of 20-nm
IT and SOI FinFETs. SOI FinFET in both analog and digital applications, with high
current drivability and short gate delays.

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channel transistor for area efficient high performance operation,” Appl. Korea, in 1994. She received the B.S. degree in
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[17] ATLAS User’s Manual, Silvaco Int., Santa Clara, CA, USA, 2016. Seongnam, South Korea, in 2017, where she is
[18] A. Kuriyama et al., “Work function investigation in advanced metal currently pursuing the M.S. degree.
gate-HfO2 -SiO2 systems with bevel structures,” in Proc. Eur. Solid-State Her current research interests include
nanophysics, nanoscale CMOS devices, and
Device Res. Conf., Montreux, Switzerland, Sep. 2006, pp. 109–112.
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of incorporated Al on the TiN/HfO2 interface effective work function,” interest in SiGe.
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functions using low-temperature anneals and selective cladding to Keun Heo received the Ph.D. degree in elec-
control interface composition,” Appl. Phys. Lett., vol. 100, no. 15, tronics engineering from Korea University, Seoul,
pp. 153501-1–153501-3, Mar. 2012. South Korea, in 2014.
[22] (2013). International Technology Roadmap for Semiconductors (ITRS). His current research interests include model-
[Online]. Available: http://www.itrs2.net ing, simulation, and system-level application of
[23] Y.-S. Kang et al., “Structural and electrical properties of EOT HfO2 the synaptic devices based on low-dimensional
(<1 nm) Grown on InAs by atomic layer deposition and its thermal quantum nanomaterials.
stability,” ACS Appl. Mater. Interfaces, vol. 8, no. 11, pp. 7489–7498,
Mar. 2016.
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CA, USA. [Online]. Available: https://newsroom.intel.com/newsroom/
wp-content/uploads/sites/11/2017/03/Kaizad-Mistry-2017-
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fluctuations in sub-0.1 μm MOSFET’s: A 3-D ‘atomistic’ simulation
study,” IEEE Trans. Electron Devices, vol. 45, no. 12, pp. 2505–2513,
Dec. 1998. Seongjae Cho (S’07–M’10) received the B.S.
[26] R. Quay, C. Moglestue, V. Palankovski, and S. Selberherr, “A tem- and Ph.D. degrees in electrical engineering from
perature dependent model for the saturation velocity in semiconductor Seoul National University, Seoul, South Korea,
materials,” Mater. Sci. Semicond. Process., vol. 3, nos. 1–2, pp. 149–155, in 2004 and 2010, respectively.
Mar. 2000. He has been an Assistant Professor with the
[27] M. V. Fischetti and S. E. Laux, “Band structure, deformation potentials, Department of Electronics Engineering, Gachon
and carrier mobility in strained Si, Ge, and SiGe alloys,” J. Appl. Phys., University, Seongnam, South Korea, since 2013.
vol. 80, no. 4, pp. 2234–2252, 1996. His current research interests include advanced
[28] R. Braunstein, A. R. Moore, and F. Herman, “Intrinsic optical absorption CMOS devices, emerging memory devices, and
in germanium-silicon alloys,” Phys. Rev., vol. 109, no. 3, pp. 695–710, intelligent integrated systems.
Feb. 1958.

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