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LIC R19 - End Sem (Jun 2024)

The document outlines the examination details for the B.E. (Full Time) program in Electronics and Communication Engineering at Anna University for the April/May 2024 semester. It includes course objectives, a breakdown of questions for the exam, and various topics related to linear integrated circuits and operational amplifiers. The exam is structured into three parts, with specific marks allocated to each section and questions designed to assess different levels of understanding and application.

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vignesh r
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0% found this document useful (0 votes)
13 views3 pages

LIC R19 - End Sem (Jun 2024)

The document outlines the examination details for the B.E. (Full Time) program in Electronics and Communication Engineering at Anna University for the April/May 2024 semester. It includes course objectives, a breakdown of questions for the exam, and various topics related to linear integrated circuits and operational amplifiers. The exam is structured into three parts, with specific marks allocated to each section and questions designed to assess different levels of understanding and application.

Uploaded by

vignesh r
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 3

ONAL CONT

600
CHENNAMA
AM
LER Roll No. 2 o22|
025 OF
DEPARTMENTS)
ANNA UNIVERSITY(UNIVERSITY
SWOILVNIN
APRIL / MAY 2024
-END SEMESTER EXAMINATIONS,
B.E. (FullTime)
AND COMMUNICATION ENGINEERING
DEPARTMENT OF ELECTRONICSIV-Semester
CIRCUITS
EC5405 - LINEAR INTEGRATED
(Regulation 2019)
Max.Marks: 100
Time: 3hrs
amplifier in
and role of the operational
significance
CO comprehend and appreciate the
1
Ability to
world
the present contemporary operational amplifier.
circuit using
CO 2 Ability to design new analog linear using linear lCs.
communication systems
CO 3 Ability to analyzer and develop
in real time scenario.
CO 4 Ability to deploy the data converters system design
ICs and circuits for analog
appropriate
CO 5 Ability to select

BL -Bloom's Taxonomy Levels


-Understanding,L3 - Applying,
L4 - Analysing, L5 -Evaluating, L6 - Creating)

(L1- Remembering, L2

PART- A(10 x 2=
20 Marks)
(Answer all Questions)

Marks CO BL
Questions
Q. No 2 1 1

Define utput Offset voltage.

2 1 3
generating a constant current of
circuit for
Design the Widlar
Use V=25mV,
l6=10uA. Assume Vcc=10V, VBE=0.7V,B=125.
= 1ma 2 2 3
Iref
ta step input voltage of
|Drawthe output of an op-amp integrator, if

HV is fed as input for 0 0.3 ms with C


sts 10nF and = R =20K 2

= 72 mV.
VH 2 2 3
circuit with
Design an inverting Schmitt trigger
voltage = +13V.
Assume, supply voltage =+15V, saturation

2 3 1

diagram of an AM detector using PLL.


Draw the block

Coefficient of 2 3 2
6 f=100 KHz, the
If
voltage to frequency transfer

VCO frequency 5 MHZ and N=100 in


VCO, K, =2 MHz/V, fo the is

What is the dc control Voltage at lock?


the frequency Multiplier.

CMOS Inverter Switch used in DAC 2 4 1

Draw the

of a 14 bit ADC ifthe full Scale output is 10V.


4 2
Find the resolution
to Vec in a 555timer? 2 5 1
Why pin 4 is connected

2 5
the switching regulator.
|List the advantages of
PART- B (5 x 13 = 65 Marks)

Marks CO BL
Q. No Questions
3
8 1

Describe the freguency compensation techniques


in an Op-Amp
11 (a)(0)
in detail.
5 1 3
amplifier with a gain of 50.
(0)A741C Op-Amp is used an inverting

741Cis upto 20KHz.


The voltage gain vs frequency curve of flat

can be applied without


What maximum peak to peak input signal

distorting the output.

OR
1 3
Describe the Input Bias current with relevant diagrams and how

to reduce the offset voltage due to Input Bias Current.

neat diagram.
5 2
OExplain the Active Load with

neat 8 2 2
12 (a)(i) Derive the output voltage of Full Wave rectifier circuit with

Circuit diagram

differentiate an input 5 2 3
that
(ii) Design an op-amp differentiator will

signal with fmex 100Hz assume C,=0.1 pF

OR
8 2 2
Derive the output of a three Op-Amp instrumentation amplifier

with neat circuit diagram

with the cut-off 5 2 3


At Design a second order Butterworth Low-Pass filter

frequency of 2KHz.Assume, C=0.1uF

and derive its output.


8 3 1

13 (a) (i) Draw the Four Quadrant Multiplier circuit 5 3 3


the Free running Frequency, Lock in range and Capture
(ü) Obtain
range for the circuit shown below.
R
268 ks2

O9TTON4)
10 8 0.01
ufF
7 Deimnodulated output oU0
o
AT
Reference output 025
6
oput NE 565
GHENNAI
o VCO output ()
KROLLER
YNIWY
o 001 HF

OR
IC 566 Voltage Controlled Oscillator 8 3 1
Draw the block Diagram of

and explain its operation.

the NE/SE 565 and explain 5 3 1

Drawthe functional block diagram of


ti)
its operation.
R-2R Ladder circuit with the 8 4
Obtain the output voltage of 4-bit

word of dadadzd=1100 (d.LSB).


input
5 4 1
)Briefly explain the Sample and Hold Circuit.
OR

neat block diagram and derive


8 1
14 (b) (i) Describe the Dual slope ADC with

its output.

5 4 3
(i) Design the 2-bit Flash type ADC with necessary diagrams.

capacitor 7 5
With neat diagrams, explain the operation of Switched
filter.

6 5
Explain the Tuned amplifier with neat diagrarn

OR
IC 723 and obtain Its
7 5 3
15 (b)() Construct theHigh Voltage regulator using

Output.

in detail.
6 5
(ü) Describe the functions of Isolation Amplifier

PART- C (1 x 15= 15 Marks)


(Q.No.16 is compulsory)

Marks CO BL
Q. No Questions
5 6
t0 Design a DC Lamp
of the
Dimmer circuit using

Lamp. Assume relevant


555 to control

components.
the
Draw the
12

brightness
circuit diagram and explain the working in detail.

3 2 3
Design a Square wave generator using Op-amp with
the
C=0.01 uF.
frequency of oscillations is 2 KHz. Assume,

1ONALCONTR

500
02
CHENNA
025

KOUYNINS

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