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0% found this document useful (0 votes)
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2017 Mid Hyd

fssdfdsfsdfsdfdsf

Uploaded by

Parth Sharma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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BITS Pilani, Hyderabad Campus

Department of Electrical and Electronics Engineering

First Semester 2017-2018


Course : IC Fabrication Technology Course number : MEL-G611
Examination : Mid Term Test (Closed Book) Maximum marks : 60
Date : Thu 12th Oct 2017 Duration : 09:00 AM - 10:30 AM
Name : ID No :

Problem 1: Simple Process Flow (15 points total)


(a) Find the packing density of diamond lattice. [3 pts]
(b) What would be the angle and depth, if one etched a <100> wafer in (111) plane? [2 pts]
(c) Why <100> wafer is preferred over <111> wafer in CMOS process technology? [2 pts]
(d) Let us consider a CMOS process starts with a p-type Si wafer: (i) List all thermal oxidation steps and their
purpose briefly in this process sequence; (ii) List all ion-implantation steps and their purpose briefly in this process
sequence. [6 pts (3+3)]
(e) In twin-well CMOS process, in order to form an N-Well, why phosphorous is preferred over arsenic or anti-
mony?[2 pts]

Problem 2: Dopant diffusion (15 points total)


Boron predeposition step is performed into an n-type Si substrate at 1000◦ C. Boron solid solubility at 1000◦ C is
known to be 3.5×1020 cm−3 and the incorporated boron dose Q is 3×1015 cm−2 .
(a) What is the Dt product of the predeposition process? [5 pts]
(b) What is the junction depth xj of the predeposition profile if the n-type substrate has a background concentra-
tion of 1015 cm−3 . [5 pts]
(c) Suppose we perform a solid solubility limited predeposition for a total of 15 minutes from a doped glass source
which introduces a total of Q impurities/cm2 . How long would it take (total time) to predeposit a total of 4Q
impurities/cm2 into a wafer if the predeposition temperature remained constant? [5 pts]
NB: If necessary, one may assumed erfc−1 (2.9 × 10−6 ) = 3.3;

Problem 3: Ion Implantation (15 points total)


1000 keV boron was implanted into n-type Silicon substrate at background doping concentration NB = 1015 cm−3 .
This results in a projected range of 1.756 µm and a normal straggle of 0.1364 µm.
(a) Calculate the dose (Q) required to achieve a peak Boron concentration of 3 × 1019 cm−3 ? [3 pts]
(b) What are the junction depths? [5 pts]
(c) Calculate the profile width WP ? [2 pts]
(d) What is the sheet resistance of the implanted layer? [2 pts]
(e) In order to have an ultra-shallow junctions, briefly discuss two methods those are used in IC processing tech-
nology to minimize the ion channeling effect. [3 pts]
Given: p-layer mobility is ∼ 40 cm2 /V-s and approximate formula for sheet resistance is RS = qµQ
1

Problem 4: Thermal Oxidation (15 points total)


(a) For a particular oxidation process, it is known that the oxidation rate (dxox /dt) is 0.24µm /hour when the
oxide thickness is 0.5 µm and it becomes 0.133 µ/hour when the oxide thickness is 1 µm. Find the linear oxidation
constant (B/A) and the parabolic oxidation constant B. Give answers in proper units. [10 pts]
(b) List four basic type of charges present in the oxide and at the semiconductor-oxide interface. Discuss briefly,
how these charges incorporated inadvertently during subsequent process steps? How does one minimizes these
charges or defects? [(1+2+2=)5 pts]

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