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org © 2018 IJCRT | Volume 6, Issue 2 April 2018 | ISSN: 2320-2882

DESIGN OF LOW POWER ALU USING GDI

TECHNIQUE
N.Srinu, M.Kedhar, O.Ajay

Abstract— the purpose of this paper is to design low to CPU. So it’s a brain of computer’s brain. They consists
power and area efficient ALU using GDI technique. of fast dynamic logic circuits and have carefully
Main sub modules of ALU are adder, logical unit, optimized structures. Of total power consumption in any
Subtractor, multiplexer, divider. This work evaluates processor, CPU accounts a significant portion of it.
and compares the performance & optimized area of Therefore, this motivate us strongly for an energy-
ALU with conventional CMOS style &GDI technique the efficient ALU designs that satisfy the high-performance
simulations are performed by using Micro wind tool. At requirements, while reducing power dissipation. ALU is a
first by using Micro Wind tool the circuits are designed combinational circuit that performs arithmetic and
&simulated with CMOS technique and then with GDI logical operations .Arithmetic operations are basic
technique. By comparing two designs GDI&CMOS style functions and necessary for any low power, high speed
then GDI is an advantage of less power and less area. application digital signal processing, image processing,
and microprocessor. The internal structure of an ALU is
Index Terms—Adder, ALU, Comparator, GDI, Logical
shown in Fig.1.
unit, Low power, one’s complement, multiplexer,
divider. Fig. 1: Internal structure of ALU

1. INTRODUCTION

Recently, the industries are in demand for low power,

less area and high speed for designing the circuits. With
improvement in technology and the enlargement of
embedded system used electronic devices such as
mobile, laptops, TV applications, power consumption,
which is one of the limits in both high & low performance
system, has become a primary focus in VLSI digital
design.

In this paper the adder was based on regular CMOS Logic Unit:
structure .Disadvantage of this paper uses a number of
ALU can perform various logic operations like NOT, AND,
transistors results in high input loads, more power
OR, NAND, NOR, XOR, XNOR etc. For these operations a
consumption and larger silicon area. Morgenshtein has
special unit is made called as Logical Unit. This Logic Unit
proposed basic GDI cell .By using this GDI cell we design
performs all logic operations asked to perform. A MUX
ALU. In digital system design processor is main part of
operated by select lines, for which particular logic
the system. And an ALU is one of the main components
operation to perform, is used inside this logic block.
of a micro-processor. CPU works as a brain to any system
& and ALU works as a brain Low Power ALU using 4:1 MUX

There is a substantial increase in the standby mode

leakage power, where technology is used here is 90nm.
Reducing the power consumption of the ALU is
important not only because they consume a

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considerable percentage of processor energy, but also adder and significantly improved threshold problem to
because they are one of the most active and busiest 50%. Gate Diffusion Input Technique is a new method of
component of the processor. As a result of they dissipate reducing power dissipation, propagation delay with less
a lot of dynamic energy. This is aggravated by the area. We have designed ALU in different way by using
exponential dependence of leakage on the temperature, GDI cells to implement multiplexers and full adder
& ALU also become a site of high leakage. The total circuit. The input and output sections consist of 4x1 and
leakage of the ALU can be given as IS, T=N.IS, i Where, 2x1 multiplexers and ALU is implemented by using full
N= number of transistors in the ALU IS, i= sub threshold adder.Ex: T. Esther Rani, M. Asha Rani, Dr. Ramesh war
leakage of gate i which is a function of gate length L. Rao, designed an area optimized low power arithmetic
Similarly, the dynamic power of the ALU is given as and logic unit in which Arithmetic Logic Unit is
ID=α.Ceff.Vdd2.f where α is the switching factor, Ceff. Is implemented using logic gates, pass transistor logic, as
the total effective capacitance, Vdd is the supply voltage well as GDI technique.
& f is the frequency of operation.
EXISTING SYSTEM STRUCTURE
RELATED WORKS
An arithmetic logic unit (ALU) is a fundamental building
• There are different types and designs of full adder block of the Central Processing Unit (CPU) of a computer,
which is discussed in various papers at state of the art and even the simplest microprocessors contain one. It
level and process and circuit level. Twelve state of the art is responsible for performing arithmetic and logic
full adder cells are: conventional CMOS, CPL, TFA, TG operations such as addition, subtraction, increment,
CMOS, C2MOS, Hybrid, Bridge, FA24T, N-Cell, DPL and decrement, logical AND, logical OR, logical XOR and
Mod2f. logical XNOR.ALU consists of eight 4x1 multiplexers, four
• R. Shalem, E. John, and L.K. John, proposed a 2x1 multiplexers and four full adders. The 4-bit ALU is
conventional CMOS full adder consisting of 28 designed in 250nm, n-well CMOS technology. When logic
transistors. Later, the number of transistor count is ‘1’and logic ‘0’ are applied as an input INCREMENT and
reduced to have less area and power consumption. DECREMENT operations takes place respectively. An
• A. Sharma, R Singh and R. Mehra, Member, IEEE, have INCREMENT operation is analyzed as adding ‘1’ to the
improved performance with Transmission Gate Full addend and DECREMENT is seen as a subtraction
adder using CMOS Nano technology where 24 transistors operation.
are used.
• The Complementary Pass-transistor Logic (CPL) full
Adder contains the 18 transistors. The power
consumption of this structure is 2.5μw.
• A Transmission Function Full Adder (TFA) based on the
transmission function theory has 16 transistors. The
power consumption of this structure is 12μw.
• N-CELL contains the 14 transistors and utilizes the low
power XOR/XNOR circuit. The power consumption of this
structure is 1.62μw.
• Mod2f Full Adder contains the 14 transistors,
generates full swing XOR and XNOR signals by utilizing a
pass transistor based DCVS circuit. The power
consumption of this structure is 2.23μw. • Saradindu
Fig 2: 4-bit Arithmetic and Logic Unit
Panda, N. Mohan Kumar, C.K. Sarkar, optimized the full
adder circuit to 18 Transistor using Dual Threshold Node Two’s complement method is used for SUBTRACTION in
Design with Submicron Channel Length. which complement of B is used. The outputs obtained
• T. Vigneswaran, B. Mukundhan, and P. Subbarami from the full adder are SUM, EXOR, EXNOR, AND & OR.
Reddy, designed 14 transistor high speed CMOS full

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Fig:2 shows the block diagram of 4-bit ALU where the

first stage to fourth stage is cascaded with the CARRY
bit. Symbolic representation of 4-bit ALU has been
visualized in it. The multiplexer stage selects the
appropriate inputs based on the condition of the select
signals, and gives it to the full adder which then
computes the results. The multiplexer at the output
stage selects the appropriate output and route it to
output port. The operation being performed and the
inputs and outputs being selected are determined by set
of three select signals incorporated in the design. Shows
multiplexer logic at input port. Shows multiplexer logic
at output port. The multiplexer stage selects the
appropriate inputs based on the condition of the select Where we are using 8: 1 mux here.for ever select line we
signals, and gives it to the full adder which then are having different functions like and, or, nand, nor, not,
computes the results. The multiplexer at the output xor, xnor, adder & subtractor. Where the each logical
stage selects the appropriate output and route it to unit is designed by using GDI technique by using the
output port. T shows the truth table for the operations gates we are design it.
performed by the ALU based on the status of the select
RESULT:
signal.

Transistor that can be modified along with the design. Fig

2 represents the complete schematic view of ALU. The
4-bit ALU consists of two 4-bit inputs, three selecting
lines, and one carry input, one carry output and four
output bits. This paper presents a new approach using
concept of Gate Diffusion Input Technique to design an
arithmetic and logic unit. In an ALU, for appropriate
selection of input to perform particular operation and for
obtaining output accordingly multiplexer is the most
applicable device. In earlier designs of ALU, the
multiplexer unit is either implemented by conventional
CMOS logic or by pass transistor logic which proven to
FIG: AND output
have high power consumption. The approach gives
better result than previous designs in terms of power
consumption, propagation delay as well as area.

PROPOSED WORK:

FIG: XOR output

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FIG: FINAL OUTPUT OF ALU

NO OF TRANSISTORS ARE USED IN ALU

CMOS GDI
FIG :OR gate output
AND GATE 4 2
OR GATE 4 2
NAND 4 4
GATE
NOR GATE 4 4
XOR GATE 8 4
XNOR GATE 8 4
NOT GATE 2 2
ADDER 10 6

CONCLUSION

Power consumption in CMOS circuit is classified in two

categorize: static power dissipation and dynamic power
FIG: Full adder output
dissipation. In today’s CMOS circuits static power
dissipation is negligible thus not considered as compared
to dynamic power dissipation. Dynamic Power
dissipation in a CMOS circuit is given by P = CLf VDD2.
The power supply is directly related to dynamic power.
The numbers of power supply to ground connections are
reduced in GDI implementation which reduces the
dynamic power consumption. This work presents a 4-bit
ALU designed in 250nm technology for low power and
minimum area with GDI technique. Various topologies of
multiplexer and full adder implementation is studied and
compared. The 2x1 multiplexer, 4x1 multiplexer, 1-bit
FIG: Full subtractor output full adder with 10- transistors designed using GDI
technique is chosen for lowering power consumption
and minimum possible area. Power dissipation,
propagation delay and the number of transistors of
ALU were compared using CMOS, nMOS PTL and GDI
techniques. GDI technique proved to have best result in
terms of performance characteristics among all the
design techniques.

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 www.ijcrt.org © 2018 IJCRT | Volume 6, Issue 2 April 2018 | ISSN: 2320-2882

REFERENCES:

1) Serial Divider Using Modified GDI Technique

A.S. Prabhu1, B. Naveena2, K. Parimaladevi3, M.

Samundeswari4, P.Thilagavathy5 Assistant Professor,
Electronics and Communication Engineering, EBET
Group of Institutions, Tirupur, India 1 UG Scholar,
Electronics and Communication Engineering, EBET
Group of Institutions, Tirupur, India 2,3,4,5

2) LOW POWER AND LOW AREA ALU DESIGN USING GDI

TECHNIQUE

Gandhi.Harikrishna1, M.Mohan Reddy2 1M.Tech

student, ECE, Santhiram college of Engineering
Nandyal,Kurnool,Andhra Pradesh, India 2Assistant
Professor, ECE ,Santhiram college of Engineering
Nandyal,Kurnool,Andhra Pradesh, India

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