Part II

Low Voltage Technologies

and Circuits
Low-Voltage Technologies
and Circuits (Invited)
TADAHIRO KURODA, MEMBER, IEEE, AND TAKAYASUSAKURAI,* MEMBER, IEEE
SYSTEM ULSI ENGINEERING LABORATORY, TOSHIBA CORPORATION
(*) INSTITUTE OF INDUSTRIAL SCIENCE, UNIVERSITY OF TOKYO
Abstract-This paper reviews low-voltage device technologies and
circuit design techniques for low-power,high- speed CMOS VLSls.
Some of the recent developments, such as employing multiple
threshold voltage and controlling threshold voltage through sub-
strate bias in bulk CMOS and Silicon on Insulator (SOl) based
technologies, are discussed. Future directions of low-power VLSls
are also described.
1. INTRODUCTION
Lowering both of the supply voltage V
DD
and threshold voltage
V
th
enables high-speed, low-power operation [1-3]. Figure 1 de-
picts equi-speed (broken lines) and equi-power (solid lines)
curves on a VDD-V
th
plane [4] calculated from their theoretical
models [5]. The contour lines are normalized at a typical design
window (box in the figure) where V
DD
= 3.3V 10% and
V
th
= 0.55V O.IV.CircuitspeedbecomessloweratlowerV
DD
and higher V
th
while power dissipation becomes larger at higher
VDD and lower V
th
Tradeoffs between speed and power can be
explored by sliding the design windowon the VDD-V
th
plane. The
upper-left comer shows the worst case speed condition, whereas
the lower-right comer shows the worst case power scenario. Re-
sults are summarized in Fig. 2 [4]. It suggests that optimum V
DD
and V
th
can save the waste (shadows in the figure) caused by the
constant V
DD
of 3.3V and constant V
th
of 0.55V.
This approach, however, raises three problems, and therefore
has not been achieved: 1) degradation of worst-case speed due to
V
th
fluctuation in low V
DD
[6,7], 2) increase in standby power dis-
sipation in low V
th
[8-10], and 3) inability to sort out defective
chips by monitoring the quiescent power supply current (IDDQ)
[11]. Delay variation due to V
th
fluctuation is increased in low-
voltage operation [6,7]. It can be understood in Fig. 1that the de-
sign window should be reduced in size to keep the delay variation
percentage constant in low VDD' Its theoretical mode is derived in
Kuroda and coworkers [12]. For example, under 50% speed re-
quirement VDD can be reduced to 1Vand V
th
fluctuation should be
reduced from 0.1V to 0.02V. The second and the third prob-
lems come from the increased subthreshold leakage current in
low V
th
A dotted line in Fig. 1 depicts a equi-power-ratio curve
61
where power dissipation due to the subthreshold leakage current
makes up 10%of the total power dissipation. The design window
should be set at high V
th
regions in a standby mode and testing.
To solve these problems, several circuit schemes are pro-
posed: a multi threshold-voltage CMOS (MTCMOS) scheme
[8], a variable threshold-voltage CMOS (VTCMOS) scheme
[12], and an elastic-Vt CMOS (EVTCMOS) scheme [13]. The
three circuit schemes are discussed and several circuit imple-
mentations are presented in Section 2. Device technologies in-
cluding bulk CMOS and SOl are then reviewed in Section 3.
Section 4 is dedicated to discussions on possible future direc-
tions and conclusions.
2. LOW-VOLTAGE CIRCUITS
A. Low- Voltage Circuit Schemes
The three circuit schemes which have been proposed to solve
the 10w-VDJlow-V
th
problems are sketched and compared in
Fig. 3. Currently in a system such as a PC, the power supply is
turned off by a power management controller when a chip is in-
active, but this idea can even be applied at the chip level. The
MTCMOS [8] employs two types of V
th
: low V
th
for fast circuit
operation in logic circuits and high V
th
for cutting off the sub-
threshold leakage current in the standby mode. Since parasitic
capacitance is much smaller on a chip than on a board, the on-
off control of the power supply can be performed much faster
on a chip. This takes less than 0.5,us, which in tum enables fre-
quent power management [14]. This scheme is straightforward
and easy to be employed in a current design method. However,
it requires very large transistors for the power supply control,
and hence imposes area and yield penalties; otherwise circuit
speed degrades. These penalties become extreme below 0.9V
V
DD
because (VGS-V
th
) of the high-V
th
transistors becomes too
small in the active mode. One potential problem is that the
MTCMOS cannot store data in the standby mode. Special
latches have been developed to solve this problem [14].
While the MTCMOS can solve only the standby leakage
problem, the VTCMOS [12] can solve all three problems. It
0.8
0.7
0.6
0.5
.--
>
-
0.4

0.3
0.2
0.1
0
0.5 1.5 2 2.5 3 3.5 4
V
oo
(V)
Figure 1 Exploring V
oo
-V
th
design space.
dynamically varies V
th
through substrate bias, V
BB
Typically, V
BB
is controlled to compensate for V
rh
fluctuations in the active
mode, while in the standby mode and in the I DDQ testing, deep
V
BB
is applied to increase V
th
and cut off the subthreshold leak-
age current.
The EVTCMOS [13] controls both V
DD
and V
BB
such that
when V
DD
is lowered, V
BB
becomes that much deeper to raise V
th
and further reduce power dissipation. Note that internal V
DD
and
V
ss
are provided by source-follower n- and p-transistors, re-
spectively, whose gate voltages are controlled. In order to con-
trol the internal power supply voltage independent from the
power current, the source-follower transistors should operate
near the threshold. This requires very large transistors.
The essential difference among the three schemes is that the
VTCMOS controls the substrate-bias while the others control
the power lines. Since much smaller current (almost none) flows
in the substrate than in the power lines, a much smaller circuit
can control the substrate-bias. This leads to negligible penalties
in area and speed in the VTCMOS. Global routing of substrate-
contacts, however, may impose an area penalty, which may in
tum make the application of the VTCMOS to existing macro de-
signs impractical. It has been experimentally evaluated that the
number of substrate (well) contacts can be greatly reduced in
low-voltage environments [10-12] . Using a phase-locked loop
and an SRAM in a VTCMOS gate-array [11], the substrate noise
influence has been shown to be negligible even with 11400
of the contact frequency compared with the conventional gate-
array. A DCT (Discrete Cosine Transform) macro made with the
VTCMOS [12] has also been manufactured with substrate- and
well -contacts only at the periphery of the macro; it worked with-
out problems realizing power dissipations more than one order
of magnitude smaller than a DCT macro in the conventional
CMOS design.
B. vrCMOS Circuits
Several variants have been reported [7,9-12] for the
VTCMOS scheme, whose salient features are summarized in
Fig. 4.
1.5
0.0
0.0
'0
Ql
.
iii
E
o 1.0

c::
o

0..
'00
rJl
(5 0.5
Q5
:i:
o
a..
0.5 1.0
Speed (Normalized)
Figure 2 Speed and power saving by optimum V
oo
and V
th

62
Scheme
MTCMOS

Ref.[a]
V
DD
on-off
St'by
VTCMOS
n-well
p-well
Ref.[ 12]
V
aa
control
EVTCMOS
St'by
Ref.[ 13]
V
DD
&V
aa
control
Effect
Penalty
+, st'by reduction
- large serial MOSFET(*)
slower,larger,lower yield
- special latch
+ IJ\lfh compensation
+ 'stlby reduction
+'OOQ test
- triple well (desirable)
+ IJ. \lfh compensation
+ 'stlby reduction
+,ODQtest
- large serial MOSFET(*)
Figure 3 MTCMOS, VTCMOS, and EVTCMOS.
A self-adjusting threshold-voltage scheme (SATS) [7] re-
duces the V
th
fluctuation. When V
th
is lower than a target value,
larger leakage current flows through a leakage current monitor
(LCM) and turns on a self-substrate bias (SSB) circuit. As a re-
sult, V
BB
goes deeper and causes V
th
to increase. Thus the sub-
strate bias is controlled such that the transistor leakage current
is adjusted to be a constant value. This means that the V
th
process
fluctuation can be canceled by the SATS. The measured overall
V
th
controllability including static and dynamic effects is
0.05V while using a bare process V
th
fluctuation of 0.15V.
The same idea is also presented in Kaenel and coworkers [15].
Two standby power reduction (SPR) circuits [9,10] have been
reported to lengthen battery life in mobile applications. One
circuit in Seta [9] switches V
BB
between the power supply and
an additional supply for substrate bias. It requires three exter-
nal power supplies but takes less than O.I,us for the substrate
bias switching. Triple well technology is a must. The other circuit
in Kuroda [10] employs the SSB for the substrate bias. No addi-
tional external power supply or additional step in process
is required. An active-to-standby mode transition is performed
by the SSB, and hence takes about l00,us. On the other hand,
a standby-to-active mode transition is carried out by an MOS
SATS SPR SATS + SPA
LCM
--------1
Circuit
l .J
Ref.[?]
"ss
1......4 ... VBB.p

Ref.[9]
V
BB
Ref.[ 10]
V
BB
Ref.[ 12]
Active
St'by
Transition
time
Effect
SSB
no consideration
+ IJ.V
th
compensation
(St'by Active)
0.1us (Active St'by)
+'st'by reduction
+1
000
test
SSB
0.1us (St'by Active)
100us (Active St'by)
+'st'by reduction
+'000 test
SSB
SSB
0.1us (St'by-+ Active)
100us (Active St'by)
+IJ. Vth compensation
+ Ist'by reduction
+/oootest
Penalty
- triple well (desirable) - 3 suppliesrequired - triplewell (desirable)
- triple well required
LCM: Leakage Current Monitor, SSB: Self SubstrateBias, SCI: Substrate ChargeInjector
Figure 4 VTCMOS variants.
63
References
Valuable discussions and constant encouragement by T. Fujita,
K. Suzuki, T. Furuyama, and Y. Unno are appreciated.
Small
swing
signal
analog
signal

<D
t
<D
>
C
o
o
Cl
c:::

en
ca
c:::
C)
en
5. ACKNOWLEDGMENT
Internal circuit (low\!fh)
Low-VOltage memories
Small-swing signals
(clock, bus...)
----I

(ij 1
__-....-...--- ...a 1 c::: 1

Small
swing
signal
\.bo
Figure 5 Future low-power VLSI.
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digital design," IEEE J. Solid-State Circuits, vol. 27, no. 4, Apr. 1992,
pp. 473-484.
[2] T. Kuroda and T. Sakurai, "Overview of low-power ULSI circuit tech-
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[3] D. Liu and C. Svensson, "Trading speed for low power by choice of sup-
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Jan. 1993,pp. 10-17.
[4] T. Kuroda, "Low power and high performance-Can supply voltage
be scaled below 1V?" Rump session in Symposium on VLSI Circuits,
June 1996.
[5] T. Sakurai and A. R. Newton, "Alpha-power law MOSFET model and its
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State Circuits, vol. 25, no. 2, Apr. 1990, pp. 584-594.
[6] S. Sun and P. Tsui, "Limitation of CMOS supply-voltage scaling by
MOSFET threshold-voltage variation," Proc. CICC'94, May 1994,
pp. 267-270.
[7] T. Kobayashi and T. Sakurai, "Self-adjusting threshold-voltage scheme
(SATS) for low-voltage high-speed operation," Proc. CICC'94, May
1994, pp. 271-274.
[8] S. Mutoh et aI., "1-V power supply high-speed digital circuit technology
with multithreshold-voltage CMOS," IEEE J. Solid-State Circuits, vol. 30,
no. 8,Aug. 1995,pp. 847-854.
[9] K. Seta et aI., "50% active-power saving without speed degradation using
standby power reduction (SPR) circuit," ISSCC Dig. Tech. Papers, Feb.
1995, pp. 318-319.
[10] T. Kuroda et aI., "A high-speed low-power O.3/lmCMOS gate array with
variable threshold voltage (VT) scheme," Proc. CICC'96, May 1996,
pp.53-56.
[11] T. Kuroda et aI., "Substrate noise influence on circuit performance in variable
threshold-voltage scheme," Proc. ISLPED'96, August 1996, pp. 309-312.
[12] T. Kuroda et aI., "A 0.9V 150MHz 10mW 4mm
2
2-D discrete cosine trans-
form core processor with variable-threshold-voltage scheme," IEEE J.
Solid-State Circuits, vol. 31, no. 11, Nov. 1996, pp. 1770-1779.
[13] M. Mizuno et aI., "Elasti-V, CMOS circuits for multiple on-chip power
control," ISSCC Dig. Tech. Papers, Feb. 1996, pp. 300-301.
[14] S. Mutoh et aI., "A 1V multi-threshold voltage CMOS nsp with an effi-
cient power management technique for mobile phone application," ISSCC
Dig. Tech. Papers, Feb. 1996, pp. 168-169.
4. DISCUSSIONS AND CONCLUSIONS
At room temperature, CMOS circuits operate at supply voltages
as low as 0.2V, which is theoretically derived in [16] and ex-
perimentally examined in [17]. Optimization of device parame-
ters [18] and tradeoffs between speed and power [3] are
reported. The impact of V
th
variation on circuit speed is experi-
mentally investigated and its model is derived in [6].
Silicon on Insulator (SOl) CMOS processes have several
potential advantages over the traditional bulk CMOS technolo-
gies. These include a lower parasitic substrate capacitance and a
deeper subthreshold cut-off slope. In addition, one circuit fam-
ily in SOl technology has recently attracted much attention for
its unique way to control V
th
; it involved tying the body to the
gate [19]. This can be considered as a kind ofVTCMOS in SOl
technology. This circuit is called DTMOS (dynamic threshold
voltage MOSFET). Consider using an n-channel MOSFET.
When the gate of the NMOS increases, the bulk tied to the gate
also becomes high, lowering the threshold voltage. Conse-
quently, larger switching current flows to increase the operation
speed. On the other hand, when the gate voltage becomes low,
the threshold voltage becomes higher and suppresses the leak-
age current; this assures a low standby current. The issue with
this scheme is that the supply voltage should be below the for-
ward voltage of the junctions (---0.7V). Otherwise, when VDD is
applied to the NMOS gate, bulk-source junctions tum on to in-
crease power dissipation drastically. Another interesting ap-
proach is to realize SATS in SOl technology [20]. The tunable
range of the threshold voltage with the back-gate of a dual gate
SOl technology is wider than the bulk CMOS. An MTCMOS
circuit in SOl technology is also reported [21].
A possible future low-power VLSI is illustrated in Fig. 5. Some
kind of threshold engineering both in circuit and device tech-
nology will be essential in the future to enable stable operation
in low-voltage environments. Optimum voltages for logic gates,
memory circuits, and analog circuits may vary widely. They
may change as workload varies with time in data processing.
"V
DD
on demand" in terms of both static and dynamic adjust-
ment of the supply voltage will be carried out on a chip by
DC-DC converters [22]. Low-voltage circuit design is another
future challenge. Noise issues, especially those induced by in-
ductance and resistance along power lines, should be studied.
SOl based technologies are other candidates for achieving ultra
low voltage LSls armed with the DTMOS where gate and bulk
are tied together to optimally control the threshold voltage.
switch, and hence is completed in 0.1,us. This "slowfalling asleep
but quick awakening" feature is acceptable for most applications.
The latest circuit in Kuroda [12] achieves both the SATS and
the SPR capability at the same time. Operation principles are the
same as the circuits in Kobayashi and Sakuri, and Kuroda
[7,10], and hence the same circuit performance.
3. LOW-VOLTAGETECHNOLOGIES
64
[15] V. Kaenel et aI., "Automatic adjustment of threshold & supply voltages
for minimum power consumption in CMOS digital circuits," Proc. Symp.
on LowPowerElectr., 1994, pp. 78-79.
[16] R. M. Swanson and 1. D. Meindl, "Ion-implanted complementary MOS
transistors in low-voltage circuits," IEEEJ. Solid-StateCircuits, vol. sc-7,
no. 2, pp. 146-152, April 1972.
[17] J. B. BurrandT. Shott, "A200mVself-testing encoder/decoder using Stanford
ultra-low-power CMOS," in ISSCCDig. Tech. Papers, Feb. 1994, pp. 84-85.
[18] Z. Chen, J. Burr, 1. Shott, and J. Plummer, "Optimization of quarter mi-
cron MOSFETs for low voltage/low power application," Proc. IEDM'95,
Dec. 1995,pp.63-66.
65
[19] F. Assaderaghi et aI., "A dynamic threshold voltage MOSFET (DTMOS)
for very low voltage operation," IEEE Electron Device Letter, vol. 15,
no. 12, Dec. 1994,pp.51Q-512.
[20] I. Yang, C. Vieri, A. P. Chandrakasan, and D. Antoniadis, "Back gated
CMOS on SOIAS for dynamic threshold control," Proc. IEDM'95,
Dec. 1995,pp.877-880.
[21] T. Douseki et aI., "A 0.5V SIMOX-MTCMOS circuit with 200ps logic
gate," ISSCCDig. Tech. Papers, Feb. 1996, pp. 84-85.
[22] V. Gutnik and A. Chandrakasan, "An efficient controller for variable
supply-voltage low power processing," Proc. Symposium on VLSI Cir-
cuits, June 1996, pp. 158-159.