Eindhoven University of Technology

MASTER

Design of a 12-bit, 250 MPSPS digital-to-analog converter in 0.35 Mum CMOS technology

Houet, Jack M.

Award date:
1997

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 Eindhoven University of Technology
Faculty of Electrical Engineering
Electronic Signal Processing Systems (SES)

Design of a 12-bit, 250 MSPS

digital-to-analog converter in
0.35J.lDl CMOS technology

J.M. Douet
May 1997

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Report of graduation work,

performed from September 1996 to May 1997.
at the Philips Research Laboratories in Eindhoven.

Coach: Prof. Dr. If. R.J. van de Plassche

e Philips Eindhoven N.V. 1997

The Eindhoven University of Technology accepts no responsibility
for the contents of graduation reports.
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Acknowledgments

This report is written in the context of my graduation at the TUE, University of Technology in
Eindhoven. My graduation took place at Philips Research Laboratories in Eindhoven for a
period of nine months, from 1 September 1996 to 31 May 1997.
I want to thank all members of the cluster Integrated Receivers for their support and useful
advises, especially Ardie Venes for his instructive coaching. Furthermore I want to express
special thanks to Rudy van der Plassche for giving me this great opportunity of graduating at
Philips Research Laboratories and of course for his support in completing this graduation
project.

Eindhoven, 30 May 1997,

Jack Houet

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Abstract

This report presents the circuit implementation and IC-Iayout of a 12-bit, 250 MSPS, digital-
to-analog converter (DAC). The DAC is implemented in C75, a 0.35J..lm, five layer metal
CMOS technology. At the differential output of the DAC, loaded with two external son
resistors, a full-scale differential voltage of2Vpp will be generated.

The matching perfonnance and transition frequency of CMOS technologies C75 and its
predecessor C 100 are analyzed. If the driving voltage V gs - VI (V81) of the transistors is low
enough, both parameters are in favor ofC75. Due to the low supply voltage of3.3V, low
driving voltages are inevitable and therefore it may be concluded that C75 is superior
compared to ClOO.

The DAC is based on a coarse-fine architecture with 6 MSBs (Most Significant Bits) and 6
LSBs (Least Significant Bits) driving the coarse part and the fine part respectively. This
architecture is chosen based on calculations of sampling time uncertainties and DNL. The
binary coded MSBs are encoded into a thennometer code by means of a segment decoder.
Master-slave latches are implemented to synchronize the encoded MSB signals with the
binary coded LSB signals. To reduce clock feedthrough buffers are added in between the
master-slave latches and the current switches. The differential output signals of these buffers
are used for driving the current switches. Depending on the state of the input bits the switches
switch their corresponding current to the inverting or the non-inverting output of the DAC.

Special attention is paid to the IC-package in which the DAC is implemented. The influence
of the IC-package on the perfonnance of the DAC is discussed.

To improve the linearity perfonnance of the DAC a special layout arrangement is required.
Every bit- and segment current source is constructed by means of a certain number of parallel
unity current sources. The dimension of the transistor used for one unity current source is
derived from the DNL calculations. To cancel effects of process gradients across the chip, the
unity current sources that make up a certain bit- or segment current source are unifonnly
distributed in a matrix. The same reasoning holds for the current switches. Every current
switch is constructed by means of a number of parallel unity current switches, but are
unifonnly distributed in an array rather than in a matrix.

Simulations of the DAC show a glitch energy of2.5pVs in the single ended output signal.
This result is not sufficient to obtain a glitch energy smaller than the energy of a half LSB.
The settling time of the DAC to a lO-bit (!) accuracy equals 1.8ns.
Because of the complexity of the complete circuit, it is impossible to simulate specifications
such as S/(N+THD)-ratio and SFDR. Measurements of test chips are needed to detennine
these specifications.

The chip area is approximately 5 x 2 mm2 • The power consumption of the DAC equals 200
mW, this is without the contribution of the digital circuitry.

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Contents

Acknowledgments 3

Abstract 5

Contents 7

List of symbols 9

Introduction 11

1 Digital-to-analog conversion 13
1.1 Performance definitions of digital-to-analog converters 13
1.1.1 Signal-to-noise ratio 14
1.1.2 Sampling time uncertainty 14
1.1.3 Sampling clock time uncertainty 15
1.1.4 Integral non-linearity 16
1.1.5 Differential non-linearity 16
1.1.6 Sin(x)/x-distortion 16
1.1.7 Glitches 17
1.1.8 Switching characteristics 18
1.2 The architecture of the DAC 19
1.2.1 Evaluation of the implementation of an R-2R ladder network 19
1.2.2 DNL calculation of a binary weighted DAC 21
1.2.3 DNL calculation of a coarse-fine DAC 23
1.2.4 INL performance of different kind of architectures 26
1.2.5 Conclusions 27
1. 3 Specifications and design criteria of the DAC 27

2 Circuit implementation 28
2.1 A complete block diagram 28
2.2 Characteristics of different MOS technologies 29
2.3 Input circuitry 32
2.4 Segment decoder 33
2.5 Single-differential converter 36
2.6 Clock buffer 37
2.7 Master-slave latch 38
2.7.1 A basic CMOS latch 39
2.7.2 Improving the CMOS latch 41
2.7.3 The master-slave latch 45
2.8 Buffer 46
2.9 Current switch 48
2.10 Current source 50
2.11 The output circuit of the DAC 52
2.12 Reference current sources 56

3 Simulations 57
3.1 Glitch energy simulation 57

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3.2 Switching characterization 57

4 Layout 59

5 Conclusions 61

References 62

Appendices

A.I Floorplan of the segment decoder 64

A.2 Floorplan of the column decoder 65
A.3 Floorplan of the row decoder 66
A4 Floorplan of the local cell decoder 67
AS Schematic of the logic AND gates 68
A6 Schematic of the logic OR gates 69

B Schematic of the single-differential converter 70

C Schematic of the clock buffer 71

D Schematic of the master-slave latch 72

E Schematic of the buffers 73

F Schematic of the current switches 75

G Schematic of the current sources 77

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List of symbols
Symbol Description

A Amplitude
Ao,A) Gain of a differential pair of transistors
ADC Analog-to-digital converter
A(f3) (3-spread parameter
A(VI ) VI-spread parameter
M Amplitude deviation
B(f3) (3-spread parameter
bk Bit k
Cb Bonding pad capacitance
Cj Interconnect capacitance
CL Capacitive load
CMOS Complementary metal oxide semiconductor
Co Output capacitance of the DAC
Cox Capacitance per unit area gate oxide
Cp Package capacitance
DAC Digital-to-analog converter
DNL Differential non-linearity
Egliteh Glitch energy
ELSB Energy of one least significant bit (LSB)
en Noise energy
ESD Electrostatic discharge
fb -3dB bandwidth
f elk Clock frequency
fin Input signal frequency
fs Sample frequency or conversion rate
fr Transition frequency
gm Transconductance of a transistor
HOm) Transfer function
IC Integrated circuit
Id Drain current
I Fs Full-scale output current
I tai ) Tail current
Itail,opl Optimal tail current
I Qs Quantization step current
INL Integral non-linearity
k Boltzmann's constant
L Gate length
LSB Least significant bit
Lw Wire inductance
MSB Most significant bit
Pd Power dissipation
~ Bonding pad resistance
Ri Damping resistance
Ri Interconnect resistance
RL Load resistor
Ro Output resistance of the DAC
Rn Equivalent noise resistance
Rref Reference value

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SIH Sample and hold circuit

SNR Signal-to-noise ratio
Sod Slope ofthe differential output voltage
T Temperature
41 Delay time
tc Fall time
th Hold time of the SIH circuit
THD Total harmonic distortion
1:"" Gate oxide thickness
tPD Propagation delay time
tr Rise time
ts Settling time
Ts Sample period
Velle,diC Differential clock signal
Vdd Supply voltage
Vds Drain-source voltage
V gs Gate-source voltage
Vgt Driving voltage, V gs - VI
Vid Differential input voltage
Vid,sat Differential input voltage required to tum off one transistor of a pair
V od Differential output voltage
Vos Offset voltage
Vout Analog output voltage ofthe converter
Vss Ground potential
VI Threshold voltage
W Gate width
P Current factor
i\telle Time uncertainty of clock generator
Mmax Maximum sampling time uncertainty
E Relative accuracy
~ Mobility in channel
l; Damping ratio
ron Undamped natural frequency
cr(i\Vt) Standard deviation ofthe matched pair spread of the threshold voltage V t
cr(i\P1P) Standard deviation ofthe matched pair spread of relative current factor i\P/P
cr(MJI) Standard deviation ofthe difference in currents in two
matched transistors
RC-time

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Introduction

Digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) provide the link
between analog transducers and digital signal processing systems. The demand for high-
specified converters has increased tremendously over the last decade. Nowadays these
converters are implemented in instrumentation, video applications, digital audio, computer
systems, etc. Two important performance definitions are the conversion rate and the
resolution of the converter.
In digital audio applications the resolution of the DAC is one of the key specifications, in [9]
a 16-bit, 44kHz audio CMOS DAC with a dynamic range of95 dB is discussed. In video
DACs the conversion rate is more important, in [10] a 6-bit, 100MHz video CMOS DAC is
discussed. Generally, the design of the DAC is a trade-off between conversion rate and
resolution.

Up to now higher bandwidths are achieved in bipolar technologies compared to CMOS

technologies. In bipolar technologies high-speed DACs are developed with conversion rates
into the Gsamples/s range [11], [12]. Yet, realizing DACs in CMOS has many advantages
such as low cost and low power consumption. Moreover CMOS DACs have good
compatibility with digital systems, so they may be easily integrated on the same chip as these
digital systems.

In chapter 1 the basic principles of digital-to-analog conversion are explained. Section 1.1
gives an overview of the most important performance definitions of the converter. Different
kinds of architectures are evaluated in section 1.2. In section 1.3 the specification demands
and design criteria are summarized.
In chapter 2 a complete block diagram of the converter is discussed. In section 2.2 some
remarks are made about the characteristics of different CMOS technologies. In the remaining
sections of chapter 2 the circuit implementation of the different building blocks of the
converter are discussed.
Simulation results are given and explained in chapter 3.
In chapter 4 is the layout arrangement of the DAC discussed.

Furthermore, the hand calculations mentioned in this report are performed with MOSCA.
MOSCA is a program that calculates output data of a transistor based on input values and
specified conditions, such as V gh W, L, Id etc.

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Chapter 1 Digital-to-an alog conversion.

In this chapter an introduction is given of digital-to-analog conversion. Different kinds of

properties of the digital-to-analog converter (DAC) will be discussed; e.g. glitches, settling
time, INL and sampling time uncertainties. These properties and the architecture of a high-
speed DAC determine its performance.

1.1 Performance definitions of digital-to-analog converters.

The basic function of a digital-to-analog converter (DAC) is to reconstruct an analog signal
from a digital input code. The digital input code consists of bits and is applied to the converter
as parallel signals. Because of the finite number of bits the output is quantized into discrete
amplitude levels. A bit is defmed as a signal which has two possible values, in consideration
of the positive logic convention: a 'I' represents a 'true' or 'active' state and a '0' represents
a 'false' or 'not-active' state. The minimum 'ON-level' and the maximum 'OFF-level' are
called logic levels.

A simple model of a DAC is shown in figure 1-1. The input bits bo up to bn-I> where bo is the
least significant bit (LSB) and bn- I is the most significant bit (MSB), are the digital inputs of
the n-bit converter.

digital -- .... analog

output
input

Figure 1-1: Block diagram ofa DAC.

Basically, a DAC consists of a sampler circuit (D/A), a sample-and-hold circuit (S/H) and a
low-pass reconstruction filter. The output signal of the sampler consists of a series of zero-
width impulses at equidistant intervals equal to the sampling period. The amplitude of the
impulses represents the analog value of the converted digital input bits. Note that the output
signal of the sampler is zero at all times except at the sampling moments. During conversion
of the input bits the analog output signal is kept constant by the S/H circuit. The
reconstruction filter is added to eliminate the repeated spectra of the input signal around the
sampling frequency and multiples of the sampling frequency, resulting in smoothing out of
the time-discrete output signal of the S/H circuit.

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The analog output function of the binary coded converter equals:

n-I
Vout = Rref 2>k2k (1.1)
k=O
where bk is the value of the kth bit and R,.ef is a reference value. This reference value may be a
voltage, a current or a charge. The factor 2 k indicates the binary-weighting factor of the
different input bits. R.-ef is the smallest step with which YOU! can change and is called a
quantization step.

In the following sections the most important properties of D/A-converters will be discussed.

1.1.1 Signal-to-noise ratio.

The quantization process introduces an irreversible error. These errors have a random
amplitude distribution and are therefore often called quantization noise.
The signal-to-noise ratio (SNR) is defined as the quotient of the analog signal and the noise
measured at the output of the converter. SNR depends on the number of quantization levels
2°_1 used in an n-bit converter. The theoretical SNR for a sine wave is given by [1]:
SNR =6.02 n + 1.76 (1.2)

where n is the number of bits. Thus for an ideal 12-bit DAC, SNR = 74 dB.
In practice the theoretical value of the SNR can only be approximated because measurements
of the SNR also includes sampling time uncertainty, glitches and non-linearities.
The SNR is a dynamic specification and is very important in digital signal processing systems
such as digital audio and digital video.

1.1.2 Sampling time uncertainty.

When samples are taken at equal time intervals and conversion takes place at time intervals
that show a time uncertainty, additional errors are introduced in the output signal of the
converter.
In figure 1-2 is shown that a sampling time uncertainty ~t results in an amplitude variation
M.

amplitude

A+M
A
t t+~t

sampling time

Figure 1-2: Sampling time uncertainty.

To avoid a significant loss of quantization resolution, /1A should be smaller than 1 LSB. The
tightest constraint for the sampling time uncertainty is obtained at the zero-crossing of a sine

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wave signal with a frequency equal to half the sampling frequency. The maximum sampling
time uncertainty is derived in [1]:

(1.3)

with n the resolution of the converter and fin the input signal frequency.

For a 12-bit DAC and an input signal with fin = 125MHz the maximum allowed sampling time
uncertainty becomes 0.6ps!

1.1.3 Sampling clock time uncertainty.

In figure 1-3 a simplified model used for calculation of pulse-to-pulse time uncertainties of a
clock generator is depicted.

squaring circuit
n
V clk

Figure 1-3: Sampling clock time uncertainty.

An ideal sine wave signal V elk = Asin(2n'felk) is applied to the squaring circuit. The squaring
circuit generates noise (mostly thermal noise) en with a bandwidth ~f equal to the bandwidth
of the squaring circuit fb • The addition of noise results in a pulse-to-pulse time uncertainty,
which depends on the amplitude of the noise and the slope of the sine wave.
Considering the squaring circuit as a first order system, the pulse-to-pulse time uncertainty of
the clock generator can be derived [1]:

~21! kT Rn ft,
/).t elk = --=------ (1.4)
1! felk A

with Boltzmann's constant k = 1.38'10.23 JIK, temperature T and Rn the equivalent noise
resistance of the squaring circuit.
The pulse-to-pulse time uncertainty should be less then maximum allowed time uncertainty
calculated with equation (1.3), this restriction sets a demand on the noise resistance Rn of the
squaring circuit.

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1.1.4 Integral non-linearity.

The linearity error of a DAC, expressed in mUltiples of LSBs, is defined as the deviation of
the measured analog output values from a straight line drawn through zero and full-scale
(figure 1.4). This linearity error is also called integral non-linearity (INL).

analog
output
measured value
% .-- full-scale
% "'
% +Y2 LSB /~ ideal curve
/ ""./"""/""
~ ~/":::":">;:"""/
% "//"" ":/:// \ -Y2 LSB
~ ././

X
001 011 101 III
000 010 100 110
digital input

Figure 1-4: Integral non-linearity ofa converter.

To guarantee monotonicity of the converter, the INL must be smaller than a 'lj LSB [1].

1.1.5 Differential non-linearity.

The differential non-linearity (DNL) error of a converter describes the difference between two
analog output values compared to 1 LSB generated by two adjacent digital input code words.
The DNL is calculated over the full range of the converter. DNL is zero if every transition to
its neighbors equals 1 LSB.
To obtain a monotonic converter the maximum DNL is ±1 LSB [1]. In this case an increase of
the binary input code by 1 LSB results in an increase of the analog signal between 0 and 2
LSBs.

1.1.6 Sin(x)/x-distortion.

During the reproduction of a digital input signal into an analog value, the output signal of the
DAC is kept at a constant voltage. For this purpose a circuit block S/H is added in figure 1-5.
This zero-order hold operation introduces an amplitude distortion.
The amplitude characteristic ofthe SIH-circuit is derived [1]:

. (OJt h )
sm--
IH (j OJ)I =t h "'----_2------:.
OJ t h
(1.5)

2
with th the time in which the circuit is in the hold-mode and ro = 21t·fin •

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The normalized amplitude characteristic IRoUm)1 for a system using Nyquist sampling (fin = Y2
fs), expressed in dB, is plotted in figure 1-5.

IHoOco)1
[dB]

o
-3.92

o fs frequency [Hz]

Figure 1-5: Normalized amplitude characteristic ofa S/H circuit.

From the figure it is clear to see that the hold operation results in an amplitude reduction, this
is the so-called sin (x)/x distortion.
In normal operation the hold time 4t is equal to the sampling time T s • In a DAC that is
sampled at Nyquist rate, the maximum input frequency is equal to half the sampling
frequency. Inserting m = 21t·f;n = 1t·fs into equation (l.5) results in an amplitude reduction of
3.92 dB (see figure 1-5).

Note that the zero-order hold operation can be used as a simple low-pass filter if signals are
applied with low frequency with respect to the sampling frequency.

1.1.7 Glitches.

If the input code of a DAC changes by I LSB it can pass through a major transition (e.g. from
code 0111... to 1000... through 0000...). For a binary weighted DAC the largest transition
appears at half-scale, when the MSB changes state. If the switches are faster (or slower) to
switch off than on, the DAC will give for a short time a zero or full-scale output value. These
spikes are commonly known as glitches.
For a 1 LSB change of input code the output voltage of the DAC is depicted in figure 1-6.
The glitch energy, Eglitch, is defined as:
~ ~

E glilch = ~VOUI (t) - Vn (t)1 dt + ~VOUI (t) - Vn+1 (t)1 dt (1.6)

'
0 '1
The maximum allowable glitch energy, calculated with (1.6), should be smaller than the
energy of a Y2 LSB. The energy of 1 LSB is calculated with:

E = Vfull-scale. T (1.7)
LSB 2n -1 s
with n the number of bits and T s the sample period.

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V out
[V]

Vn+ 1

o t [s]

Figure 1-6: Output voltage ofa DACfor a 1 LSB data transition.

For a 12-bit DAC with fs = 250MHz and a 2Vpp differential output voltage the energy of I
LSB is calculated, ELSB == 2pVs. Thus the maximum allowable glitch energy becomes Eglitch ==
IpVs.

1.1.8 Switching characteristics.

The switching characteristics are illustrated in figure 1-7. At the falling edge of the clock
signal a full-scale data transition is reconstructed.

clock
'\1'-----------
I
I
code 4095
input data :
(full-scale input codeO /
transition)

V od = IV -------------- 10%
(code 0)

'-':--+---'1--+\
td ----------- 50%

------t 90%

---ti
_:....--Vod=-IV
LSB (code 4095)

Figure 1-7: Switching characteristics.

The definitions of the delay time t1i, the propagation delay time tpD, the settling time ts and the
fall time tf are simply illustrated in figure 1-7 and need no further explanation.

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1.2 The architecture of the DAC.

There are different ways to convert a digital code word into its analog value [1]. The used
architecture depends on the application ofthe converter. In this case a high-speed converter
has to be designed.
In the following sections different kinds of architectures are evaluated, in order to make an
appropriate choice from the available architectures.

1.2.1 Evaluation of an R-2R ladder network.

A first approach of realizing a 12-bit DAC using 12 equal current sources and an R-2R ladder
network is depicted in figure 1-8. The current switches are directly controlled by the digital
input code word. An R-2R ladder is implemented to obtain the binary weighting of the equal
currents I. The output current, the sum of all binary weighted currents, of the DAC is
converted into a voltage by an extemalload resistor RL •

digital input

DAC

v o--+---+-----.---+------'-"----'-"----.--+--,--+-,.-+_-----.
55

R-2R ladder
VddD--+---;-----.L.------------'----.L.-------'
;
i.•. _. _.•.•. __ •. _. _.•.•.•. _. _.•.•_•.• _•.•.•.•. _. _.•. _.•.•.•.•_•.•. _.•__ .•. _.•. _.•.•.•.•.•_•.•. _.•__ .• _. o._•._._..._. _.......•..._._.._... _.•.••.•._•.•.•.•._._. ._._._._... _~

Figure 1-8: Block diagram ofa DAC with an R-2R ladder network.

The impedance of the R-2R network is designed for son. Considering a maximum single
ended output voltage of IV over an effective impedance of2Sn (SOn ladder impedance
parallel to a son load resistor) a full-scale output current of20mA is required. To obtain this
full-scale value the current sources have to generate all together 12·1 = 360mA, this results in
an enormous power dissipation.

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To reduce power dissipation the implementation of an R-2R network is usually combined

with other conversion principles. Figure 1-9 gives an example of a DAt with an R-2R ladder
network combined with binary weighted current sources.

digital input
bll blo b. b. b., b. b, b, b, b2 b, bo
DAC

v".o---+..--

Figure 1-9: Block diagram ofa DAC with an R-2R ladder network and binary weighted current
sources.

In this case all current sources together have to generate 30mA to obtain a 20mA full-scale
output current. The total power dissipation is reduced.

The current switches are realized with MOS transistors. Due to the parasitic capacitances of
these transistors the individual bit currents will arrive with different delay times at the output
tenninal ofthe DAC. In figure 1-10 the output stage of the DAC with all parasitic
capacitances included is shown. The parasitic capacitance C is proportionally to the current
value that has to be switched.

;~._ •••••••• _ • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •• A •• • ••• • ••••••••• • • • • • • • ••• • •••••••••• _ ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• _ •••••••••••• , •••••••••••••••••••••••••••• _;

V.S o - - - - j ' : - - - . - - - - - - - - - , - - - , - - - - - - , - - - - - - , : - - - - - - . - - - - - - - - , ;

t1281 ----.------ t21

Vout o---,---'-----'------.--'--~..........,
R=R
,L 255C
Vddo--...L--i--------'---------'----'-_ _L----'-_ _-'-----J'---_ _---'----J
i•.•.•.•.•••.•.•.•.•.•.•.•.•.•.•.•.•.•.•.•.•.•.•.•.••• .•••.•.•.•.•.•.•.•.•.•.•.•.•.•.•.•.•.•.•.•.•.•.•.•.•.•.•.•••.•••••.•.•.•.•••.•.•.•.•.•.•.•.•.•.•.•.•••.•.•.•.•.•••.•.•.•••.•.•••.•.•.•.•.•.• .1

Figure 1-10: Output stage ofa DAC.

With R = 50n and C = 80fF the circuit of figure 1-10 is simulated. Due to the RC-
combinations in the R-2R ladder is it impossible to satisfy the stringent sampling time
uncertainty demand of 0.6ps (section 1.1.2). The simulated difference in delay time between
LSB and MSB current of 9ps is much larger than is allowed. These sampling time
uncertainties may be compensated by implementation of expensive, difficult to design SIH-
circuits at the output of the converter.

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Another disadvantage of this kind of architecture is the voltage drop across the resistor ladder,
especially in low-voltage technologies like C75. Moreover, the mismatching of the resistors in
the ladder will cause additional distortion.
All these aspects considered, the implementation of an R-2R ladder in a high-speed DAC is
not recommendable.

1.2.2 DNL calculation of a binary weighted DAC.

A block schematic ofa binary weighted DAC is given in figure 1-11. The binary weighted
current sources are controlled by the bit signals.

digital input
b ll b lO bg b, b7 b6 bs b4 b] b2 bl bo
DAC

v.. o---+---F=:::;::===+===================:::::;:==+=;=:=t=;==t-~

current sources &

switches

VOUIC----'------'----------------'-------L-----.J

Figure 1-11: Block diagram ofa binary weighted DAC.

In the following analysis the DNL perfonnance of this DAC architecture is evaluated.

The differential non-linearity (DNL) error of a DAC is defined as the difference between two
analog output values compared to 1 LSB, generated by two adjacent digital input code words
[1 ]:
(1.8)

with Dm = b n_! bn-2 •••••• bo a digital input code and I(Dm) the corresponding output current of
the converter.

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Every kth bit current source is constructed by 2k uncorrelated unity current sources in parallel.
A kth bit current can be written as a summation of a deterministic value 2kr and a stochastic
variable fu:
(1.9)

The stochastic variable fu represents the mismatching of the transistors used to generate the
kth bit current and has a normal distribution with a zero mean and a variance a2k' Because all
unity current sources are assumed to be uncorrelated, the variance of the kth bit current can be
expressed as a summation of the variances ofall2 k unity currents, a2k = 2k . 0'2.

The output current of a n-bit converter with input code Dm can be expressed as a summation
of all turned-on binary weighted current sources:
n-l n-I

£(Dm ) = L}k£k = 2)k(2 k I +~k) (1.10)

k=O k=O
with bk the value of the kth bit.

A statistic expression of the DNL can be derived by substitution of equation (1.10) into
equation (1.8):
n-I
DNL(Dm ) = I(b k - Ck)'~k (1.11)
k=O
with bk and Ck the values of the k th bit in the adjacent code words Dm and Dm_1 respectively.
Notice that the stochastic variable DNL(Dm) also has a zero mean and a variance a 2DNL(Dm)
that is equal to the sum of the variances of all unity current sources that are switched during a
1 LSB data transition.
The variance of the DNL(Dm) can be expressed as:
n-I

ai>NL(Dm ) = Ilb
k=O
k - I·
c k ai ( 1.12)

A plot of the standard deviation aDNL(Dm) for a 8-bit converter is shown in figure 1-12.

18
aDNL(Dm)

[0'] 16
14
12
10
8
6
4
I I
2
II I. 1.1. It I. II I. ~I ILII LII LII LIII. III I ,I III. 111.1.1.
I

o
o 25 50 75 100 125 150 175 200 225 250
digital input code Om

Figure 1-12: Standard deviation ofthe DNL ofa 8-bit binary weighted converter.

22 ©Philips Electronics N.V. 1997

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As expected, the standard deviation O'ONL(Dm) has a maximum at half-scale, the point in which
all unity current sources are switched. The maximum of the standard deviation O'DNL(Dm) is
easily derived from equation (1.12):

~=
-l
max(aDNL(D.. ») = La; (1.13)
k=O

In a binary weighted converter the DNL is maximum ±1 LSB (section 1.1.5). The maximum
standard deviation of a 12-bit converter is calculated with equation (1.13), max(O'DNL(Dm» ::;
64cr. If a three-sigma limit is demanded for the DNL to stay within 1 LSB, the standard
deviation of the unity current can be calculated:

a = 100% = 0.5% (1.14)

3·64
This order of accuracy is difficult to realize in CMOS technology. Using segment decoding
the accuracy demand can be reduced significantly. This will be discussed in section 1.2.3.

1.2.3 DNL calculation of a coarse-fine DAC.

In a n-bit coarse-fine DAC, p MSBs are decoded into a thermometer code with which the
coarse-part of the output current is driven. The coarse-part consists of 2P-1 segment current
sources. Each segment current source is constructed by 2q parallel unity current sources. The
remaining q ::; n - p LSBs are used to drive the binary weighted current sources in the fine-
part of the output current.

In section 1.2.2 was determined that the variance dl ONL(Dm) of the statistical variable DNL(Dm)
is linearly proportional to the number of unity current sources that are switched during a 1
LSB data transition. Due to the segment decoding in a coarse-fine DAC this maximum
number of unity current sources is considerably reduced.

The statistic variable DNL and its variance dl DNL(Dm) of a coarse-fine DAC are derived in the
same way as described in section 1.2.2.1:
n-p-l 2P -2
DNL(Dm ) = L(bk - Ck)'~k + L(si - t')'~1 (1.15)
k&O 1=0

n-p-I 2P -2

a;NL(D.. ) = Llbk -ck!·a; + Lisl -tll'a( (1.16)

k=O I~O

with O'2k the variance of the kth bit current, 0'21 the variance of the lth segment current and with
bk (Sl) and Ck (tl) the values of the kth bit (lth segment) in the adjacent code words Dm and Dm- l
respectively. The stochastic variables fu and AI represent the mismatching of the transistors
used to generate the kth bit current and the lth segment current. Notice that the statistic variable
DNL(Dm) has a zero mean and a variance ~ DNL(Dm) that is equal to the sum of the variances
of all unity current sources that are switched during a 1 LSB data transition.
The largest current that has to be switched during an arbitrarily transition of 1 LSB input code
is equal to just one segment current.

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The maximum standard deviation crONL(Dm) can now easily be derived from equation (1.16):
n-p-. n-p-I

max(OODNL(D.. ») = La; +00,2 = L 2

k=O k=O
k
00 2 + 2 n - p 00 2 = .J2 n - p
+) -1· 00(1.17)

with n the resolution and p the number of decoded bits, pE [1 ..n].

Note that the value of (s. - t.) in equations (1.15) and (1.16) is equal to 1 (or -1) for only one
segment current that is switched during a 1 LSB transition.

From equation (1.17) can be concluded that the DNL performance of the DAC improves if the
number of decoded bits p is increased. An optimal DNL performance is obtained if all input
bits are decoded into a thermometer code (p = n), in that case the maximum standard
deviation of the DNL max(crONL(Om») becomes equal to the standard deviation of one unity
current cr.

Example: In the coarse-fart of a 8-bit DAC, 4 MSBs (p = 4) are decoded into a thermometer
code in order to drive 2 - 1 = 15 segment current sources. The remaining 4 LSBs are used to
drive 4 binary weighted current sources. A block schematic of this DAC is depicted in figure
1-13.
digital input
bs b4 b3

V.. O----I--.....;....-.,....--f--...:...--------,--+--...---+---,--+-,...,....,--t.,.,--+---e-t

Vdd31!i
RL=R

V out · :

:._._.~ ••••••. _.•.•••••••.••_.•••••.•.•.•••••._.•.•••••••. _.•••••.•.•.•••••••••••.•.•••.•••.•••••.•.•.•.•••••••••••.•••••.•••••••••••••••.•.•••.•.••J

Figure 1-13: Block diagram ofa 8-bit coarse-fine DAC.

The maximum number of unity current sources that are switched during a 1 LSB input code
transition is easily derived from the block schematic. In this case is the highest number of
switched unity current sources equals 31, consisting of 16 unity current sources in the coarse-
part and 15 unity current sources in the fine part. In a 8-bit binary weighted DAC the
maximum number of switched unity current sources appears at the 1 LSB transition around
half-scale and equals to 255.

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From the example can be concluded that the DNL perfonnance is increased because the
maximum number of switched unity current sources in a coarse-fine DAC is reduced.
Figure 1-14 shows a plot of the standard deviation O'ONL(Om) of the coarse-fine DAC described
in the example. As expected, each time a segment is added to the output current of the
converter a maximum in O'ONL(Dm) is observed.

6....--------------------------,
CJoNl.(Dm)

[0'] 5
4+-C-+-CO-+-,---f---,---I----o--+-O--+-.,.-+--,----l---,---}---;-+--O-+--,--+--,----lr--;-+--O--+-C-j

3+-f---+-1I-++--f--+-'I-+--I-J-+-i-I---I-J-+-f-++--I-+-t-+~f-+-t-t--+-JH

O+--,--------,----,----r--...,..----,-------,-----,-----,---,J

o 25 50 75 100 125 150 175 200 225 250

digital input code Om

Figure 1-14: Standard deviation ofthe DNL ofa 8-bit coarse-fine converter with 4 decoded MSBs.

The maximum standard deviation of the DNL for a 12-bit DAC, max(O'ONL(Om»), is plotted in
figure 1-15 as a function of the number decoded bits p.

70
max«(jDNL(Dm»
60
50
'\.
40 "-"'-.
30
~
20
10
o
I 2 3 4
"""'--
5 6
number of decoded bits p
--
7 8 9 10 II

Figure 1-15: Maximum standard deviation ofthe DNL ofa 12-bit coarse-fine converter as afunction of
decoded bits p.

From the figure is clear that increasing the number of decoded bits p results in an
improvement of the DNL perfonnance.

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Knowing that a three-sigma limit is demanded for the DNL to stay within one LSB, the
standard deviation of one unity current in a 12-bit DAC with 6 decoded MSBs (p = 6), is
calculated:

a:: 100% :: 100% = 2.9% (1.18)

3· max(aDNL(Dm ) 3 ·11.3
It is clear that the accuracy demand of the unity current sources is not that stringent as it was
for the binary weighted DAC.

1.2.4 INL performance of different kind of architectures.

From section 1.1.4 is known that the integral non-linearity (INL) of the output of a converter
is defined as the difference between the "measured" output current and the "ideal" output
current taken from a straight line between zero and full-scale.

A statistical derivation of the INL as a function of the architecture of the DAC is much too
complex. However, with the aid of the transfer characteristics illustrated in figure 1-16 some
insight is obtained about the effect of segmentation on the INL performance.

analog
analog output
output

digital input digital input

(a) (b)

Figure 1-16: (a) TransJer characteristic oja binary weighted DAC. (b) Transfer characteristic oja
coarse-jine DAC.

Assume the largest current has a maximum error, while all other currents are errorless. The
largest current in a coarse-fine DAC is the segment current. The absolute error of this segment
current is smaller than the error in the MSB current of the binary weighted DAC.
Observing the transfer characteristics in figure 1-16a and figure 1-16b it is clear that the INL
(the difference between the straight line and the analog output signal) of the coarse-fine DAC
is smaller than the INL of the binary weighted DAC.

Note that the straight line is not drawn through zero and full-scale but is in this case a "best fit
" line. This altered definition makes no difference for the non-linearity performance of the
DAC.

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1.2.5 Conclusions.
In section 1.2.1 was determined that the implementation of an R-2R ladder network in a DAC
introduces inadmissible sampling time uncertainties.

The DNL of a binary weighted DAC is calculated in section 1.2.2. To obtain a monotonic 12-
bit converter the unity current sources have to be designed with an accuracy of 0.5%. This is,
in CMOS technology, almost impossible to realize.
The high accuracy demand can be significantly reduced, when a coarse-fine architecture is
used. Moreover, a coarse-fine DAC produces much smaller glitches than a binary weighted
DAC and it has a better INL performance.

A major disadvantage of the coarse-fine architecture is the additional circuitry needed to

make the segment decoder.

Finally, it can be concluded that the DAC is best realized with a coarse-fine architecture. The
number of decoded MSBs p is chosen to be 6. In this case the accuracy demand of one unity
current source of 2.9% can easily be satisfied and the amount of additional circuitry in the
segment decoder is acceptable.

1.3 Specifications and design criteria of the DAC.

Table 1-1 gives an overview of the most important specifications and design criteria of the
DAC. The main specification is the 12-bit accuracy at a conversion rate of250 MSPS.
The 2Vpp differential output voltage is a practical value, as well as the external 500 load
resistor. These values match the requirements of the system in which the DAC is
implemented. The requirements of the test set-up, in which the DAC is analyzed, also
correspond with the output specifications of the DAC.
To obtain a IV single ended output voltage of the DAC across a external load resistor of 500,
a 20 rnA full-scale output current has to be generated. So, for a 12-bit resolution an unity
current source of 5J.!A is required.
Due to the high frequencies a special IC package has to be used. The physical size of this
package limits the power dissipation of the circuit to 1Watt. The supply voltage is 3.3V.

Target specifications Values

Resolution n 12 bits
Conversion rate fs 250 MSPS
Differential output voltage Vod 2V DD
Output load resistor RL 500
Supply voltage Vdd 3.3V
, .. ~ ...
···· .. <·.l\\',· ".nn".....
• I .. ~ •...
'C'";m •.,.".."..,,,.. .....,
...... , '

Sampling time uncertainty ~t < 0.6ps

Glitch energy E"Jitch <lpVs
Full-scale current value IFs 2ornA
Quantization step current value I QS 5JJA
Accuracy of an unity current source (J' <2.9%
Power dissipation Pd <IW
Table 1-1: Target specifications and design criteria.

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Chapter 2 Circuit implementation.

In chapter 1 it is concluded that a 12-bit high-speed DAC is best realized with a coarse-fine
architecture. A complete block diagram of the coarse-fine DAC is given in section 2.1.
The converter has to be implemented in C75 CMOS technology. Section 2.2 gives an
overview ofthe most important transistor parameters in C75 and C100 CMOS technology,
special attention is paid to the differences of both technologies.
In the remaining sections the circuit implementation of the different building blocks of the
coarse-fine DAC are discussed.

2.1 A complete block diagram.

The DAC is based on a coarse-fine architecture with a differential current output. A complete
block diagram of the DAC is given in figure 2-1.

digital input
b4 bs b6 b7 bs

,
,
!_._. _,_. _ _.", __ ,_ _. _."._ ._._. _._.",.". _. _ ,_ _ _ _ i

Figure 2-1: A complete block diagram ofthe 12-bit coarse-fine DAC.

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When the bits arrive on chip they are immediately buffered. The digital input code word is
clocked-in by means ofthe D-Iatches at the rising-edge of an external single-ended clock
signal V c1k • In the coarse part of the DAC the binary code of the six most significant bits is
converted into a linear code, a so-called thermometer code, which controls 63 segment current
sources. Table 2-1 shows an example of a 3-bit binary code and the corresponding
thermometer code. To generate the thermometer code a segment decoder is added. The six
least significant bits are used to control the corresponding binary weighted current sources.

:::::::::;::::::::::::::::;; .. :::::;;".;;::::::: .. :: ..

· ~~~~SR~# ·
o o o o 0 o 0 o o o
o o 1 o 0 o 0 o o 1
o 1 o o 0 o 0 o 1 1
o 1 1 o 0 o 0 1 1 1
1 o o o 0 o 1 1 1 1
1 o 1 o 0 1 1 1 1 1
1 1 o o 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
Table 2-1: Binary code versus thermometer code.

Besides a reduction in DNL and INL (section 1.2.4) also the glitch energy is considerably
reduced by using segment decoding. In case of a binary weighted DAC, the largest glitch is
generated at the transition with input code 0111...1 to 1000...0. In this case the total amount of
switched current is the largest. The glitch energy of a coarse-fine DAC is not determined by
the MSB current but by the much smaller segment current.

To reduce all kinds of distortion on chip, e.g. clock feedthrough, the single-ended output
signals of the segment decoder and the D-Iatches are converted into differential signals.

The segment decoder introduces a signal delay between coarse andfine signals, causing
possible glitch errors. To reduce this error master-slave latches are implemented in order to
synchronize the digital information. These latches are active at the falling-edge of the
differential clock signal. In this way half a clock period is reserved to decode the MSBs into a
thermometer code and to convert the single-ended signals into differential signals.

To reduce clock feedthrough a buffer is added in between the master-slave latches and the
current switches. Depending on the state ofthe input bits the current switches will switch the
current to the non-inverting or the inverting output of the DAC. All bit currents are summed
and converted into a voltage by an external load resistor RL •

2.2 Characteristics of different CMOS technologies.

As mentioned before the DAC has to be implemented in C75 CMOS technology. C75 is a
0.35 Jlffi, five layer metal technology. In order to compare this new CMOS technology with
its predecessor C 100 (a 0.5 Jlffi, three layer metal technology) an overview of the most
important parameters is given in table 2-2. In [7] and [8] all parameter values, used in circuit
simulators, of respectively C75 and C100 are given.

©Philips Electronics N.V. 1997 29

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",
,. , ",,'" T"'I •••',
'i'
, ,,,:,,," NMOS····
;~;.",. . <::f PMOS ·,NMOS'" PMOS ."
Supply voltMe Vdd rvl 3.3 3.3 3.3 3.3
Minimum gate length Lnun l~j 0.5 0.5 0.35 0.35
Threshold voltMe Vto rvl 0.61 -0.63 0.64 -0.63
Current factor J3 [J.l.A/VZ] 100% 100% 172% 144%
Gate oxide thickness tax nml 12 12 8 8
':" ',., ... "' .... ,..... ,:.::,.,: ..
, ."'"
:' .. ,.,,'
""",",''':,',
»'"
I I! I I I ~~~~
r~~~~J ."."
.,','.,<
"

A(Vt ) mV'IAm 100% 100% 66% 135%

A(/3) f%'llm] 100% 100% 127% 60%
B(I3) [%] 100% 100% 58% 112%
Table 2-2: Parameters afCMOS technologIes C75 and ClOO.

The threshold voltages in both technologies are almost identical and are therefore considered
equal in the following calculations.

The transition frequency £ is defined as the frequency where the current gain of a transistor is
unity. The £ for a saturated transistor is derived in [3]:

It = ~~ . ~ (Vgs - ~) (2.1)

with J.l. the mobility in the channel and L the gate length.
Noticing that the current factor P is proportional to the mobility f.1, the ratio between the
maximum transition frequency in C75 and C 100 for an NMOS transistor is calculated:
£ L2
:!..!Ell... = 13C7S nUnC100
3.5
h C100 r:.. c" f3clOO
(2.2)

Because of the higher maximum £ in C75, this technology yields for higher bandwidths
compared to C 100.

Two identical transistors will have mismatches in their current factors and threshold voltages
due to e.g. mobility and gate oxide thickness variations [4]. This matched pair spread is
presented in terms of standard deviations of the difference in threshold voltage, cr(/iVt), and
the relative difference in the current factor, cr(/iP/P). The matched pair spread ofVt and P of
identical transistors can be estimated by evaluating the following matching model:

(2.3)

0'(6.13) = A(f3) +B(f3) [%] (2.4)

13 .JWL
in which W and L are the effective channel dimensions.

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The matching parameters AcYt), A([3) and B([3) are given in table 2-2. Notice that the
threshold voltage mismatch parameter AcYt) is decreased linearly in C75 with the gate oxide
thickness compared to ClOO [4]. The current factor mismatch parameters A([3) and B([3) are
increased in C75 compared to ClOO.

The current mismatch of two identically designed transistors is calculated [2]:

a2(M) = 4a2(~V;) +a2(~P)11002 (2.5)

I Vgt 2 P
This results in a current mismatch determined by cr(~Vt) for low V gt. For high V gt the
mismatch is determined by cr(~[3/[3).

From equation (2.5) it is clear that an optimum matching performance is obtained if the [3-
spread dominates the mismatch. In that case a V gt » V gt,eq should be applied to the transistor
pair. V gt,eq is defined as the V gt for which the contributions in the current mismatch of the V t-
spread and the [3-spread are equal:

V = 200 a(~V;) (2.6)

gt,eq ~p
a(-)
p
V gt,eq as a function of the square root of the transistor area is derived by substitution of
equations (2.3) and (2.4) into (2.6):

V = 200 A(V,) (2.7)

gt,eq A(P) + B(P)-,JWL

Figure 2-2 shows a plot of V gt,eq as a function of the square root of the transistor area for both
C75 and ClOO.

2.5 ,------------;::=====:::;1
V gt,equ
[V] 2

1.5 +-----"S.~----------___1

0.5 +-----------------___1

O+---,------r----,----,---,.-----r-----r----r---r----!

o 2 3 4 5 6 7 8 9 10
WL ["1m?]

Figure 2-2: Vgt,eq as afunction oJthe transistor area WI.

From figure 2-2 is it clear that C75, especially for small devices, requires a smaller V gt to
obtain an optimum matching performance compared to CIOO. Notice that V gt is limited
because of the low supply voltage of 3.3 V.

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Evaluating equation (2.5) the current matching performance of a NMOS transistor pair in C75
and C 100 can be compared. A fair comparison can only be made if the drain current and the
WIL-ratio of the transistors are identical in both technologies. To realize equal drain currents
with a certain WIL-ratio, the V gt applied to the CI00 transistor pair has to be corrected in
order to compensate the difference in the current factor 13 of both technologies:

VgtClOO ~ ~ fJPC7' Vgtc,s ~ 1.3 V

gtc,s
(2.8)
CIOO

For both C75 and C 100 the current matching is presented in figure 2-3 as a function of one
over the square root of the transistor area, with V gt as a parameter.

05 - - ClOO -----.
cr(LWI)
10010 , - - - - - - - - - - - - - - - - - - - - - , - . ,
.' Vrg.C75 = O.2V
8% +-------------------:~-~C_._.f

6% +-----------..-.-'----=--""----------j

4% +--------,-.-..'~"--------::~'--'=-=-----j
Vrg.C75 = OAV

o 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

-I
l/sqrt(WL) [JlIll]

Figure 2-3: Current matching a/transistors in C75 and ClOD technology.

Be,cause of the decrease of VI-spread, the current matching performance for low V gt is
improved in C75. For high V gt the mismatch is dominated by l3-spread and is therefore worse
in C75 compared to C 100. Normally low V gt are required because of the low supply voltage,
therefore the current mismatch is in favor ofC75.

2.3 Input circuitry.

The digital input bit signals and the clock signal are immediately buffered as they arrive on
chip. The single ended input clock signal is also buffered.
The CMOS input buffers are taken from the standard cell I/O library IOLIB_PL [13]. In this
way the DAC can easily be embedded with other digital systems on the same chip. All input
cells in the IOLIB_PL library have Electrostatic Discharge (ESD) protection.
The digital input code word is stored in the D-Iatches. Just like the input buffers, the D-Iatches
are taken from a standard cell library, the CORELIB library [13]. This library contains
standard cells for 0.35JlO1 VLSI digital designs. The D-Iatches in the coarse-part of the
converter, have a higher driving capability. This is necessary to compensate the propagation
delay time of the segment decoder.

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2.4 Segment decoder.

As mentioned before, the binary code of the six most important bits has to be decoded into a
thermometer code. A segment decoder is added to generate this thermometer code. The
segment decoder consists of 63 local cell decoders and two separate decoders, a row decoder
and a column decoder (figure 2-4).

column decoder

------10
i.

i2
1-0
Q)
~ i3
0
U
Q) i4
~

:::0 i,
1-0

i, 1----L~A~;fs;7fsi;/~7fs~'1t;71''-------'
v" -----~

63 local cell decoders

Figure 2-4: Block schematic o/the segment decoder.

The output signals of the D-Iatches (figure 2-1) representing the bits b6, b7 and bg are applied
to the column decoder. The output signals of the column decoder are indicated by jk, with k E
[0,7]. The logic function of this decoder is illustrated in a truth table, table 2-3.

Input signals Output signals

bg b7 b6 j, J6 is j4 .il 1: jt jo
0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 0 1 1
0 1 1 0 0 0 0 0 1 1 1
1 0 0 0 0 0 0 1 1 1 1
1 0 1 0 0 0 1 1 1 1 1
1 1 0 0 0 1 1 1 1 1 1
I 1 I 0 1 1 1 1 1 1 1
Table 2-3: Truth table o/the column decoder.

Simplified Boolean expressions of the output signals jk can be derived by evaluating the truth
table. These simplified expressions are presented in table 2-4.

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Column decoder expressions Row decoder expressions

K lie: n in
0 b6 + b7 + bs 0 I
1 b7 + b s 1 b 9 + b lO + b ll
2 b 6 ·b7 + bs 2 b lO + b ll
3 bs 3 b 9 • b lO + b ll
4 (b 6 + b 7) • bs 4 b ll
5 b7 • bs 5 (b 9 + b lO ) • b ll
6 b6 ·b7 ·bs 6 b lO . b Il
7 0 7 b9 ' b lO • b Il
8 0
Table 2-4: Boolean expressIOns/or the row decoder and the column decoder.

The row decoder is controlled by the output signals ofthe D-Iatches representing the bits b9 ,
b lO and bIt. Again, a truth table is used to illustrate the logic function of the row decoder
(table 2-5), the output signals of the decoder are indicated by in, with n E [0,8]. The simplified
expressions of the output signals are presented in table 2-4.

Input signals Output signals

btl bIO b9 is i, i6 is i4 iJ i:z it io
0 0 0 0 0 0 0 0 0 0 0 1
0 0 I 0 0 0 0 0 0 0 1 1
0 1 0 0 0 0 0 0 0 1 1 1
0 I I 0 0 0 0 0 1 1 I I
1 0 0 0 0 0 0 1 I 1 I 1
I 0 1 0 0 0 1 1 1 1 I 1
1 1 0 0 0 I 1 1 1 1 1 1
I I 1 0 1 1 1 I I I I 1
Table 2-5: Truth table o/the row decoder.

The output signals of the segment decoder indicated by Sq with q E [0,62] in figure 2-4 are
used as control signals. The state of a control signal Sq, determined by the values of the six
most significant bits, decides whether the corresponding segment current is switched to the
inverting or the non-inverting output of the DAC. The control signal Sq is generated by a local
cell decoder (figure 2-5). The input signals of the local cell decoder are generated by the row
and column decoder.

&

Figure 2-5: A local cell decoder.

The control signal Sq can be expressed as a Boolean function:

Sq = in '(jk +in+t ) (2.9)

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Note the differences in the signals used to control the cells in the top row, the bottom row and
the last column compared to the other cells in the matrix (figure 2-4). Because of these
differences the Boolean functions of the control signals Sq in these cells can be simplified. So,
the cells in figure 2-4, indicated with B, C, D and E, are able to generate their corresponding
control signal Sq with a Boolean expression that differs from equation (2.9). These simplified
expressions are presented in table 2-6.

Index Sq

A in' (ik + in+1)

B ik + in+ 1
C in . in+1
D in . ik
E in+ 1
Table 2-6: Boolean expressIOns for Sq.

All the Sq functions are realized with logic AND and OR gates. The schematics of these gates
are depicted in figure 2-6 and figure 2-7.
Vdd Vdd ~-------r--------,

A~-----'---+--l1 Z=A-B Z=A+B

B~----'---11

B ~-------'---II
A~---+------+-.....J

V. . .----------1.-------' V'" .-----'-------1.--------'

Figure 2-6: Logic AND gate. Figure 2-7: Logic OR gate.

In order to avoid glitches at the output signals ofthe segment decoder, some design criteria
have to be considered. The propagation delay times of all row decoder and all column decoder
output signals should be the same. Redundant AND and OR gates are required in the row
decoder and column decoder to obtain these equal propagation delays. Furthermore, notice
from figure 2-4 that a row decoder output is loaded with two local cell decoders, while a
column decoder output is loaded with just one local cell decoder. To compensate this
difference in capacitive load, the WIL-ratio of the row decoder output buffers is scaled up.
Finally, when the gates drive capacitive loads, rise time and fall time should be equal. For a
CMOS inverter this equality is obtained, if the WIL-ratio of the PMOS transistor is about 2.5
times the WIL-ratio of the NMOS transistor [14].

Furthermore, the available time to decode the binary code into a thermometer code is limited.
From section 2.1 is known that the propagation delay time of the segment decoder together
with the propagation delay time of the single-differential converter is limited to one half clock
period.

In appendix A are the complete schematics of the row decoder, the column decoder, the
segment decoder and the different AND and OR gates illustrated.

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2.5 Single-differential converter.

The single-ended output signals of the fine-part ofthe D-Iatches and the output signals of the
segment decoder have to be converted into differential signals. Single-differential converters
are implemented to generate these differential signals. In figure 2-8 a schematic is given of
this converter.

V dd • ....--,.---,----,-----r---,

V in ------1 TI 1 - - -__• vout

f----+----II~ V outnot

V ss . o - - - - - - - - - - . L - - - - - . . . I . . . - - - - L - - - J

Figure 2-8: Circuit ofa single-differential converter.

The gate of transistor T 2 is biased at a voltage equal to 1;2Vdd. A single-ended voltage V in is

applied to input terminal ofthis single-differential converter with a voltage swing equal to
V dd. The source followers are implemented as buffers in between the single-differential
converters and the master-slave latches (figure 2-1).

The propagation delay time of the single-differential converter is an important design

parameter. The time in which a binary code has to be decoded into a thermometer code plus
the time needed to generate a differential signal is limited to one half clock period.

A complete schematic of the single-differential converter is illustrated in appendix B. A

cascode stage is added in the current source circuits in order to reduce the output capacitance
ofthe current sources.

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2.6 Clock buffer.

A differential clock signal decides at which moment a new conversion takes place. In order to
activate all 69 master-slave latches a clock buffer is required. The clock buffer is indicated in
figure 2-1 in the block with single-differential converters. A schematic of the buffer is
depicted in figure 2-9.
V dd _~-,----...,..-----r------,------,

f - - -__• V out

t-----+-------I~ V oulnot

V .. _~ _ _-----'- ---'- --'--_---'

Figure 2-9: Circuit a/the clock buffer.

Notice that the circuit of the clock buffer is exactly the same as the circuit of the single-
differential described in the previous section. However, the design criteria of the clock buffer
are much more stringent.

First of all, the pulse-to-pulse time uncertainty of the differential output signal of the clock
buffer should be less than the maximum allowed sampling time uncertainty of 0.6ps (section
1.1.3). Furthermore, the source followers in the buffer have to drive a capacitive load of CL ~
100fF. This load capacitance CL limits the steepness of the falling edge of the output voltages
V out and VOUlnot by I/C L •

The complete schematic of the clock buffer is illustrated in appendix C.

Figure 2-10 shows a timing diagram of the clock buffer, depicted in appendix C, loaded with
a capacitance CL = 100fF.

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VN(VIN)
3.~
f--- r--- t-- r--f- ,.-
3.0

2.0

1.0

0.0
VN(YO(Jf)- VN(YOllTN$Om

200.0m

-200.0m

-600.0m
0.0 ~.On 1~.On 20.On
2.5n 7.Sn 12.~n 17.~n

T
Figure 2-10: Timing diagram ofa loaded clock buffer.

The rise and fall times of the differential output voltage Vod are not equal due to the
asymmetric driving of the clock buffer. From section 1.104 is known that the pulse-to-pulse
time uncertainty of the clock signal is caused by the noise of the buffer. To minimize this
jitter the steepest slope is chosen to activate the master-slave latches.

2.7 Master-slave latch.

All current switches are controlled by master-slave latches (figure 2-1). In this way all current
switches can be activated at the same time. This will prevent glitches due to different delays
in the preceding circuits.
The latches are implemented as master-slave latches. This means that after a sample is taken
at the beginning of a clock cycle, the sample is transferred to the output ofthe latch and is
held constant during one clock period. The differential voltage swing of both input and output
signals of the latch are 500mV.
The master-slave latch is a cascade of2 latches, with a master latch driving the slave latch.

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2.7.1 A basic CMOS latch.

In figure 2-11 a schematic is given of a basic CMOS latch.

Vdd • ..---,..---------------,

out-------l f-----~·outnot
f------.-----... ~___,__------l

in---1

Figure 2-11: A basic CMOS latch.

This circuit has a differential input voltage V id (Vid = Vin - Vinoot) and a differential output
voltage V od (Vod = V out - VOUlnoJ. The operation of the circuit can be explained as follows. When
the differential clock signal Vclkdif (Vclkdif = V clk - VclknoJ is high, the tail current IlaiI is switched
to the outer differential pair consisting of transistors T I and T 2 • The output signal will follow
the input signal and the latch is said to be in transparent-mode. When the clock changes
polarity the other differential pair, T 3 and T 4, is biased. The latch is now in hold-mode, the
output signal is kept constant and is independent of the input signal.

If a small DC-voltage V id is applied to the latch and the latch is switched from transparent- to
latch-mode at t = 0, the output voltage V od of the latch is determined by [6]:
AI-II

Vod=AO~de t" with A=gmR and r=RC (2.10)

From equation (2.10) is clear that the higher the differential input voltage V id , at t = 0, the
faster the latch settles. The time constant t is measured at the output pins of the latch. Ao and
Al are respectively the gain of the outer and the inner differential pairs and are identical in the
latch depicted in figure 2-11. The growth factor (A I -l)/t determines the speed ofthe latch.
With R = (Vdd - VouJ/I taih gm = ..J(2·J3·W/I..,IlaiI12) and capacitance C considered constant, the
growth factor becomes equal to:

AI-I_g. I
- - - - - - - = -=---=---
~P~I"" (2.11 )
r C RC C (Vtid - V01ll)C
The optimal tail current Itail,opt biases the latch at maximum speed, at this bias point the growth
factor reaches its highest value. Itai~oPl can be derived from equation (2.11):
flW 2
flail,opt = 4L(Vtid - VOUI ) (2.12)

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In the analyses above side effects such as channel length modulation and body effect are
ignored. These effects will cause, especially for small devices, a difference between
calculated values and simulated values of the optimal tail current and the corresponding
maximum growth factor.

The optimal tail current Itai~oPI is calculated by inserting the values of V dd - Voul> WILand into
equation (2.12): Itai~oPI= 19 ~. The total capacitance C present at the output of the latch is
determined with MOSCA:

C = Cdb2 +Cdb4 + C gs3 = 2.8/ + 2.8/ + 004/ = 6jF (2.13)

With C = 6fF the maximum growth factor (A I-l)/t is calculated, «A I-l)lt)max = 6.3.109 S·I.

To verify these calculations the circuit depicted in figure 2-11, with a DC input voltage V id of
10pV, is simulated for different values ofI tail . The growth factor as a function of the tail
current can be derived from the simulated differential output voltage of the latch. Rewriting
equation (2.10) results in:

A, -1 1 dVod A -1
--=--- with Vad = Ao~d exp(_I- t) (2.14)
r Vad dt r
The simulated growth factor as a function of the tail current of the latch depicted in figure 2-
11, indicated as latchi, is plotted in figure 2-12.
- yl-axis - 16.00 -i(L=IN::..:.:....)_--.--_ _-,-- ..,.-_ _..,.-_ _-,-_ _.. ....--_-.,
lalchl
1ateb2 14.00
.......
lalch3 '.",
12.0G
1ateb4

10.OG

8.0G

6.00

4.0G irx
2.0G

0.0

-2.00
0.0 SO.Ou IOO.Ou lS0.Ou 200.Ou
25.Ou 75.Ou 125.0u 17S.Ou
(LIN) [tail
Figure 2-12: Growthfactor as afunction ofthe tail currentfor different latch configurations.

From figure 2-12 is clear that latchi biased with a tail current of 16~ operates at maximum
speed, the corresponding growth factor equals 5.7,109 S·I. The difference between simulation
results and the theoretical calculations are caused by the earlier mentioned side effects.

The gain Ao of the outer differential transistor pair can also be evolved from the simulation.
Rewriting equation (2.10) results in:

In(Vad )
A -1
= 1n(AoV;d) + _1_ (2.15)
t
r

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Figure 2-13 shows a plot ofln(Vad) as a function of time, for the latch operating at maximum
speed (Itail = ltai1,opt = 16J.1A).

- yl·axis· (L'N)
0.0
In(VOD)
/-
- Subvar· ·5.0
ITAIL: 16.0u

-10.0
/
-15.0
/
·20.0
/
-25.0 /
-30.0
0.0 4.00 8.0n
2.On 6.On 10.00
(LIN) T
Figure 2-13: A plot o/ln(Va<iJ as a/unction o/time.

With an initial value of the curve In(V ad) equal to In(AoV id) = -24.8 and a differential input
voltage of 10pV, the gain AD is calculated, Ao = 1.7. The gain of the inner differential
transistor pair AI equals AD, because both differential pairs are identical. The slope of the
curve is, as expected, equal to the growth factor, (A I -l)!'t = 5.7'109 s·'.
Finally, the output capacitance C can be derived from the simulation. Rearranging equation
(2.11), the output capacitance C can be expressed as:

C = AI -I (2.16)
R
Inserting Al = 1.7 and R = (V dd - Vout)lItail,opt = 3 I kn gives C = 4fF.

These simulation results confinn the accuracy of the calculations made before.

2.7.2 Improving the CMOS latch.

The growth factor of the latch, expressed in equation (2.11), can be rewritten as a function of
the transistor dimensions. Noticing C - WL, the growth factor becomes:

A,-I A B
=-== (2.17)
L.JWL WL
with A and B arbitrary constants.

The channel length L is kept at 0.35~m in order to obtain a high frequency perfonnance. Thus
an increase of the W/L-ratio is realized by increasing width W at a constant length L.

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According to equation (2.17) increasing the WIL-ratio results in a decrease of the growth
factor, while according to equation (2.12) the optimal tail current is increased. With a higher
optimal tail current the growth factor can be increased at cost of more power dissipation. The
curve in figure 2-12, indicated with latch2, gives an impression of the growth factor versus
the tail current of the latch with transistors with a WIL-ratio of 5/0.35.

Another way to improve the speed performance ofthe latch is to increase the gain of the inner
differential pair by additional drain resistors in between the output nodes and the drain
terminals ofthe inner transistor pair. This is shown in figure 2-14, the transistors have the
same dimensions as in figure 2-11.

V dd -~--..--------------,

out..-I---J I----~outnot
~"""'C:::::J---1

in~ ~innot

Figure 2-14; A CMOS latch with additional drain resistors.

The RC-time 't present at the output nodes ofthe latch is determined by approximately the
same parasitic capacitances, but the resistance is doubled compared with the latch in figure 2-
11. According to equation (2.11) an increase of the resistance R results in a higher growth
factor. Figure 2-12 shows a plot of the growth factor versus the tail current, indicated with
latch3, of the latch depicted in figure 2-14. A major increase of speed is obtained. A
disadvantage of this circuit is the extra voltage swing over the supplemental drain resistors.
Because of this extra voltage swing and the low supply voltage, the transistors used in the
current source Itai ( are biased in the triode region in stead of the saturation region. So, the latch
depicted in figure 2-14 cannot be implemented in the master-slave latch.

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The differential input signal V id, the differential clock signal Velk and the differential output
signal V ad of the basic CMOS latch (figure 2-11) are plotted in figure 2-15.
Vid
6OO.0m

200.Om

-200.0m

-600.0m
Veil<

Vod
~:~
6OO.0m

200.0m

-200.0m

-600.0m
0.0 IO.On 20.0n 30.0n 40.On
S.On IS.On 2S.On H.On
T

Figure 2-15: Timing diagram ofthe basic CMOS latch.

When the clock signal is high the latch is in transparent-mode. When the clock changes
polarity the output signal of the latch is kept constant, the latch is now in hold-mode.
The large spikes superimposed at the differential output voltage of the latch are generated at
each clock transition. The small spikes are generated at transitions of the differential input
voltage and are negligible compared with the large spikes. The spikes are fed through the
DAC and will cause a distortion of the analog output signal of the DAC. A reduction of the
clock feedthrough can be obtained by reducing the differential voltage swing of the clock
signal.

As mentioned before a master-slave latch is a cascade of 2 latches, with the master latch
driving the slave latch. During a clock transition the charge stored in the gate-source
capacitance of the input transistors in the slave latch might kick back into the master, causing
the master to take a wrong decision. To prevent this from happening source followers are
added. The charge stored in the gate-source capacitance is now properly discharged and the
source follower is acting as a buffer. A schematic of this configuration is plotted in figure 2-
16.

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Vdd _~--r-----,.--....------,

out.-l---1 l----·outnot
II-r---

~innot

,p

Figure 2-16: A CMOS latch with source followers.

The price that has to be paid is twofold. First, the power consumption of the latch is almost
doubled. Furthermore, the overall gain of this configuration is reduced by a factor equal to the
gain of a source follower ASF (ASF == 0.85 [2]). A reduced gain results in a decrease of the
growth factor and causes the latch to slowdown.
If the output capacitance C of the latch is considered unchanged, the growth factor becomes
equal to:

A,·ASF -1 = 1.7·0,85-1 =3.6.10 9 s-' (2.18)

r 31k·4j
with ASF the gain of a source follower. The parameters A, and't are derived from simulation
results of the basic CMOS latch discussed in section 2.7.1. The growth factor is reduced with
36% compared to the basic CMOS latch (figure 2-11). Figure 2-12 shows a plot of the
simulated growth factor versus the tail current, indicated with latch4, for the latch depicted in
figure 2-16. Observing the curve latch4 confirms the calculated reduction of the growth factor
of36%.

Nevertheless, the possibility of making wrong decisions is considered more important than
speed and power dissipation. So, a latch with source followers is used to construct a master-
slave latch.

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2.7.3 The master-slave latch.

In figure 2-17 a schematic ofthe master-slave latch is shown. Notice that the master is
activated by Vclkdif, while the slave is activated by an inverted fonn OfVclkdif.

Master latch \ Slave latch

V dd _..-------,,-------,--.-------.----+--\---.--------,,-----.-------,--

Qut-I-+----.-H 1h------1~~ outnot

\
~inn~t 1
I

\\
+1 \
V. . ...-----------'-------L.----'---T---------l----------'-----'

Figure 2-17: A CMOS master-slave latch.

The operation of the master-slave latch is best explained with the aid of a timing diagram
(figure 2-18).

Vid
6OO.0m

200.Om

-200.0m

-600.Om
Velk.
6OO.Om

200.Om

-200.0m

-600.0m
Vod
6OO.0m

200.0m

-200.0m

-600.0m
0.0 20.00 40.00 60.00
10.00 30.00 50.00
T

Figure 2-18: Timing diagram ofthe master-slave latch.

©Philips Electronics N.V. 1997 45

When a differential input signal V id is applied to the input terminals in and innot and Vclkdif is
low, the master will be in latch-mode and the slave in transparent-mode. Hence the slave
freezes the output signal of the master. If the clock signal changes polarity the state of the
master is transferred to the slave. The master is now in transparent-mode while the slave is
holding a sample. Thus, one sample per clock period is produced.

A complete circuit schematic is shown in appendix D.

2.8 Buffer.
To reduce the clock feedthrough a buffer is added in between the master-slave latch and the
current switch (figure 2-1). In figure 2-19 a schematic is given of the buffer. The buffer
consists of a differential pair of transistors and two source foIlowers.

Vdd -~-...,------...,--------,.----,

1--- V oul

V innOI _~-+---I------' 1---+----1. V ouIDol

~I
V _~ _ _----l ----l_---'
ss

Figure 2-19: A buffer.

In the next section it will be discussed that the dimensions of a switch transistor are scaled up
with the current that has to be switched. This means that the source foIlowers are loaded with
different capacitive loads, causing inadmissible timing differences (see section 1.1.2). To
compensate the difference in the load capacitances, the quotient lie is kept constant for all
buffer stages.

Moreover, the mismatch of the used transistors and resistors causes undesired timing errors.
In the following analysis the mismatch of the transistors and the resistors in the differential
pair are evaluated. The circuit of the differential pair is depicted in figure 2-20. The effect of
all component mismatches within the differential pair are referred to the input. The input
offset voltage Vos is defined as that differential input voltage that is required to make the
differential output voltage of the differential pair exactly zero. This requires that ~I'RI =
Id2 ·R2• As illustrated in figure 2-20, the transfer function of the differential pair is shifted with
a voltage Vos along the horizontal axis.

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11----4
•• innot

vss _.-------'
Figure 2-20: Modelfor calculation ofthe sampling time uncertainty caused by matching errors.

The input offset voltage Vos is derived in [2]:

V = LlV + Vgt (_ M -
os I 2 R
LlPPJ (2.19)

Because in this application V gt is low, the contributions of the 13-spread and R-spread can be
neglected. Therefore the variance of the offset voltage becomes approximately equal to the
variance of the VI-spread.

The time uncertainty caused by the matching errors of the transistors and the resistors is
related with the slope of the differential output voltage Sod. Sod is calculated using the
defmition of the rise time tr described in section 1.1.8:
_ 0.8· Voo
S00- (2.20)
IT
Generally, in amplifier systems is the rise time t r related with the RC-time by:

(2.21)

Expressing C as a function of the transistor area WL:

C=C'·WL (2.22)

and knowing that the differential output voltage V od is kept constant:

V00 = I . R = constant (2.23)

the slope Sod can be expressed as a function of the tail current I and the transistor area WL:

s = 0.8 . I (2.24)
00 2.2 C'. WL

As will be discussed in the next section, the differential input voltage Vid,sal that is required to
just tum off one transistor in the differential pair is related with the quotient I/W:

V
id,SQI -
_~21 _ ~
k - V/iW7L (2.25)

and is for a certain application kept constant.

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Inserting equation (2.25) into equation (2.24), the slope Sod can be expressed as a function of
Land Vid,sat:

(2.26)

Finally, the sampling time uncertainty due to matching errors of the transistors in the
differential pair is determined by the quotient of the offset voltage Vas' equation (2.19), and
the slope Sad, equation (2.26). The standard deviation of the sampling time uncertainty (j(~t)
becomes:

L2 1
cr(ilt) ~ - - . - 2- (2.27)
.JWL V;d,sa/

Note that for a optimal time uncertainty performance the gate length L should be at minimum
size, while the gate width W should be as high as possible. However, from equation (2.25) is
clear that increasing W and keeping Vid,sat constant, a linearly proportional increase of the
power consumption is required.

By simulation it is determined that the maximum allowable sampling time uncertainty

demand can not be satisfied. For example: a differential pair of transistors with a WIL-ratio of
4/0.35 and a tail current of 40~ has a standard deviation ofthe sampling time uncertainty
(j(~t) equal to 1.5ps.

The complete schematics of the different buffer stages are depicted in appendix E.

2.9 Current switch.

The switching block depicted in figure 2-1 has to switch 63 segment currents and 6 binary
weighted currents. A basic circuit implementation of a current switch is depicted in figure 2-
21. The tail current I is generated by a current source that will be discussed in the next
section.

out outnot

- .......
- innot

__. . l.1~1
V ss_..-----'
Figure 2-21: A basic current switch and the corresponding transfer characteristic.

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If the influence of channel length modulation and body-effect are ignored and both transistors
T. and T2 are assumed identical, the difference in drain currents of these transistors can be
calculated [3]:

-1

.!.k. V. ~41 _ V. 2 (2.28)

2 kId id

+1

with V id the differential input voltage, V id = Yin - V innot and k = p·WIL.

When a large DC differential input voltage V id is applied, all of the tail current I is switched to
the inverting or the non-inverting output. The transfer characteristic of the differential pair is
plotted in figure 2-21. Note that for a differential pair of MOSTs, the range OfV id for which
both devices conduct current is a function of device dimensions and tail current. The
differential input voltage Vid,sat required to just tum off one of the transistors is equal to [2]:

V;d,sal = ~2: = j2. Vgt (2.29)

The WIL-ratio of the transistors switching the LSB current is 0.5/0.35 and is scaled up by
factors of2. A segment current equals 64 times a LSB current, resulting in a WIL-ratio of the
corresponding switch transistors equal to 32/0.35. To obtain a 12-bit accuracy the driving
voltage swing for the current switches has to be 500mV.

In order to avoid glitches the sum of the drain currents through T I and T2 should be kept
constant, even during switching. In figure 2-22a the drain currents are depicted as a function
of time. The rise and fall times of the drain currents through T 1 and T 2 are equal. The dashed
line represents the sum of both drain currents.
I[Alt 1lAlt v, IV) t

I", I",

llsl- llsl- lls)-

(a) (b) (c)

Figure 2-22: Drain currents a/transistors T} and Tz during swifching.

From figure 2-22a is it clear that even during switching the sum of the drain currents is equal
to the tail current, this results in a glitch free output current. Figure 2-22b shows a situation
for which the fall and rise times of the drain currents are not the same. The sum of the drain
currents shows a deviation of AI compared to the tail current I. The deviation AI is generated
by discharging the capacitance Cp at the common-source node. The capacitance Cp consists of
one gate-source capacitance C gs (Cgs 1 or Cgs2 depending on the state of the switch), two
source-bulk junction capacitances (C sb1 and Csb2) and the output capacitance of the current
source. Due to the current deviation AI, the voltage at the common-source node will show a

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brief drop ilVs (figure 2-22c). The relation between the voltage drop and the current error is
given by:

M =C ilVs (2.30)
p /).1

So, to minimize the glitch error capacitance Cp should be as smaIl as possible. The output
capacitance of the current source is reduced by adding a cascode stage.

A problem that is not yet discussed is the charge feedthrough of a switch transistor. A
transistor contains channel charge when it is conducting current. If such a transistor is
switched on, the charge has to be applied and is injected back into the signal path when the
transistor is switched off. This is called charge feedthrough. As mentioned in section 2.7
feedthrough causes spikes on the differential output voltage of the DAC. Feedthrough can be
compensated for by implementing half-sized dummy transistors at both ends of the main
switch transistor. The dummy switches are driven by an inverted control signal with respect to
the main switch. This compensation technique only works well with fast switching and good
matching [1][5]. Because the dummy transistors have different gate width, the matching
might be a problem. Implementing dummy transistors the feedthrough is significantly reduced
and possible matching problems are therefore taken for granted.

The different bit and segment current switches are illustrated in appendix F.

2.10 Current sources.

The ideal architecture to realize a 12-bit high-specified DAC is determined in section 1.2. The
DAC is based on a coarse-fine architecture. The 6 LSBs control 6 binary weighted current
sources. The remaining 6 MSBs are decoded into a thermometer code which controls 26_1 =
63 segment current sources.
Every kth bit current is constructed by means of 2k parallel unity current sources. A segment
current source is constructed by 26 = 64 paraIlel unity current sources. An unity current source
should be designed with a relative accuracy of at least 2.9% (section 1.2.3). The unity current
value 10 is calculated by dividing the required full-scale output current value IFs = 20mA by
the number of quantization steps 4095, resulting in 10 = 5J.LA.
The configuration in figure 2-23 is used to generate the bit currents and segment currents. The
cascode stage is added to reduce the influence of the output capacitance of the current
sources. The WIL-ratio ofthe transistor used for cascoding is scaled up by factors 2 from
0.5/0.35 for one unity current to 32/0.35 for one segment current.

1~---4I-----------4I---------------------1~-------------------------- -----1~II::'
64x -1
Vss_~-'------_----J'--_---1_...l- _ _....L..----l_--l.-_.L..-.. ...l- ---'

Figure 2-23: Circuit ofthe cascoded bit and segment current sources.

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An unity current generating transistor needs a minimum area WL to obtain a certain current
mismatch. lbis area can be derived by isolating WL from equation (2.5) after substitution of
equations (2.3) and (2.4):

Z2 +2X·Y+Z~Z2 +4x·y
WL exact = 2 (2.31)
2x
with:

(2.32)

(2.33)

z = 2A(ft)B(P) (2.34)

The complicated equation (2.31) can be simplified for small Vgt. In that case the contribution
of the p-spread can be neglected, the minimum required transistor area WL can now be
approximated by:

(2.35)

Figure 2-24 shows a plot of the approximated required transistor area as a function of Vgt for
an allowed current mismatch of2.9%.

\V L. ppro. 10 _ _ _ .
[J.1II11] 9 +----------------------1
8 +'<--\---------------------l
7 +-"\-------------------1
6 +-----'.-\------------------1
5 + - -......\ - - - - - - - - - - - - - - - - - - - - i
4 +------->c-""'-----------------1
3 +-------""""~=-----------------I
2+--------=-....:::---------------J

~ t=====----==::::=~=:;:::~
0.2 0.3 0.4 0.5 0.6 0.7 0.8 1
Vet [V]

Figure 2-24: Characteristic ofthe transistor area WL versus Vgt for different matching demands.

High Vgt results in a smaller transistor area and therefore in a reduction ofthe current source
output capacitance. The maximum Vgt is limited by the number of cascoded transistors; Vgt.max
= O.3V. As mentioned before the current mismatch should be less than 2.9%, resulting in a
transistor area of25~2.
The WIL-ratio ofa transistor used in a unity current source with Id = 5J.1A, Vgt= O.3V and WL
== 25~2 can now be calculated.

©Philips Electronics N. V. 1997 51

--Company restricted

The schematics of the current sources are illustrated in appendix G.

To eliminate long distance gradients in oxide thickness and doping implementations the
transistors of the current sources will be randomized over the layout. TIlls will be discussed in
chapter 4.

2.11 The output circuit of the DAC.

In low-frequency circuits, the IC package is of no influence on the behavior ofthe circuit. But
for high frequency systems, such as a DAC with a clock frequency of 250MHz, the influence
ofthe package cannot be ignored.

The IC package is modeled to analyze its influence on the performance of the DAC. A
frequently used model is shown in figure 2-25. TIlls model also includes the parasitic
components ofthe bonding pad and the parasitic components ofthe interconnect between the
DAC output and the bonding pad.

I
,, I

I
V out
I
I
I

tI !
DAC
I
I

Interconnect : Bonding IC package

pad
Figure 2-25: A model ofthe output circuit ofthe DAC.

R is the ohmic resistance ofthe interconnection in between the output of the DAC and the
bonding pad and is determined by the width and the length of the interconnection. The
capacitance Ci is determined by the area ofthe interconnection. Rand C j are estimated to 8.0
and 45fF respectively.
The capacitance ofthe bonding pad Cb is according to the C75 Blue Book [7] equal to 0.2pF.
~ is the substrate and contact resistance and has value of approximately 5.0.
The IC package is characterized by L w the inductance ofthe bonding wire and the lead frame,
Rw the ohmic resistance ofthe wire and Cpthe package capacitance. The component values
depend on the chosen package. For high-frequency applications the packages have to be small
in order to minimize L w and Cpo These high-frequency packages are often square in order to
keep the parasitic properties of each pin the same. The package which is chosen for the DAC
is type SOT255A5, 28 pins Leadless Ceramic Chip Carrier (LCCC28). The wire inductance
Lw, the package capacitance Cp and the ohmic resistance ofthe wire Rw for this package are
equal to 7nH, 1.7pF and 0.2.0 respectively.
Rr. is the external load resistor of 50.0.
A survey of all component values is given in table 2-7.

52 ©Philips Electronics N.V. 1997

 Company restricted

;,
;';COlllpo;~~~t:::~~~fiptions Values
Interconnect resistance Rt 80
Interconnect capacitance Cj 45fF
Substrate resistance ~ 50
Bonding pad capacitance Cb 0.2pF
Wire inductance Lw 7nH
Wire resistance Rw 0.20
Package capacitance Cn 1.7pF
Extemalload resistance RL 500
Output capacitance of the DAC Co 2.6pF
Table 2-7: OvervIew ofoutput component values.

In order to perform some hand calculations the model depicted in figure 2-25 has been
simplified. Observing all component values in table 2-7 is concluded that only the package
components Cp and Lw have a noticeable effect on the output signal of the DAC. The
simplified model is depicted in figure 2-26.

Figure 2-26: A simplified model ofthe output circuit ofthe DAC.

The step response of the simplified model can be derived from the transfer function:

' ) - Vaut _
H( jm RL (2.36)
----
I DAC (jm)2 Yz.LwC p + jm RLCp +1
Generally, the transfer function of a second-order system can be written as:

(2.37)

where the parameter l; is the damping ratio and ron is the undamped natural frequency [15].

Comparing equations (2.36) and (2.37) expressions can be found for the damping ratio l; and
the undamped natural frequency ron:

r-RC~
~ -2L CL p
w p
(2.38)

(2.39)

With the component values from table 2-7 the damping ratio and the undamped natural
frequency are calculated, l; = 0.55 and ron = 13.109 rad/s.

©Philips Electronics N.V. 1997 53

Company restricted

The system is critically damped when the damping ratio is equal to Y2"'2. The calculated
damping ratio is smaller than 1h"'2, hence the step response of the system will show
overshoot. Damping the system can be obtained by taking two pins together, resulting in a
doubling of the package capacity and halving ofthe wire inductance. The damping ratio will
be twice as high, ~ = 1.10. The system is overdamped and an increased settling time is
detected. Figure 2-27 shows the step response of the complete package model (figure 2-25).

- yl-axis - 250.0m
I pin

~p~~------
.~l!~._._._ ...._
0.0 Af\
r .<,"V.:V--\J
1\./\ t\ .f\.
\j
f\ f\ f\ 1'\
V \/ v v v v
~
V " "

. .......
I :-.:

• Subvar· ... ,'

-250.0m
RD: IOO.Om I

·: ,'-'

-500.Om ·'t··
:
:
:

-7S0.0m

-1.0 'J

-1.25
5.00 7.00 9.0n
6.0n 8.On

Figure 2-27: The step response ofthe complete output circuit. T

As expected, damping of the step response is obtained by taking two or more pins together at
the expense of the settling time. Taking two pins together seems to be the best choice.

A problem that is not yet discussed is the output capacitance Co of the DAC. Capacitance Co
in combination with the IC package of the DAC will cause a ringing in the step response. To
reduce the ringing damping resistors can be added in between the drain tenninals of the
switches and the load resistor R L • This is shown in figure 2-28.
'I. L w 'I. L w
r - - - - - - - - - r - - - - r - - - - - t - - - - - r - - - - ; - - - - - r - - - - - r - - - - - - I T1' ".,,-f TT '----,-- ~v00'

63 x
-------------

L..- - J -_ _-L-_---'_ _---'-_ _...L-_ _'--,...----'- ---..-J'---_ _---'--~v ..

Figure 2-28: A simplified output circuit ofthe DAC with extra damping resistors.

The output capacitance of each switch depends on the weight of the current that has to be
switched. The output capacitances ofthe least significant current switch and the segment
current switch is equal to Cs and 64C s respectively. The output capacitance of the DAC Co is
detennined by the sum of all capacitances Cs, Co = 4095C s = 2.6pF and Cs = O.6fF.
For an accurate operation of the switches, the voltage at the drain tenninal of every switch
must be equal. Therefore, the voltage drop across every damping resistor should be the same.
The damping resistors are scaled down from RJ for the LSB current switch to RJ64 for the
segment current switch. When a switch is turned ON, the corresponding transistor is in

54 ©Philips Electronics N.V. 1997

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saturation. In order to keep the transistor in saturation, the voltage drop across the damping
resistors is limited to 0.5V. Thus, the maximum allowable damping resistor ~max becomes
~,max 0.5V/5JJA = 100kn.

Note that the output impedance of each current source is equal. Figure 2-29 shows the output
circuit of a segment current source.
Yo L w Yo L w
r-----,---------'" ll"YY\_--._~vout

IV4031

4031C.
L...-_ _----L_..--- ----L '-I. .v..

Figure 2-29: A simplified output circuit ofa segment current source.

The step response of the output circuit of the segment current is presented in figure 2-30 as a
function of the damping resistor ~.

- y (-axis - loo.Om
VOUl

- Subvar-
RD: IO.Om
2
-loo.Om
y.. .//
.-
~.- ...--

RD: IO.Ok -3oo.0m

3
RD: lOO.Ok
-5oo.0m
0"-
-7oo.0m II
·9oo.0m fJ
-1.1
5.On 7.~ 9.On
6.On 8.On

Figure 2-30: Step response ofthe segment current as afunction ofthe damping resistm. T

From figure 2-30 is clear that adding a damping resistor is only effective in decreasing the
ringing when the resistance is large.

As mentioned before the output impedance of the each current source in figure 2-28 is
assumed to be equal. This means that each current source shows the same step response. This
assumption is not completely justifiable. In a practical situation the resistors are processed
with a certain inaccuracy. Moreover, the output capacitances of the least significant current
switches are not linear with the transistor area. For small transistors the influence of the
overlap capacitance cancels the linear relation between output capacitance and transistor area.
Both effects result in differences in the output impedance of each current source. This implies
that the step responses of each current are not equal anymore
With MOSCA is determined that the output capacitance of the 3 least significant current
switches are almost identical. The output circuit in figure 2-28 with the adapted output

©Philips Electronics N.V. 1997 55

Company restricted

capacitances and a damping resistor of 100kO is simulated. The simulated difference in delay
time between the step response of the least significant current and the segment current is
equal to 200ps. The maximum allowable sampling time uncertainty of 0.6ps (section 1.1.2) is
exceeded.

Furthermore, due to the low sheet resistance in CMOS a large area is required to make a
100kO resistor. The corresponding parasitic capacitance is large and causes a reduction of the
bandwidth. Again, the settling time is further increased.

Thus the damping resistor causes a small decrease of the ringing, but has the disadvantage of
an increased settling time. Besides the increased settling time is also a large sampling time
uncertainty introduced. All aspects considered is concluded to leave out the damping resistors,
in order to avoid further degradation of the performance of the DAC.

2.12 Reference current sources.

In the circuit implementation of the DAC, different kind of reference current sources are
required. In table 2-8 a survey is given. All these currents are derived from one fixed input
reference current by means of basic current mirrors.

Circuits Current Number of Total current

fJJAl circuits [mA]
Clock buffer 1700 1 1.7
Master-slave latch 300 69 20.7
Single-differential 120 69 8.3
converter
Buffers bo, bI. b2 , 70 3 0.2
Buffers b3 80 1 0.1
Buffers b4 90 1 0.1
Buffers bs 120 1 0.1
Buffers So 180 63 11.0
Current sources 5 4095 20.0
Table 2-8: Survey ofthe required current sources.

From table 2-8 the total power dissipation can be calculated, 200mW. The power dissipation
of the digital segment decoder and input circuitry are omitted, because it depends on the
frequency of the input signal. Note, that almost one half of the total power is dissipated in the
external load resistors.

56 ©Philips Electronics N.V. 1997

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Chapter 3 Simulations.
In chapter 2 the circuit implementation of the different building blocks of the DAC is
discussed. In this chapter some simulations of the complete DAC are presented. Due to the
complexity of the circuit, specifications such as S/(N+TlID) and THD are impossible to
determine by simulation. Measurements oftest chips are needed to determine these
specifications.

3.1 Glitch energy.

In the coarse-fine DAC a major glitch is generated at the moment when all binary weighted
LSBs together with one segment change state. The single-ended output voltage of such a
transition is depicted in figure 3-1.

VN(VONOn
3.255

3.254
f\

3.253 I\
3.252
/
/ \ \
3.251 '~
3.25 1\ /
3.249 \ /\.../
3.248
10 .On 12.0n 14.On
II.On I3.On 15.On
T
Figure 3- J: Major glitch at the single-ended output voltage.

The glitch energy is calculated with equation (1.6), Eglitch = 2.5pVs. Unfortunately, this is not
sufficient to obtain a glitch energy smaller than the energy of one LSB.

3.2 Switching characterization.

The switching characteristics of the converter are derived from a full-scale step response of
the DAC. The DAC will generate a 2V pp differential output voltage.

The transient behavior of the step response is characterized by the delay time 41, the
propagation delay time tpD, the settling time ts and the fall time tr or the rise time tr. The
definitions of these switching characteristics are illustrated in section 1.1.8.

Figure 3-2 shows the full-scale data change at the output of the converter.

©Philips Electronics N.V. 1997 57

 Company restricted

- yl·axis·
VOD

\.0

JOO.Om
/
0.0

·jOO.Om

•\.0
) I

4.On S.On 12.0n 16.0n 20.0n

6.On 10.On 14.On 18.0n

T
Figure 3-2: Full-scale differential output swing a/the DAC.

The propagation delay time tpD is caused by the delays of the buffers, the current switches and
the delay of one half sampling period of the segment decoder, tPD = 2.4ns. The settling time ts
of the DAC to a 10-bit (!) accuracy equals 1.8ns. The delay time t.J and the rise time tr are
equal to 3ns and 1ns respectively.

The settling time is mainly determined by the output capacitance at the drain terminals of the
current switches in combination with the IC package. Further, due to the clock feedthrough
the settling time is determined for a 1O-bit accuracy.

58 ©Philips Electronics N.V. 1997

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Chapter 4 Layout.

The performance of the DAC is not only determined by the circuit implementation. Especially
in CMOS technology is the layout arrangement of the DAC of great importance. Correlated
matching properties like doping gradients and oxide thickness gradients can devaluate the
performance of the DAC. These effects can be eliminated by choosing an optimal distribution
of the devices on chip.
From section 1.2 is known that 63 segment current sources have to be generated. Each
segment current consists of 64 unity current sources. In order to cancel the effects of the
earlier mentioned process gradients, the 4095 unity current sources are uniformly distributed
in a 7x9 matrix. 9 sub-matrices

[][][][][][][][][]
[][] [][][][]] [][][]
[][][][J[J[][][][J
[][][][][][][][][]
[J[][J[J[J[][][][]
[][J[J[J[][][][J[]
[][][][][] [J[][][]
Figure 4-1: A 9x7 matrix with 4095 uniformly distributed unity current sources.

The matrix, depicted in figure 4-1, is divided into 63 sub-matrices. A sub-matrix is a 8x8
matrix containing one unity current source of each segment current source. A sub-matrix is
depicted in figure 4-2. 8 unity current sources
.. ~

00
§
~.

n
s::
~
a
VJ
o
..,
s::
;:lfll:~II~:II:~:II:~lr:II::II:: R
VJ

illilllillil!lll.li.ill!.
:'_':11':11:'11':'11-:11:'11"11"
~1:::.:.: 1~:::::::: 1~:::::::1~:.:.:.: i:~:::.:::~::::: -:. ~~:::::::; 1~:::.:.:~:
Figure 4-2: A 8x8 sub-matrix with 64 unity current sources.

©Philips Electronics N.V. 1997 59

The binary weighted current sources also consists of unity current sources. The distribution of
these unity current sources across the matrix area is exemplified by figure 4-3.

D~D~D~DII Db s (32x)

~D~D~D~D ~b4 ( 16x)

D~D~D~D~ ~bJ (8x)

~DI§§]D~DITlIIIlD ~b2 (4x)

D~DIID~D~ lIIIIIl b l (2x)

[[ill]D~D~D~D II bo (2x)

DrnD~D~D[Ij
~D~D~D~D
Figure 4-3: A 8x8 matrix filled with the unity current sources ofthe binary weighted current sources.

Again, the unity current sources are distributed uniformly in order eliminate the process
gradients. To place all 4095 unity current sources a die area of2 x 1 mm2 is required.

The same reasoning holds for the current switches. Every current switch is constructed by
means of a number of parallel unity current switches, but are uniformly distributed in an array
rather than in a matrix. In all other critical parts of the layout same kind off averaging
techniques are used. The overall die area is approximately 5 x 2 mm 2•

Furthermore, when signals lines and sampling clock lines have different lengths on the die,
timing errors are introduced between the same signal at different places. These timing errors
causes distortion. Therefore, the interconnections between the different circuit blocks (figure
2-1) have to be laid out very carefully.

60 ©Philips Electronics N.V. 1997

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Chapter 5 Conclusions.
The circuit implementation and the layout of a 12-bit DAC with a conversion rate of250
MSPS has been presented. The DAC is implemented in C75, a 0.35J.lm, five layer metal
CMOS technology.

In low-voltage applications is the matching perfonnance in C75 CMOS technology superior

compared to its predecessor C100. Moreover, a higher transition frequency is obtained in
C75.

The architecture of the DAC is detennined based on calculations of sampling time

uncertainties and DNL. The DAC is based on a coarse-fine architecture with 6 MSBs (Most
Significant Bits) and 6 LSBs (Least Significant Bits) driving the coarse part and the fine part
respectively. A segment decoder is used to decode the binary coded MSBs into a thennometer
code. Master-slave latches are implemented to synchronize the encoded MSB signals with the
binary coded LSB signals.

All generated bit and segment currents are made up by a number of unity currents. The
minimum accuracy of one unity current to obtain a DNL smaller than ± 1 LSB is calculated.
This accuracy sets a demand for the area of the transistor used to generate one unity current.

The sampling time uncertainty demand of 0.6ps can not be satisfied. Due to the mismatching
of a differential pair of transistors a sampling time uncertainty is introduced equal to 1.5ps.

Correlated matching properties like doping gradients and oxide thickness gradients can
devaluate the perfonnance of the DAC. A special layout arrangement is developed in order to
cancel these gradients. Furthennore, the interconnections between the different building
blocks have to be laid out very carefully in order to prevent signal delays on chip.

Finally, it can be concluded that the perfonnance of the DAC is limited by the mismatching of
the CMOS transistors. Mismatching introduces sampling time uncertainties and increases
DNL and INL.

All results mentioned before are obtained by means of simulations and analytical reasoning.
Measurements of test chips have to confinn the correctness of these results.

©Philips Electronics N.V. 1997 61

Company restricted

References
[1] RJ. van de Plassche,
Integrated analog-to-digital and digital-to-analog converters,
first edition, Academic Publishers
Boston, 1994

[2] P.R. Gray and R.G. Meyer,

Analysis and design of analog integrated circuits,
third edition, John Wiley & Sons,
New York, 1993

[3] R.F. Wassenaar en B. Nauta

Analoge CMOS schakelingen
Versie 1.2, Chiptronix Consultancy
Alemelo, januari 1991

[4] M. Pelgrom et. al.

Matching properties ofMOS transistors,
IEEE Journal of solid-state circuits, vol. 24, no. 5, October 1989

[5] GJ.G.M. Geelen

Clockfeedthrough in switched-capacitor circuits.
Nat. Lab. Technical Note Nr. 240/86

[6] HJ.M Veendrick

The behavior of flip-flops used as synchronizers and prediction oftheir failure rate,
IEEE Journal of solid-state circuits, vol. Sc-15, no. 2, April 1980

[7] C075FM Blue Book

Philips Semiconductors Nijmegen
Version 1.02, February 1997

[8] CI00TM Blue Book

Philips Semiconductors Nijmegen
Version 2.01, January 1996

[9] H,J. Schouwenaars et. al.

A low-power stereo 16-bit CMOS D/A converter for digital audio
IEEE Journal of solid-state circuits, vol. 23, no. 6, December 1988

(10] A. Cremonesi et. al.

A 1OO-MHz CMOS DAC for video-graphics systems
IEEE Journal of solid-state circuits, vol. 24, no. 3, June 1989

[11] D.R Scheffer, graduation report Eindhoven University ofTechnology

Design of a 10-bit I-Gsample/sec DAC,
Eindhoven, 1993

[12] F.M.P Brouwers, graduation report Eindhoven University of Technology

Design of a 10-bit I-Gsample/sec Digital-to-analog converter,
Eindhoven, August 1996

62 ©Philips Electronics N.V. 1997

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[13] ClOO Library handbook

Philips Semiconductors Nijmegen, Library Group
Nijmegen, March 1996

[14] David A. Hodges and Horace G. Jackson,

Analysis and design of digital integrated circuits,
Second edition, McGraw-Hill Book Company,
Singapore, 1988

[15] Gene F. Franklin, J. David Powell and Abbas Emarni-Naeini,

Feedback control of dynamic systems
Third edition, Addison-Wesley Publishing Company, Inc.,
Stanford, 1994

©Philips Electronics N.V. 1997 63

 Company restricted

Appendix A.I Floorplan of the segment decoder

"'• ..,.a&-
';'7...,az.
."" ..,.a&-
.a• ..-..
.~,...,a.m
._" ...,.au

I~
~
.3

.••
05

~::~
.
•7
08

.12
.13

~
::;
.1.
...
"7
.1•

112'
.21
.22
~1123

~~:~; 112.

.2.02.
1127
...,_;"~7t
, ...
12:, MaJ'
~oJI
oJl
.32
o.1J
.3<4
.J!!
.38
037
.3•

......
• 31

..2
"3

:;:.,.::;"7
----.~=
::
05'
.52
0 ..
,,"'''',->11,
,
'"" ,.,

§i .511
.511
057
.58

~ ..'
:::
"2

"~-_ "~-_. "~-u1 "~-_ "r4-,--" "~---~ "r4-,....

.. ..

~~7~~~~~

64 @Philips Electronics N.V. 1997

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Appendix A.2 Floorplan of the column decoder

bB
b8 A
b6 Z
8 R22_76
'0
Z 1 j0
b6
b6 b7 A Z
b7 8

~~ B~2V9
:~ l" _; Z~~ •
b71
~ j1
Z---,ML-;
b6
b7 A
--l0.oi..1..-----11---1 8
j2
b8

I ~ND2
~. n36 ~j •
bB r·N3D22_84
If B ~ j.3
bB
bB .i _A8 36 _A8
.

b6
-'-'u..L----1.....--fA
b8
-'-''''-'-----11---1 8

j4
b7
b8 A
---I.ol~----tlt----i 8

b6 ND22:L'9
b7 A n62 n02 ND22_92
'6
Z~J... _
-~~t----i8 Z n32 A j6
8

b7
b8 A
--UJ..I.----tlt----i 8

@Philips Electronics N.V. 1997 65

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Appendix A.3 Floorplan of the row decoder

b9
b9 b1f2l A
t---....- --18
Z f---I..----,
b10 n31
A
OR212_7
n67
8
ZI---l.--------------- i1
b1f2l
n67
b11 A
b 11 ..--- --i 8

"i2

,---------, AND22L87
b9
b1f2l A Z n72
...........L.LL-----III___l 8 '-- n72-iA
n55
h7'+~J---l8
ZI---l.-------------- ;3
b 11
....u...~---1I--lA
b 11 Z
...........L..L-----III--i 8

AND22L92
b9
n75
b11 A Z
..........J...J--._--i8
n75

b1f2l
AND22L9Ui8 A ZI---l.-------------- is
n58 8
b11 A Z
....u...~---11--l8

.--------, AND221_97
b9 ,---------, AND22L99
- ...........----III-f2l-iA Z n37 n37 A i7
b1
------'.L.UC~1___l8
r--
n.34
--l B Z 1---1-------------- i7
.--------, AND 2L98
b10
b11 A Z n34
------'.L..L-1----111___l B

66 @Philips Electronics N.V. 1997

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Appendix A.4 Floorplan of the local cell decoder

i~nAN02_1
inl "~-.L,t12

In .---.
n Z - . - - - . . , dec 1

in A!:2_2B
J W>-----...
Ok . .
G
jk
A
B
Z
n7

AND2_0
In .,.>----.-
...
... in1
In
A dec3
Zr-. ~. dec3
in1 ~ .-B

AND2_0
In
In ~ = A dec4
"k . .
J .,.>-------.- jk
B
Zr-. ~ dec4

vdd vdd

Vdd'rr p5
~1~dd!
-Ie 6/035
dec5

--.dec5

n17 MN18 dec5 MN2

;n'l 1/0.35 nL1[ 35/0.35

gndl' gndl'
gnd gnd

©Philips Electronics N.V. 1997 67

Company restricted

Appendix A.5 Schematic of the logic AND gates

vdd vdd
AND2: vdd

vd. P25
,---_~B_lIVdd!
1.2/CU5
n44

n44 MN27
1.2/0.35 Z
A
n46

n46 MN28 Z MN30

1.2/0.35 n4 1.6/0.35
B

AND22i (extra buffered):

vdd vdd vdd

P24 vd . P25 vdd. P26

B n4
vdd! vdd!8/0.35
2.2/0.35
n44 Z

gnd gnd

68 ©Philips Electronics N.V. 1997

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,Appendix A.6 Schematic of the logic OR gates

vdd vdd

OR2:

Z MN2
1.6/0..35

gnd

0R22i (extra buffered):

vdd
vdd

vdd! P4

• .1 vdd!
n7
5.75/0.35

Z MN2
.3.2/0..35

gnd

©Philips Electronics N.V. 1997 69

 Company restricted

AppendixB Schematic of the single-differential converter

Vdd

MP11 d Vd P110 V PIll

21 n21 21
2.4/1
Vdd ......,....---.....ff"~i'71-------~n
:..:t1V,dd
2/1 2/1
Fold=2 n21 n58 Fold=2 n61 Fold=2

Vdd MN101
t---- -+ +-_~n.:;5~1 1.6/0.6
Fold=2
Vo
Vdd MN102
t---------t---_----I-_ _...:.n;;:6:..:j' 1 1.6/0.6
Fold=2
MN6 n61 Vonot
Yin 3/0.35 32
FOld=2 It-------+

MN156
bias2 1.6/0.35
Fold=2

MN113 MN8
21.5/1.5 11.6/1.5
'bias1
Fold=2 Fola=2

70 @Philips Electronics N.V. 1997

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Appendix C Schematic of the clock buffer

jd

MP6
P58 V P59 P55
n19
1J:-<....4jIoCG4-,..,...".....----------------''-+-.:Wdd 25/1
n2"6 Fold-2

Vdd MN6J
n19 4"/11.7
+-------------------1---------+---'-." Fold-2
Vdd MN61
elkout n2" 40/11.7
+----------1-----+---->-11 Fold =2
elkoulno
n191 MN66 MN67 n2"6
elk; 1"/".J5 l"/".J5 174
.~----1--":""--11 Fold=2 Fold=2 It-------+

nl7 P54 + - - - - - - - + - - - - I a c1kout

Vo
nI7\/2
+ - - - -...... c1koutnot
Vos Fold=2

elkoul MN62
Vbiool 9"/1
old=2 Fold=2

©Philips Electronics N.V. 1997 71

 Company restricted

Appendix D Schematic 'of the master-slave latch

Vdd. Vdd

v• • • 'Iss
Vbio85
,'0.4 • Vbios4
~.5 • Vblos5

Bit. bit

itnal • bi tna '

elk • elk hI.

M;not . . dkno t

Q 41 VOllI,laye
I10t ."""'no.,I",,.

n87

~.8

72 ©Philips Electronics N.V. 1997

 Company restricted

AppendixE Schematics of the buffers

Buffer bitO, bitt, bit2:

Vdd

Vbios1 .. Vbios1
Vdd MN56

......
Vss IJ.7/0.7
vss.

Vdd Vdd

Via
Yin

Vinnot
Vjonot :;
o
VO!!t >
Vout •

Voutnot • VOlltnot

n43 Vout MN55

Vbiosl'bios 1 Vbios1 1.2/2

Vss

Buffer bit3:
Vdd

Voios1 .. Vbios1
P2IJ

2.211

....
Vss Fold=2
Vss.

Vdd Vdd

Yin

Vinnot
Vout •
.. Vja

Vjnnot

VOilt
-0c:
:;
a
>

Voutnot • VOlltoot

n43 Voul MN55

Vbiostbiosl Vbiosl 2.3/2
Fold=2
Vss

Buffer bit4:
Vdd

Vbios1

Vss.
• Vbios1

Vss Vdd MN56

4.lIIJ.7

••
Fold =2
Vdd Vdd

Yin

Vinnot
Vout •
.. Via
Vinnot

VOI!t
:;
a
>
-0c:
:;
>
a

Voutnot • VO! ,toot

n43 Vout MN55

Vbiostbiosl Vbiosl 9.312
Fold=2
VSS

<elPhilips Electronics N.V. 1997

73
 Company restricted

Vdd
Buffer bitS:

Vbiosl

Vss.
• Vbiosl

Vss ~N56
4.610.7

••
Fold=2
Vdd
Vdd

yin Vin
oc
Vinnot
41
Vout
• Vin not

VOl,t
:;
>
o
:;
>
o

Voutnot 41 Valltont

n43 Vout ~N55

Vbios~bio.l Ybiosl 4.612
Fold=2
Vss

Buffer segment: Vdd

Vbios1

VSS.
• Vbios1

Vss Vdd ~N56

8/0.7
Vdd

yin
•• Vdd

Vin
0
Fold=2

Vinnot

Vout.
• Vinnot

VoI!t
:;
0
>
.5
>
::J
0

Voutnot 41 VOIJtnot

n43 Vout ~N55

VbioSThio.l Vbio.l 18.612
Fold=2
Vss

74 te>Philips Electronics N.V. 1997

 Company restricted

AppendixF Schematics of the current switches

in _in in _in
10n _jonnn
innon _joDno
out • ....o.uL out.Ollt
tnon e"lnon outnon e"lnon
Qutnan
Qutnan
.ce . o l l r c e In~Olhnon in
Isource • 00Jrc
e In~Ol'noon
oulnon MN_swl Qutnan
Qutnan out Qutnan
n
In. in inno ir ,:>1 In. In

Isource
Isource MN_sw6
(source
In~ornnon in
.i~
lsource Isource

Current switch bitO: Current switch bit! :

in _in
)0 _i oann
in _in
innon _joann

out. o"t
Ion elltnon
outnon e'lloon
Qutnon
e .SOIl(C e
Isource . o l l rce In~olhoon
Qutnon

10
MN_sw2 oulnen
8/0.5
Fold=2 r. io

MN_sw5
MN_sw5 (source
2/0.5
Fold=2
4/0.5
Fold=2
In~olhooo
Isource (source

Current switch bit2: Current switch bit3:

©Philips Electronics N. V. 1997 75

 Company restricted

In _in
innon _i nnnn
In _in
innon _jonnn

out 41 o"t
out non e"loon
Qutnan outnon e'lloon
Isource esOlJ[ce In~o'j\JOOo Isource esolJrce
outnon
MN_sw2 Qutnen MN_sw2
16/0.5 32/"'.5
Fold=2
In. io
Fold=2

MN_sw5 Isource MN_sw5 Isource

8/0.5 In~OI}lOoo 16/"'.5 r~07n
Fold=2 Fold=2
Isource Isource

Current switch bit4: Current switch bitS:

innon _i
in _in
oono

outnon e"loon

Isource esQl,rCe

in

Isource
r~O'ibooo
Isource

Current switch segment:

76 ePhilips Electronics N.V. 1997

 Company restricted

AppendixG Schematics of the current sources

Vbios 1 •_ _- -
Vbios2 ••
lout . .
..---
__-
. -
,oJ"",,,
VbiqS~biO.S~[ 0.5/0..35
Vbios 1 •_ _- -
Vbios2 •• ..---
lout . .__-
. -

~~~I
"~
"12 MN csl
.3.85/5.95

g"dl'Fold=2

gnd

Current source bitG: Current source bit! :

Vbiosl ••
Vbios2 ••
lout . .
..---
..---
__-
. -
lo~t
Vbias~bio.s2J
~I
MN259
2/0 ..35
Fold=2
Vbiosl ••
Vbios2 ••
lout . .
..---
..---
__-
. -
lo~t
Vbias~bio.s2J
MN259
4/0 ..35

'11 -~~FOld=2

'112 MN cs 1 '112 MN csl

IJ~~~I .30.8/5.95

g'1d! g'1dl'FOld=.2

gnd
gnd

Current source bit2: Current source bit3:

@Philips Electronics N.V. 1997 77

 Company restricted

Vbias 1
Vbias2
.~--­
.~--­
lout ....- - Vbias~bi".s21
IO[~1
I
MN259
MU5
Fold=2
Vbiosl ••

lout
.---
Vbios2 •.
•---
41.~---
~L2J
IO~1
-I
MN259
16/0.35
Fold=2
n12 nl

n 12 MN_cs I nl2 MN csl

gnd! gnd!

gnd gnd

Current source bit4: Current source bitS:

Vbiosl ••
.---
Vbios2 ••
.---
lout •__-
• - ~".:..2J
IOr~1
-I
MN259
32/0.35
Fold=2
n1

n12 MN_csl

gnd!

gnd

Current source segment:

78 ePhilips Bectronics N.V. 1997