Pandian Saraswathi Yadav Engineering College, Arasanoor – 630561

Department of Electrical and Electronics Engineering

Course: B.E Electrical and Electronics Engineering
Cycle Test-I Examination Max. Marks: 50
Date: /08/2023 Time: 09.20 – 11.00 a.m
Sub Code & Subject:EE3501 & Power System Analysis
Year & Sem : III & V Name of the Faculty: Mrs.C.KalaRani

Note: Answer all the questions

Part A: (10 x 2 = 20)
1. What are the advantages of per unit system?
2. What is one line diagram?
3. How is generator in transient analysis represented?
4. Define bus impedance matrix and bus admittance matrix?
5. Define primitive network?
6. What is the need for power system analysis in planning and operation of power system?
7. The reactance of a generator designed X” is given as 0.2 per unit based on the generators name plate
rating of 20kv, 500 MVA. The base of calculation is 22 kv, 100MVA. Find X” on the new base.
8. Define per unit value of an electrical quantity. Write equation for base impedance with respect to 3
phase system.
9. What is impedance and reactance diagram?
10. Draw the π circuit representation of a transformer with off nominal tap ratio“α”
Part B: (3 x 10 = 30)
Note: Answer any 3
11.Draw the reactance diagram for the power system shown in figure. Neglect resistance and use a
base of 100 MVA, 220 kV in 50Ω line. The ratings of the generator, motor and transformer are given
below.
Generator : 40 MVA, 25 kV, X’’ =20%
Synchronous motor : 50 MVA, 11 kV, X’’=30%
Y-Y Transformer : 40 MVA, 33/220 kV,X=15%
Y-Δ Transformer : 30 MVA, 11/220 kV, X =15%
12. Determine the Z bus for the system whose reactance diagram is shown in fig. where the impedance is
given in per unit

13. Draw the per unit reactance diagram for the system shown in Fig. and mark all reactances in per unit on
50 MVA, 13.8 KV on generator G1.

G1 : 20 MVA, 13.8 KV, X’’=20%

G2 : 30 MVA, 18 KV, X’’=20% G3 :
30 MVA, 20 KV, X’’=20% T1 : 25
MVA, 220/13.8KV,X=10%
T2 :three single phase units each 10 MVA, 127/18 KV ,X=10%
T3 : 35 MVA, 220/22 KV, X=10%

14.Using singular transformation method , determine the YBus for the network shown in figure where the
impedances are labelled are shown in per unit.

STAFF IN CHARGE HOD/EEE VICEPRINCIPAL PRINCIPAL

 Pandian Saraswathi Yadav Engineering College, Arasanoor – 630561
Department of Electrical and Electronics Engineering
Course: B.E Electrical and Electronics Engineering
Unit Test-II Examination Max. Marks: 50
Date: 11/09/2023 Time: 11.30 – 1.00 p.m
Sub Code & Subject:EE8702 & Power System Operation And Control
Year & Sem : IV & VII Name of the Faculty: Mrs.C.KalaRani
Note: Answer all the questions
Part A: (10 x 2 = 20)
1. What are the assumptions made in dynamic response of uncontrolled case?
2. What is the function of load frequency control?
3. What is automatic load dispatching?
4. What is AGC?
5. What is meant by single area power system
6. Specify the use of static and dynamic response of ALFC loop
7. What is the main difference of load frequency and economic dispatch controls
8. What is the principle of tie line bias control.
9. What is the control area
10. What is meant by area control error?
Part B: (3 x 10 = 30)
Note: Answer any 3
11. Draw the block diagram of uncontrolled two area load frequency control system and explain the
uncontrolled static analysis.
12. Explain the dynamic analysis of controlled and uncontrolled case of single area load frequency
control
13. Explain in detail about the integration of economic dispatch with LFC with help of a block
diagram
14. Explain with neat block diagram tie line with frequency bias control of two area system

STAFF IN CHARGE HOD/EEE VICEPRINCIPAL PRINCIPAL

 Pandian Saraswathi Yadav Engineering College, Arasanoor – 630561
Department of Electrical and Electronics Engineering
Course: B.E Electrical and Electronics Engineering
Unit Test-II Examination Max. Marks: 50
Date: 05/09/2023 Time: 11.30 – 1.00 p.m
Sub Code & Subject:EE3501 & Power System Analysis
Year & Sem : III & V Name of the Faculty: Mrs.C.KalaRani
Note: Answer all the questions
Part A: (10 x 2 = 20)
1. What is P-Q bus in power flow analysis?
2. What do you mean by flat voltage start?
3. What is the need of slack bus in a power system?
4. What is meant by acceleration factor in Gauss – Seidal load flow solution and its best value.
5. What is Jacobian Matrix?
6. What is load flow analysis? Give the significance in power system analysis.
7. Mention any one advantage and one disadvantage of NR method over GS method.
8. Distinguish between slack bus and infinite bus.
9. When the generator bus is treated as load bus?
10. Write the general power flow equation.
Part B: (3 x 10 = 30)
Note: Answer any 3
15. Derive load flow algorithm using Gauss-Seidal method with flow chart and discuss the
advantages of the method.
16. Derive load flow algorithm using Newton-Raphson method with flowchart and discuss the
advantages of this method.
17. For the sample system shown in the fig. the generators are connected at all four buses while
the loads are at buses 2 and 3. Assuming a flat voltage start, examine bus voltages and bus
angles at the end of first Gauss seidal iterations and consider the reactive power limitas 0.2 ≤
Q2 ≤1 .
Bu P in pu Q in pu V in pu Remarks
s
1 - - 1.04∟0o Slack bus
 2 0.5 - 1.04pu PV bus
3 -1.0 0.5 - PQ bus
4 0.3 -0.1 - PQ bus

14. In the power system network shown in figure, bus 1 is slack bus with V1= 1.0 + j0.0 per
unit and bus 2 is a load bus with S2 = 280MW = j60MVAR. The line impedance on a base of
100MVA is Z = 0.02 + j0.04 per unit. Using Gauss – Seidal method, give V2.Use an initial

estimate of V2(0) = 1.0 + j0.0 and perform four iterations. Also find S1 and the real, reactive
power loss in the line, assuming that the bus voltages have converged.

STAFF IN CHARGE HOD/EEE VICEPRINCIPAL PRINCIPAL

 Pandian Saraswathi Yadav Engineering College, Arasanoor – 630561
Department of Electrical and Electronics Engineering
Course: B.E Electrical and Electronics Engineering
Unit Test-III Examination Max. Marks: 50
Date: 04/10/2023 Time: 11.20 AM – 1.00 PM
Sub Code & Subject:EE8702 & Power System Operation And Control
Year & Sem : IV & VII Name of the Faculty: Mrs.C.KalaRani
Note: Answer all the questions
Part A: (10 x 2 = 20)
1. What is the reason for transients during short circuits?
2. What is meant by fault in a power system?
3. How the circuit breakers can be selected?
4. Define short circuit MVA.
5. How do short circuits occur in a power system?
6. Write down the balanced fault and unbalanced faults occurring in a power system.
7. What is sequence network?
8. Mention two approximations made in short circuit studies.
9. Distinguish between symmetrical and unsymmetrical short circuits.
10. What is solid fault or bolted fault?
Part B: (3 x 10 = 30)
Note: Answer any 3
11. A 3- phase, 5 MVA, 6.6 kv alternator with a reactance of 8% is connected to a feeder of series
impedance (0.12+j0.48)ohm/phase/km through a step transformer. The transformer is rated at 3
MVA, 6.6kv/33kv and has a reactance of 5% Determine the fault current supplied by the
generator operating under no load with a voltage of 6.9kv, when a 3- phase symmetrical fault
occurs at a point 15 km along the feeder.
12. With the help of a detailed flowchart, explain how a symmetrical fault can be analysed using Z
bus

13. A 11 kv, 100 MVA alternator having a subtransient reactance of 0.25 pu is supplying a 50
MVA motor having a subtransient reactance of 0.2 pu through a transmission line. The
reactance is 0.05 pu on a base of 100 MVA. The motor is drawing 40 MW at 0.8 pf leading
with a terminal voltage of 10.95 kv when a three phase fault occurs at the generator
 terminals. Calculate the total current in generator and motor under fault conditions.
14.For the radial network shown in figure. Three phase fault occurs at F. Determine the fault
current and the line voltage at 11kv bus under fault conditions.

STAFF IN CHARGE HOD/EEE VICEPRINCIPAL PRINCIPAL

 Pandian Saraswathi Yadav Engineering College, Arasanoor – 630561
Department of Electrical and Electronics Engineering
Course: B.E Electrical and Electronics Engineering
Unit Test-III Examination Max. Marks: 50
Date: 10/10/2023 Time: 11.20 AM – 1.00 PM
Sub Code & Subject:EE8702 & Power System Operation And Control
Year & Sem : IV & VII Name of the Faculty: Mrs.C.KalaRani
Note: Answer all the questions
Part A: (10 x 2 = 20)
1. Define Spinning Reserve.
2. List the constraints in unit commitment problem.
3. What is participation factor with respect to economic load dispatch?
4. Write the condition for the optimal power dispatch in a lossless system.
5. What is base point with respect to economic load dispatch?
6. What is meant by priority list metod?
7. What is minimum up and minimum down time in unit commitment problem?
8. Write the equality and inequality constraints considered in the economic dispatch problem.
9. Draw incremental cost curve for a thermal plant.
10. What is the purpose of economic dispatch?
11. Part B: (3 x 10 = 30)
12. Note: Answer any 3
11. (i). What is unit commitment problem? Discuss the constraints that are to be accounted in unit
commitment problem..
(ii). Explain the priority ordering method of committing units. State merits and limitations of this
method.
12.
 Pandian Saraswathi Yadav Engineering College, Arasanoor – 630561
Department of Electrical and Electronics Engineering
Course: B.E Electrical and Electronics Engineering
Revision Test- II Examination Max. Marks: 100
Date & Session: 18/11/2023& AN Time: 1.15 PM – 4.15 PM
Sub Code & Subject:EE8702 & Power System Operation And Control
Year & Sem : IV & VII Name of the Faculty: Mrs.C.KalaRani
Note: Answer all the questions
Part A: (10 x 2 = 20)
1. Define Spinning Reserve.
2. List the constraints in unit commitment problem.
3. What is participation factor with respect to economic load dispatch?
4. What is meant by single area power system
5. Specify the use of static and dynamic response of ALFC loop
6. What is the main difference of load frequency and economic dispatch controls
7. Write the condition for the optimal power dispatch in a lossless system.
8. Define stiffness of the interconnected system.
9. What is the difference between load curve and load duration curve?
10. Define load factor and diversity factor.
Part B: (5 x 15= 65)
11. Explain in detail about the integration of economic dispatch with LFC with help of a block
diagram
12. Explain with neat block diagram tie line with frequency bias control of two area system.
13. What are the components of speed governor system of an alternator? Derive a transfer function
and sketch block diagram.
14. Explain the basic P-f and Q-V control loops in power system with relevant block diagram.
15. Consider the following three units:
IC1 = 7.92 + 0.003124 PG1
IC2 = 7.85 + 0.00388 PG2
IC3 = 7.97 + 0.00964 PG3;
PD = 850 MW ; PG1 = 392.2 MW; PG2 = 334.6 MW; PG3 = 122.2 MW.
Determine the optimum schedule if the load is increased to 900 MW by using Participation Factor
method.
Part C: (1 x 15= 15)
16. Formulate the Forward Dynamic Programming method of solving unit commitment problem with neat
flaw chart.
 Faculty In-charge HOD Vice Principal Principal

Pandian Saraswathi Yadav Engineering College, Arasanoor – 630561

Department of Electrical and Electronics Engineering
Course: B.E Electrical and Electronics Engineering
Revision Test- II Examination Max. Marks: 100
Date & Session: 16/11/2023& AN Time: 1.15 PM – 4.15 PM
Sub Code & Subject:EE3501 & Power System Analysis
Year & Sem : III & V Name of the Faculty: Mrs.C.KalaRani
Note: Answer all the questions
Part A: (10 x 2 = 20)
1. What is the reason for transients during short circuits?
2. What is meant by fault in a power system?
 3. How the circuit breakers can be selected?
4. Define short circuit MVA.
5. What is P-Q bus in power flow analysis?
6. What do you mean by flat voltage start?
7. What is the need of slack bus in a power system?
8. What is meant by acceleration factor in Gauss – Seidal load flow solution and its best value.
9. Distinguish between symmetrical and unsymmetrical short circuits.
10. What is solid fault or bolted fault?
Part B: (5 x 15= 65)

11. Derive load flow algorithm using Gauss-Seidal method with flow chart and discuss the
advantages of the method.
12. Derive load flow algorithm using Newton-Raphson method with flowchart and discuss the
advantages of this method.
13. Draw the reactance diagram for the power system shown in figure. Neglect resistance and
use a base of 100 MVA, 220 kV in 50Ω line. The ratings of the generator, motor and trans-
former are given below.
Generator : 40 MVA, 25 kV, X’’ =20%
Synchronous motor : 50 MVA, 11 kV, X’’=30%
Y-Y Transformer : 40 MVA, 33/220 kV, X=15%
Y-Δ Transformer : 30 MVA, 11/220 kV, X =15%

14. With the help of a detailed flowchart, explain how a symmetrical fault can be analysed using Z
bus

15. For the radial network shown in figure. Three phase fault occurs at F. Determine the fault current
and the line voltage at 11kv bus under fault conditions.
 Part C: (1 x 15= 15)
17. A 25MVA, 11kV generator with Xd”=20% is connected through a transformer, line and trans-
former to a bus that supplies three identical motors as shown in figure. Each motor has Xd”=20%
and Xd’=30% on a base of 5 MVA,6.6kV.The three phase rating of the step-up transformer is
25MVA,11/66kV with a leakage reactance of 10% and that of the step-down transformer is
25MVA,66/6.6kV with a leakage reactance of 10%.. The bus voltage at the motors is 6.6kV
when a three phase fault occurs at the point F, For the specified fault, calculate (i) The sub tran-
sient current in the fault
(ii) The sub transient current in the Breaker B.
(iii) The momentary current in breaker B
(iv) The current to be interrupted by breaker B in five cycles
Faculty In-charge HOD Vice Principal Principal

Pandian Saraswathi Yadav Engineering College, Arasanoor – 630561

Department of Electrical and Electronics Engineering
Course: B.E Electrical and Electronics Engineering
Unit Test-II Examination Max. Marks: 50
Date & Session: 17/11/2023 & FN Time: 11.20 AM – 1.00 PM
Sub Code & Subject:EE3302 & Digital Logic Circuits
Year & Sem : II & III Name of the Faculty: Mrs.C.KalaRani
Note: Answer all the questions
Part A: (10 x 2 = 20)
1. Convert the given expression in canonical SOP form Y = AB + A'C + BC’
2. Design a Half Subtractor and Half Adder.
3. Compare Decoder and Demultiplexer.
4. Draw the logical diagram of EX-OR gate using NAND gates.
5. Draw the NAND gate circuit using NOT, AND & OR Gates.
6. Given F = B' + A' B + A' C': Identify redundant term using K-Map.
7. Give one application each Multiplexer and Decoder.
8. Draw the truth table of 2 :1 MUX.
9. Define duality property.
10. What is a karnaugh map?
Part B: (3 x 10 = 30)
Note: Answer any 3
11. Design a Combinational logic circuit to convert Binary to Gray code and write its truth table.
12.(i) Reduce the following minterms using Karnaugh – Map: (7)
f(w, x, y, z)=Σm(0, 1, 3, 5, 6, 7, 8, 12, 14) + d(9, 15) .
(ii) Implement the following function using a suitable multiplexer f(a,b,c) = Σm (3, 7, 4, 5).
(3)
13.Design a full subtractor and realise using logic gates. Also, implement the same using half subtractors
14.(i). Design a BCD to Excess-3 code converter (5)
(ii). Simplify the boolean function using K-map and implement using only NAND gates. F(A,
B, C, D) =Σm(0,8,11,12,15) + Σd(1,2,4,7,10,14). Mark the essential and non-essential prime
implicants. (5)

Faculty In-charge HOD Vice Principal Principal

 Pandian Saraswathi Yadav Engineering College, Arasanoor – 630561
Department of Electrical and Electronics Engineering
Course: B.E Electrical and Electronics Engineering
Revision Test- I Examination Max. Marks: 100
Date & Session: 30/12/2023& AN Time: 1.15 PM – 4.15 PM
Sub Code & Subject:EE3302 & Digital Logic Circuits
Year & Sem : II & III Name of the Faculty: Mrs.C.KalaRani
Note: Answer all the questions
Part A: (10 x 2 = 20)
1. What is Programmable Logic Array?
2. List the language that are combined together to get VHDL language.
3. Draw the structure of PAL.
4. State the purpose of test bench.
5. Write a VHDL program for an EXNOR gate using behavioural coding.
6. What are the operators present in VHDL?
7. Draw basic configuration of three PLDS.
8. What is the advantage of PLA over ROM?
9. What is PROM?
10.What is package in VHDL?
Part B: (5 x 15= 65)
11. Explain the various types of hazards in sequential circuit design ant the methods to
eliminate them. Give suitable examples.
12.(i). Design a BCD to Excess 3 code converter and implement using suitable PLA.(10)
(ii). Draw a PLA circuit to implement the logic functions
ABC+ABC+AC and ABC+BC (5)
13.(i). Comparsion between PROM, PLA and PAL. (5)
(ii).A combinational logic circuit is defined by the following function.
F1(a,b,c)=Σ(0,1,6,7), F2(a,b,c)= Σ(2,3,5,7).
Implement the circuit with a PAL having three inputs, three product terms and two
outputs. (10)
14. Explain RTL design using VHDL With the help of example.
15.Explain the concept of behavioural modeling and structural modeling in VHDL. Take the
example of Full Adder design for both and write the coding.

Part C: (1 x 15= 15)

16. Design an asynchronous sequential circuit with two inputs x1 and x2 and one output z.
Initially, both inputs are equal to zero. When x1 or x2 becomes 1, the output z becomes 1.
When the second input also becomes 1, the output changes to 0. The output stays at 0
until the circuit goes back to the intial state.
Faculty In-charge HOD Vice Principal Principal