Experiment No.
Aim To verify the truth table of half adder by using XOR and NAND gates respectively.
Introduction
Adders are digital circuits that carry out addition of numbers. Adders are a key component of
arithmetic logic unit. Adders can be constructed for most of the numerical representations
like Binary Coded Decimal (BCD), Excess – 3, Gray code, Binary etc. out of these, binary
addition is the most frequently performed task by most common adders. Apart from addition,
adders are also used in certain digital applications like table index calculation, address
decoding etc.
Binary addition is similar to that of decimal addition. Some basic binary additions are shown
below.
Figure Schematic representation of half adder
1) Half Adder
Half adder is a combinational circuit that performs simple addition of two binary numbers. If
we assume A and B as the two bits whose addition is to be performed, the block diagram and
a truth table for half adder with A, B as inputs and Sum, Carry as outputs can be tabulated as
follows.
Figure. Block diagram and truth table of half adder
If A and B are binary inputs to the half adder, then the logic function to calculate sum S is Ex
– OR of A and B and logic function to calculate carry C is AND of A and B. Combining
these two, the logical circuit to implement the combinational circuit of half adder is shown
below.
Figure .Half Adder Logic Diagram
As we know that NAND and NOR are called universal gates as any logic system can be
implemented using these two, the half adder circuit can also be implemented using them. We
know that a half adder circuit has one Ex – OR gate and one AND gate.
Half Adder using NAND gates:
Five NAND gates are required in order to design a half adder. The circuit to realize half adder
using NAND gates is shown below.
Figure. Realization of half adder using NAND gates
Half Adder using NOR gates
Five NOR gates are required in order to design a half adder. The circuit to realize half adder
using NOR gates is shown below.
Figure7.Realization of half adder using NOR Gates
.
Result: The truth table of half adder by using XOR and NAND gates respectively verified
successfully.
Experiment No.4
Aim To verify the truth table of full adder by using XOR and NAND gates respectively.
Introduction
Adders are digital circuits that carry out addition of numbers. Adders are a key component of
arithmetic logic unit. Adders can be constructed for most of the numerical representations
like Binary Coded Decimal (BCD), Excess – 3, Gray code, Binary etc. out of these, binary
addition is the most frequently performed task by most common adders. Apart from addition,
adders are also used in certain digital applications like table index calculation, address
decoding etc.
Binary addition is similar to that of decimal addition. Some basic binary additions are shown
below.
Figure. Schematic representation of half adder
Full Adder
Full adder is a digital circuit used to calculate the sum of three binary bits. Full adders are
complex and difficult to implement when compared to half adders. Two of the three bits are
same as before which are A, the augend bit and B, the addend bit. The additional third bit is
carry bit from the previous stage and is called 'Carry' – in generally represented by CIN. It
calculates the sum of three bits along with the carry. The output carry is called Carry – out
and is represented by Carry OUT.
The block diagram of a full adder with A, B and CIN as inputs and S, Carry OUT as outputs
is shown below.
Figure. Full Adder Block Diagram and Truth Table
Figure. Full Adder Logic Diagram
Full Adder using NAND gates:
As mentioned earlier, a NAND gate is one of the universal gates and can be used to
implement any logic design. The circuit of full adder using only NAND gates is shown
below.
Figure. Full Adder using NAND gates
Full Adder using NOR gates:
As mentioned earlier, a NOR gate is one of the universal gates and can be used to implement
any logic design. The circuit of full adder using only NOR gates is shown below.
Figure. Full Adder using NOR gates
Result: The truth table of full adder by using XOR and NAND gates respectively verified
successfully.
