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Comprehensive Analysis of Three-phase Three-level T-type Neutral-Point-

Clamped Inverter with Hybrid Switch Combination

Conference Paper · June 2019

DOI: 10.1109/PEDG.2019.8807618

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Comprehensive Analysis of Three-phase Three-level
T-type Neutral-Point-Clamped Inverter with Hybrid
Switch Combination
Hongwu Peng* , Zhao Yuan, Balaji Narayanasamy, Xingchen Zhao, Amol Deshpande and Fang Luo
Department of Electrical Engineering
University of Arkansas
Fayetteville, AR, United States
*
hp013@uark.edu

Abstract—This paper comprehensively evaluates three space- [3] proposed a hybrid switch concept, as shown in Fig. 2. By
vector-modulation (SVM) schemes on a novel three-phase hybrid- adjusting the switching sequence of the two switches, the T-
switch-based 3-level T-type neutral-point-clamped (3L-TNPC) type inverter based on hybrid switch (hybrid structure 2) [4],
inverter, regarding switching loss, neutral point balancing and
EMI spectrum. The switching loss analysis based on the double- which is shown in Fig. 2, can have low switching loss, as
pulse test (DPT) are completed, revealing the loss characters of SiC MOSFET and low conduction loss, as IGBT. However,
each switch in 3L-TNPC. Based on the loss and EMI characters, this concept increases the system complexity in terms of
three kinds of SVMs are proposed, analyzed and compared. The gate driver and power loop design. Because more paralleled
optimal SVM is then selected based on comparison. semiconductors, more gate drivers and more gating signals are
Index Terms—three-level T-type inverter, hybrid switch, wide
bandgap devices, space vector modulation (SVM), neutral-point needed.
(NP) potential balance

I. I NTRODUCTION
Three-level TNPC inverter has been popular in renewable
energy generation systems [1], [2] because of its higher total
efficiency and lower output THD than two level inverter. And
due to lower switching loss, SiC MOSFETs enable higher
efficiency than Si IGBTs in power converters. To obtain higher
efficiency and power density in 3L TNPC, researchers start to
replace Si IGBT by SiC MOSFET. Due to the lower switching
loss of SiC MOSFET, the efficiency of the inverter can be
Fig. 2: Structure 1 of hybrid switch based T-type inverter [4]
pushed to a higher level.

Fig. 1: Structure of hybrid switch [3]

However, the high on-state resistance of unipolar SiC

MOSFET and the higher cost of SiC MOSFETs limits its
Fig. 3: Structure 2 of hybrid switch based T-type inverter
potential for use in commercial power converters. Therefore,
Another hybrid switch combination concept in a single
978-1-7281-2455-1/19/$31.00 ©2019 IEEE phase 3L-TNPC inverter was proposed in [5], which utilizes

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 (a) Switch state 1 (b) Switch state 0

(c) Switch state -1 (diode conducting) (d) Switch state -1 (MOSFET conducting)

Fig. 4: Different switching states when the phase current direction is positive

Si IGBT and SiC diode as clamping leg switches, and SiC 3 different SVM schemes are discussed. The optimum SVM
MOSFET for half bridge switch positions. The hybrid structure is then selected based on the efficiency. In Section III, a 20
2 is shown in Fig. 3. Using SPWM modulation, clamping leg kVA hardware is built and DPT is firstly performed to obtain
switches are soft switching under unity power factor, so both exact switching loss, then follows the analysis and comparison
conduction loss and switching loss of clamping leg will be low. of semiconductor loss breakdown, EMI spectrum and neutral
Therefore, the total semiconductor cost of this hybrid switch point voltage ripple for three SVMs. Section IV presents the
combination 3L-TNPC will be lower than all-SiC 3L-TNPC conclusion of preferred modulation scheme.
inverter. While the cost is low, the efficiency is higher than
II. A NALYSIS OF D IFFERENT M ODULATION ON H YBRID 3
that of the all-SiC 3L-TNPC inverter.
P HASE TNPC
Further more, if M1 , M4 , Q2 , Q2 , D2 and D2 in hybrid
In this chapter, switching loss of clamping leg will be
structure 1 are selected to operate, this operation condition is
analyzed in 3L-TNPC with hybrid switch combination. Then
essentially the same as hybrid structure 2. But hybrid structure
three different SVM schemes will be compared in terms of
2 has not been fully validated in the 3-phase 3L-TNPC system
switching losses, neutral point balancing capability and EMI
yet. One of the major challenges is to design a proper space
spectrum, which will give a guidance for hardware design and
vector modulation (SVM) scheme, which needs to consider
PWM modulation choice.
the soft switching feature of the clamping leg, neutral point
balancing (NPB) [6]–[9] and improving output EMI spectrum. A. Preferred Switch Pairs in Terms of Switching Loss Reduc-
This paper provides a modulation solution to hybrid structure 2 tion
based T-type inverter. Firstly, this paper obtains the switching Since switching loss of Si IGBT is much higher than SiC
loss of hybrid structure 2 based 3L-TNPC by experimental MOSFET, hard switching of Si IGBT on clamping leg in
double pulse test (DPT) result, then 3 different SVM schemes 3L-TNPC inverter with hybrid switch combination should be
are discussed in terms of switching loss, NPB and output EMI avoided or minimized. When phase current is positive, switch
spectrum. pair 1 and 0 is preferred since clamping leg is soft switching,
The organization of the paper is as follows. Section II as shown in Fig. 4(a) and Fig. 4(b). Switch pair 0 and -
summarizes the soft switching conditions for hybrid switch 1 should be avoided since clamping leg switch T2 is hard
based 3L-TNPC, then loss analysis, neutral point balancing switching, as shown in Fig. 4(b), Fig. 4(c) and Fig. 4(d).
capability and common mode noise voltage comparison of Symmetrically when phase current is negative, switch pair 0

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 TABLE I: Small vector’s influence on neutral point potential
Small Vector Angle Discharge neutral point Potential Charge neutral point Potential
0o V4 (1,0,0) V1 (0,-1,-1)
60o V5 (1,1,0) V2 (0,0,-1)

and -1 is preferred to obtain the soft switching character of region 3 and 2. From 1 it is known that V2 and V4 have lower
clamping leg, and switch pair 1 and 0 should be avoided or CM voltage than V1 and V5 .
minimized to reduce the switching loss of Si IGBT. Base on 2) Region 3 of Sector 1: For SVM 1, V1 and V2 are chosen
aforementioned analysis, different SVMs can be compared in to discharge neutral point voltage, V4 and V5 are chosen to
terms of switching loss, more detailed information is given charge the neutral point voltage, and final alignments are
below. respectively V3 -V2 -V1 -V2 -V2 and V3 -V4 -V5 -V4 -V3 when the
neutral point voltage is higher and lower than half of the DC-
link voltage. Since phase b switches between 1 and 0 plus 0
and -1, clamping leg has hard switching actions.
In SVM 2 scheme, region 3 is divided into region 3.1 and
region 3.2. For region 3.1, V5 is eliminated to reduce switching
loss of clamping leg. Then V1 or V4 will be chose to balance
the neutral point voltage, the alignment will be respectively
V1 -V2 -V3 -V2 -V1 and V2 -V3 -V4 -V3 -V2 when the neutral point
voltage is higher and lower than half of the DC-link voltage.
Same story for region 1.2, V1 is eliminated and alignments
will be V4 -V3 -V2 -V3 -V4 and V5 -V4 -V3 -V4 -V5 to discharge and
charge the neutral point voltage. Phase b clamping leg will
always be soft switching under unit PF.
Improved SVM 2 scheme is proposed to further reduce the
switching loss under wider power factor range, elimination
of V1 or V5 will be based on the phase b current direction
rather than phase b voltage direction. When phase b current
is negative, alignments V1 -V2 -V3 -V2 -V1 and V2 -V3 -V4 -V3 -V2
are chose to discharge and discharge the neutral point voltage.
When phase b current is positive, V4 -V3 -V2 -V3 -V4 and V5 -V4 -
V3 -V4 -V5 are chosen. Improved SVM 2 scheme is intrinsically
Fig. 5: Three phase three level space vector hexagon the same as SVM 2 scheme under unit power factor, and it
has lower loss on clamping leg under non-unit power factor
case.
B. Comparison of Different SVM Schemes
3) Region 2 of Sector 1: For region 2, modulation strategies
For switching loss reduction [5] and NPB [6]–[9] in 3 of SVM 1, SVM 2 and improved SVM 2 are the same. V1 and
phase 3L-TNPC inverter with hybrid switch combination, V4 are chose to discharge and charge the neutral point voltage,
SVM 1 with NPB [7], SVM 2 with NPB [8] and improved alignments will be V6 -V3 -V4 -V3 -V6 and V1 -V6 -V3 -V6 -V1 when
SVM 2 with NPB will be compared, and 1st sector of the the neutral point voltage is lower and higher than half of the
space vector modulation hexagon will be given as an example DC-link voltage. Soft switching can be achieved on clamping
under high power factor case. Nearest three space vector [10] leg of phase b under unit power factor.
and discontinuous pulse width modulation (DPWM) [11] are 4) Summary of Different SVM Schemes: In general, im-
adopted to track the reference vector and further reduce the proved SVM 2 scheme has the lowest switching loss on
switching loss. Common mode (CM) voltage noise at output clamping leg. And under non-unity power factor condition,
side can be modeled [12] through (1). SVM 1 has better neutral point balancing ability than SVM
2 and improved SVM 2. Since SVM 2 and improved SVM
VCM = (VAN + VBN + VCN )/3 (1) 2 eliminate V1 or V5 for reducing switching losses, and
according to (1), V1 or V5 has higher CM voltage, SVM 2
1) Switching Loss Reduction, NPB and CM Voltage Analy- and improved SVM 2 can get better CM performance than
sis of Different SVM Schemes: Firstly, space vectors of sector SVM 1.
1 are marked out in Fig. 5 and small vectors influence on
neutral point potential is stated in Table I. For the simplicity, III. E XPERIMENTAL T EST AND L OSS B REAKDOWN
region 3 and 2 will be analyzed and compared, choices of To evaluate the efficiency and noise spectrum under different
small vectors and alignments in region 1 and 4 are similar to SVM, a 20 kVA 3-phase 3L-TNPC prototype is built, upper

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 (a) SVM 1 (b) SVM 2 (c) Improved SVM 2

Fig. 6: Loss breakdown of semiconductor devices using different SVM, PF=1

(a) SVM 1 (b) SVM 2 (c) Improved SVM 2

Fig. 7: Loss breakdown of semiconductor devices using different SVM, PF=0.8

redrawn and given as an example in Fig .9.

Fig. 9: IGBT Switching Waveform

Switching loss calculation based on device’s voltage and

current waveform is comprehensively evaluated in [13]–[15].
During turn on transient, the integral of the switching power
Fig. 8: Test setup of DPT
from 10% of the device’s commutation current at the current
rising edge to 10% of device’s commutation voltage at the
voltage falling edge is obtained as switching on loss. And
and lower DC-link capacitor are 300 µF each. Top leg and during turn off transient, integral of the switching power from
bottom leg switches are rated for 1.2 kV, and remaining some 10% of device’s commutation voltage at the voltage rising
safety margin DC-link voltage is set to be 800 V. Output RMS edge to 10% of the device’s commutation current at the current
voltage is set to 208 V to meet one of the grid standards. rising edge is obtained as switching off loss.
Switching frequency is set be 70 kHz to further reduce the As mentioned in [16], switching loss in 3L phase leg is
passive components’ volume. The prototype is composed by different from 2L half bridge due to the device’s junction
three 7-kVA single-phase 3L-TNPC, as shown in Fig.8. capacitance, so double pulse test in this paper is performed
1) DPT of Three Level Inverter: DPT is firstly performed based on single-phase 3L-TNPC platform. In this way, loss
to obtain the switching transitions of both SiC MOSFET analysis using switching loss data from double pulse test will
and IGBT devices. Switching transitions of IGBT under are give more accurate results.

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 (a) CM voltage spectrum (b) Phase voltage spectrum

Fig. 10: EMI spectrum of different SVMs, PF=0.8

2) Semiconductor Loss Breakdown and EMI Performance in this topology comprehensively in terms of their influences
Evaluation: Using the switching loss from double pulse test on switching loss, NPB and EMI spectrum, and then improved
and device conducting performance in component data sheet, SVM 2 is proposed to further push the converter to a higher
a detailed semiconductor loss breakdown can be obtained in efficiency.
simulation. While total power level is 20 kVA, and switching Comparing to SVM 1, SVM 2 and improved SVM 2
frequency is 70 kHz. schemes have better loss performance and CM noise perfor-
For unit PF case, loss breakdown for different modulation mance, while improved SVM 2 scheme has the lowest power
schemes is listed in Fig. 6, and total semiconductor loss using loss and lowest CM noise. As for neutral point balancing
SVM 1, SVM 2 and improved SVM 2 will be respectively capability, SVM 1 is better than SVM 2 and improved SVM 2
73.4 W, 70.0 W and 70.0 W. As we can see from the diagram, under non-unit power factor, and their neutral point balancing
under unit power factor case, total loss of SVM2 or improved capabilities are the same under unit power factor.
SVM 2 are 4.6% lower than using SVM 1. All of the SVMs 3 phase hybrid switch combination TNPC is comprehen-
have the same 4 V neutral point voltage ripple, which is the sively studied in this paper, and it will give a guidance for
ripple voltage due to the hysteresis control algorithm at half hybrid switch topology design consideration and the choice of
of the switching frequency and switching actions at switching modulation strategy.
frequency.
However, for PF=0.8 (lead or leg) case, loss breakdown
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