UNIT - 5
VLSI FABRICATION
PROCESS
Silicon Wafers Oxidation Photolithography
Ion Implantation Diffusion Etching
Chemical Vapour
Deposition(CVD)
Metallization Packaging
Silicon Wafers Oxidation Photolithography
Ion Implantation Diffusion Etching
Chemical Vapour
Deposition(CVD)
Metallization Packaging
Ingots
Silicon Wafers
(400µm to 800µm)
Silicon Wafers Oxidation Photolithography
Ion Implantation Diffusion Etching
Chemical Vapour
Deposition(CVD)
Metallization Packaging
Oxidation
• Silicon react with oxygen to form Silicon Oxide(SiO2) under high
temperature(1000-1200oC) inside ultraclean furnace.
Silicon Wafers Oxidation Photolithography
Ion Implantation Diffusion Etching
Chemical Vapour
Deposition(CVD)
Metallization Packaging
Photolithography
Silicon Wafers Oxidation Photolithography
Ion Implantation Diffusion Etching
Chemical Vapour
Deposition(CVD)
Metallization Packaging
Etching
WET ETCHING DRY ETCHING
Method • Chemical Reaction • Gas Reaction
• Hydrofluoric acid (HF) , potassium • Corrosive gas(or ions)
Hydroxide(KOH) etc.
• Chemical attack in all direction • Highly Directional (Anisotropic
(Isotropic etching) etching)
Advantage Low cost High Precision
High speed Enables micro-patterning
Simple process
Disadvantage Low Precision High cost
Chemical contamination Low speed
Complex process
Etching Direction
Silicon Wafers Oxidation Photolithography
Ion Implantation Diffusion Etching
Chemical Vapour
Deposition(CVD)
Metallization Packaging
Diffusion
• Atom moves from high concentration to lower concentration region.
• Diffusion of impurities (dopants) is usually carried out at high
temperature (1000-1200oC).
• Performed in furnace similar to oxidation.
• Depth of impurities depend on temperature and processing time.
Silicon Wafers Oxidation Photolithography
Ion Implantation Diffusion Etching
Chemical Vapour
Deposition(CVD)
Metallization Packaging
Ion Implantation
• Another method to add impurities.
• An ion implanter produces ions of desired dopant, accelerates them
by electric field, and allow them to strike on semiconductor material.
• Depth depend on energy of ion beam
• Quantity controlled by flow of ion.
• Performed at room temperature, accurate.
Silicon Wafers Oxidation Photolithography
Ion Implantation Diffusion Etching
Chemical Vapour
Deposition(CVD)
Metallization Packaging
Chemical Vapour Deposition(CVD)
• CVD can be used to formation of solids on substrate including SiO2 , polysilicon etc.
• Faster rate and lower temperature (below 500oC)
Silicon Wafers Oxidation Photolithography
Ion Implantation Diffusion Etching
Chemical Vapour
Deposition(CVD)
Metallization Packaging
Metallization
• Depositing metal layers on a wafer to
form conductive pathways.
• The required interconnection pattern
is then selectively etched.
• Sputtering process.
Silicon Wafers Oxidation Photolithography
Ion Implantation Diffusion Etching
Chemical Vapour
Deposition(CVD)
Metallization Packaging
Packaging
• A finished silicon wafer may contain several hundred of circuits or
chips.
VLSI Design Flow
Simplified VLSI Design Flows
System
Specification
Functional
(Architecture) Circuit Design
Behavioral Design Circuit
Representation Representation
Functional Circuit
Verification Verification
Logic Design Physical Design
Layout
Logic(Gate-Level) Representation
Representation Physical
Logic Verification Verification
Front Back
Synthesis
End End
Layout
Phase Phase
Behavioral
Representation
Logic (Gate-Level) Logic Blocks, Gates
Representation
Circuit
(Transistor-Level)
Representation
Layout Physical Devices
Representation
System Specification
• First step of design process is to lay down the specification of the
system.
• High level representation of the system.
• Factors considered:
• Performance, Functionality, Physical dimension, Design technique, Fabrication
technology
• It is a compromise between market requirements, technological and
economical viability.
• The end results are specifications of
• Size, Speed, Power and Functionality of the VLSI system
• Basic architecture
Functional Design
• Main functional units, Interconnect requirements of the system are identified
• The area, power and other parameters of each unit are estimated
• The key idea is to specify behavior, in terms of
• Input, Output, Timing of each unit
• The outcome of functional design is usually a timing diagram
• This information leads to improvement of the overall design process and
reduction of complexity of the subsequent phases
Logic Design
• Design the logic, that is,
Boolean expressions, word width, register allocation, etc.
• The outcome is called an RTL (Register Transfer Level) description.
RTL is expressed in a HDL (Hardware Description Language), such as
VHDL and Verilog.
Circuit Design
• The purpose of the circuit design is to develop a circuit representation
based on the logic design.
• The Boolean expression can be converted into a circuit representation by
taking into consideration the speed and power requirements of the
original design.
• Design the circuit including gates, transistors, interconnections, etc. The
outcome is called a netlist.
• Circuit simulation is used to verify the correctness and timing of
component
Physical Design
• Given a circuit after logic synthesis, to convert it into a layout.
• Floor-planning
• Placement
• Routing
Floor-planning
• Placing blocks or macros in the chip or core
area
• Deriving the die size
• Allocating space for soft blocks
• Planning power
• Creating the boundary and core area
• Creating wire tracks for placement of
standard cells
Placement
• The process of finding a suitable
physical location for each cell in a
block.
• It affects: Routability , Performance,
Heat distribution, Power
consumption.
• The tool determines the location of
each standard cell on the die. The
tool tries to place the cells in such a
way that the design has minimal
congestions and the best timing.
Routing
• The process of creating physical connections between signal pins using metal
layers.
• Routing determines the precise pathways for interconnecting:
• Standard cells
• Macros(reusable pieces of logic blocks)
• I/O pins
Design Verification
• Design Verification in VLSI is a crucial and time-consuming step.
• It aims at ensuring that the product or system design adheres to specified
standards and requirements.
• Two main types of verifications are commonly employed:
• Functional Verification: examines whether the design or system behaviour is
functional
• Static Timing Analysis: focuses on confirming timing requirements.
• These verification steps must be applied after every design stage,
including translation, placement, and routing.
• Verification in VLSI comprises two phases:
• Verification: Predictive analysis to ensure the synthesized design will perform the
specified I/O function when built.
• Test: Testing, a production phase to check for manufacturing flaws in the actual
gadget created from the synthesized design.
• The objective of Design Verification is to provide test findings that
demonstrate the correspondence between design outputs (the real
product) and design inputs (product requirements and specifications).
• There are various approaches to design verification, all aimed at reviewing
and providing evidence that the output of a software product matches the
input specifications.
