0% found this document useful (0 votes)

15 views89 pages

TL072

The TL07xx series are low-noise, FET-input operational amplifiers designed for high performance with features like a high slew rate of 20V/μs and low offset voltage of 1mV. They are suitable for a variety of applications including solar energy systems, motor drives, and audio equipment, and operate over a wide temperature range of -40°C to +125°C. The document provides detailed specifications, pin configurations, and device information for the TL071, TL072, and TL074 models.

Uploaded by

daisoosida

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

0% found this document useful (0 votes)

15 views89 pages

TL072

Uploaded by

daisoosida

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

You are on page 1/ 89

TL071, TL071A, TL071B, TL071H

TL072, TL072A, TL072B, TL072H, TL072M

TL074, TL074A, TL074B, TL074H, TL074M
SLOS080W – SEPTEMBER 1978 – REVISED JULY 2025

TL07xx Low-Noise, FET-Input Operational Amplifiers

1 Features High ESD (1.5kV, HBM), integrated EMI and RF
filters, and operation across the full –40°C to +125°C
• High slew rate: 20V/μs (TL07xH, typ)
range enable the TL07xH devices for use in the most
• Low offset voltage: 1mV (TL07xH, typ)
rugged and demanding applications.
• Low offset voltage drift: 2μV/°C
• Low power consumption: 940μA/ch (TL07xH, typ) Device Information
• Wide common-mode and differential PART
CHANNEL COUNT PACKAGE
voltage ranges NUMBER(1)
– Common-mode input voltage range D (SOIC, 8)
includes VCC+ DBV (SOT-23, 5)
• Low input bias and offset currents TL071x Single DCK (SC70, 5)
• Low noise:
P (PDIP, 8)
– Vn = 37nV/√Hz (typ) at f = 1kHz
PS (SO, 8)
• Output short-circuit protection
D (SOIC, 8)
• Low total harmonic distortion: 0.003% (typ)
• Wide supply voltage: DDF (SOT-23-THIN, 8)

– ±2.25V to ±20V, 4.5V to 40V TL072x Dual P (PDIP, 8)

PS (SO, 8)
2 Applications PW (TSSOP, 8)
• Solar energy: string and central inverter FK (LCCC, 20)
• Motor drives: ac and servo drive control and TL072M(2) Dual JG (CDIP, 8)
power-stage modules
U (CFP, 10)
• Single-phase online UPS
D (SOIC, 14)
• Three-phase UPS
• Pro audio mixers DB (SSOP, 14)
• Battery test equipment DYY (SOT-23-THIN, 14)
TL074x Quad
N (PDIP, 14)
3 Description
NS (SOP, 14)
The TL071H, TL072H, and TL074H (TL07xH) family PW (TSSOP, 14)
of devices are next-generation versions of the FK (LCCC, 20)
industry-standard TL071, TL072, and TL074 (TL07x)
TL074M(2) Quad J (CDIP, 14)
devices. These devices provide outstanding value for
cost-sensitive applications, with features including low W (CFP, 14)
offset (1mV, typical), high slew rate (20V/μs), and (1) For more information, see Section 11.
common-mode input to the positive supply. (2) Devices with M suffix have an extended temperature range of
–55°C to +125°C.

TL071 for PS Package (SO, 8) Only TL071 (Each Amplifier)

TL072 (Each Amplifier)
OFFSET N1 TL074 (Each Amplifier)

IN+ + IN+ +
OUT OUT
IN − IN −

OFFSET N2

Logic Symbols

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TL071, TL071A, TL071B, TL071H
TL072, TL072A, TL072B, TL072H, TL072M
TL074, TL074A, TL074B, TL074H, TL074M
SLOS080W – SEPTEMBER 1978 – REVISED JULY 2025 www.ti.com

Table of Contents
1 Features............................................................................1 7 Detailed Description......................................................29
2 Applications..................................................................... 1 7.1 Overview................................................................... 29
3 Description.......................................................................1 7.2 Functional Block Diagram......................................... 29
4 Pin Configuration and Functions...................................3 7.3 Feature Description...................................................29
5 Specifications................................................................ 10 7.4 Device Functional Modes..........................................29
5.1 Absolute Maximum Ratings...................................... 10 8 Application and Implementation.................................. 30
5.2 ESD Ratings............................................................. 10 8.1 Application Information............................................. 30
5.3 Recommended Operating Conditions....................... 11 8.2 Typical Applications.................................................. 30
5.4 Thermal Information for Single Channel................... 11 8.3 Power Supply Recommendations.............................32
5.5 Thermal Information for Dual Channel...................... 11 8.4 Layout....................................................................... 32
5.6 Thermal Information for Quad Channel.................... 12 9 Device and Documentation Support............................34
5.7 Electrical Characteristics for TL07xH........................13 9.1 Device Support......................................................... 34
5.8 Electrical Characteristics (DC) for TL07xC, 9.2 Receiving Notification of Documentation Updates....34
TL07xAC, TL07xBC, TL07xI, TL07xM........................ 15 9.3 Support Resources................................................... 34
5.9 Electrical Characteristics (AC) for TL07xC, 9.4 Trademarks............................................................... 34
TL07xAC, TL07xBC, TL07xI, TL07xM........................ 16 9.5 Electrostatic Discharge Caution................................34
5.10 Typical Characteristics: TL07xH............................. 17 9.6 Glossary....................................................................34
5.11 Typical Characteristics: All Devices Except 10 Revision History.......................................................... 34
TL07xH........................................................................24 11 Mechanical, Packaging, and Orderable
6 Parameter Measurement Information.......................... 28 Information.................................................................... 35

2 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A TL074B TL074H TL074M
TL071, TL071A, TL071B, TL071H
TL072, TL072A, TL072B, TL072H, TL072M
TL074, TL074A, TL074B, TL074H, TL074M
www.ti.com SLOS080W – SEPTEMBER 1978 – REVISED JULY 2025

4 Pin Configuration and Functions

OUT 1 5 VCC+ IN+ 1 5 VCC+

VCC– 2 VCC– 2

IN+ 3 4 IN– IN– 3 4 OUT

Not to scale Not to scale

Figure 4-1. TL071H DBV Package, 5-Pin SOT-23 Figure 4-2. TL071H DCK Package, 5-Pin SC70
(Top View) (Top View)

NC 1 8 NC

IN– 2 7 VCC+

IN+ 3 6 OUT

VCC– 4 5 NC

Not to scale
Figure 4-3. TL071x D Package, 8-Pin SOIC
and P Package, 8-pin PDIP
(Top View)

Table 4-1. Pin Functions: TL071x

PIN
NO.
TYPE DESCRIPTION
NAME DBV DCK D P
(SOT-23) (SC70) (SOIC) (PDIP)
IN– 4 3 2 2 Input Inverting input
IN+ 3 1 3 3 Input Noninverting input
NC — — 8 8 — Do not connect
NC — — 1 1 — Do not connect
NC — — 5 5 — Do not connect
OUT 1 4 6 6 Output Output
VCC– 2 2 4 4 — Power supply
VCC+ 5 5 7 7 — Power supply

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A TL074B TL074H TL074M
TL071, TL071A, TL071B, TL071H
TL072, TL072A, TL072B, TL072H, TL072M
TL074, TL074A, TL074B, TL074H, TL074M
SLOS080W – SEPTEMBER 1978 – REVISED JULY 2025 www.ti.com

OFFSET N1 1 8 NC

IN± 2 7 VCC+

IN+ 3 6 OUT

VCC± 4 5 OFFSET N2

Not to scale

Figure 4-4. TL071C PS Package, 8-Pin SO

(Top View)

Table 4-2. Pin Functions: TL071C

PIN
TYPE DESCRIPTION
NAME NO.
IN– 2 Input Inverting input
IN+ 3 Input Noninverting input
NC 8 — Do not connect
OFFSET N1 1 — Input offset adjustment
OFFSET N2 5 — Input offset adjustment
OUT 6 Output Output
VCC– 4 — Power supply
VCC+ 7 — Power supply

4 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

1OUT 1 8 VCC+

1IN± 2 7 2OUT

1IN+ 3 6 2IN±

VCC± 4 5 2IN+

Not to scale

Figure 4-5. TL072x D, DDF, JG, P, PS, and PW Packages,

8-Pin SOIC, SOT-23-THIN, CDIP, PDIP, SO, and TSSOP
(Top View)

Table 4-3. Pin Functions: TL072x

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A TL074B TL074H TL074M
TL071, TL071A, TL071B, TL071H
TL072, TL072A, TL072B, TL072H, TL072M
TL074, TL074A, TL074B, TL074H, TL074M
SLOS080W – SEPTEMBER 1978 – REVISED JULY 2025 www.ti.com

NC 1 10 NC

1OUT 2 9 VCC+

1IN± 3 8 2OUT

1IN+ 4 7 2IN±

VCC± 5 6 2IN+

Not to scale

Figure 4-6. TL072M U Package, 10-Pin CFP

(Top View)

Table 4-4. Pin Functions: TL072M

PIN
TYPE DESCRIPTION
NAME NO.
1IN– 3 Input Inverting input
1IN+ 4 Input Noninverting input
1OUT 2 Output Output
2IN– 7 Input Inverting input
2IN+ 6 Input Noninverting input
2OUT 8 Output Output
NC 1, 10 — Do not connect
VCC– 5 — Power supply
VCC+ 9 — Power supply

6 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

VCC+
1OUT
NC

NC
3

19
NC 4 18 NC

1IN± 5 17 2OUT

NC 6 16 NC

1IN+ 7 15 2IN±

NC 8 14 NC

13
9
NC Not to scale

VCC±

2IN+

NC
Figure 4-7. TL072M FK Package, 20-Pin LCCC
(Top View)

Table 4-5. Pin Functions: TL072M

PIN
TYPE DESCRIPTION
NAME NO.
1IN– 5 Input Inverting input
1IN+ 7 Input Noninverting input
1OUT 2 Output Output
2IN– 15 Input Inverting input
2IN+ 12 Input Noninverting input
2OUT 17 Output Output
1, 3, 4, 6, 8,
NC 9, 11, 13, 14, — Do not connect
16, 18, 19
VCC– 10 — Power supply
VCC+ 20 — Power supply

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A TL074B TL074H TL074M
TL071, TL071A, TL071B, TL071H
TL072, TL072A, TL072B, TL072H, TL072M
TL074, TL074A, TL074B, TL074H, TL074M
SLOS080W – SEPTEMBER 1978 – REVISED JULY 2025 www.ti.com

1OUT 1 14 4OUT

1IN± 2 13 4IN±

1IN+ 3 12 4IN+

VCC+ 4 11 VCC±

2IN+ 5 10 3IN+

2IN± 6 9 3IN±

2OUT 7 8 3OUT

Not to scale

Figure 4-8. TL074x D, DYY, J, N, NS, PW and W Packages,

14-Pin SOIC, SOT-23-THIN, CDIP, PDIP, SOP, TSSOP, and CFP
(Top View)

Table 4-6. Pin Functions: TL074x

PIN
TYPE DESCRIPTION
NAME NO.
1IN– 2 Input Inverting input
1IN+ 3 Input Noninverting input
1OUT 1 Output Output
2IN– 6 Input Inverting input
2IN+ 5 Input Noninverting input
2OUT 7 Output Output
3IN– 9 Input Inverting input
3IN+ 10 Input Noninverting input
3OUT 8 Output Output
4IN– 13 Input Inverting input
4IN+ 12 Input Noninverting input
4OUT 14 Output Output
VCC– 11 — Power supply
VCC+ 4 — Power supply

8 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

1OUT

4OUT
1IN±

4IN±
NC
3

19
1IN+ 4 18 4IN+

NC 5 17 NC

VCC+ 6 16 VCC±

NC 7 15 NC

2IN+ 8 14 3IN+

13
9
Not to scale
2IN±

2OUT

3OUT

3IN±
Figure 4-9. TL074M FK Package, 20-Pin LCCC
(Top View)

Table 4-7. Pin Functions: TL074M

PIN
TYPE DESCRIPTION
NAME NO.
1IN– 3 Input Inverting input
1IN+ 4 Input Noninverting input
1OUT 2 Output Output
2IN– 9 Input Inverting input
2IN+ 8 Input Noninverting input
2OUT 10 Output Output
3IN– 13 Input Inverting input
3IN+ 14 Input Noninverting input
3OUT 12 Output Output
4IN– 19 Input Inverting input
4IN+ 18 Input Noninverting input
4OUT 20 Output Output
1, 5, 7, 11, 15,
NC — Do not connect
17
VCC– 16 — Power supply
VCC+ 6 — Power supply

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A TL074B TL074H TL074M
TL071, TL071A, TL071B, TL071H
TL072, TL072A, TL072B, TL072H, TL072M
TL074, TL074A, TL074B, TL074H, TL074M
SLOS080W – SEPTEMBER 1978 – REVISED JULY 2025 www.ti.com

5 Specifications
Note
The TLV07xx series has transitioned new die fabrication into a modern process.
This new die is available with an H suffix.
A die with a different suffix is either older or newer; see also Section 9.1.1.

Section 5.7 and Section 5.10 describe the performance of the new die.

Section 5.8, Section 5.9, and Section 5.11 describe the performance of the old die.

5.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)(1)
MIN MAX UNIT
All NS and PS packages; All TL07xM devices –0.3 36
Supply voltage, VS = (V+) – (V–) V
All other devices 0 42

Common-mode All NS and PS packages; All TL07xM devices (VCC–) – 0.3 (VCC–) + 36
V
voltage(2) All other devices (VCC–) – 0.5 (VCC+) + 0.5

Signal input All NS and PS packages; All TL07xM devices(3) (VCC–) – 0.3 (VCC–) + 36
Differential voltage(2) V
pins All other devices VS + 0.2
All NS and PS packages; All TL07xM devices 50
Current(2) mA
All other devices –10 10
Output short-circuit(4) Continuous
Operating ambient temperature, TA –55 150 °C
Junction temperature, TJ 150 °C
Case temperature for 60 seconds - FK package 260 °C
Lead temperature 1.8 mm (1/16 inch) from case for 10 seconds 300 °C
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Input pins are diode-clamped to both power-supply rails on all new die. Current limit input signals that swing more than 0.5 V beyond
the supply rails to 10 mA or less.
(3) Differential voltage only limited by input voltage.
(4) Short-circuit to ground, one amplifier per package.

5.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

10 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

5.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)
MIN MAX UNIT
All NS and PS packages; All TL07xM devices(1) 10 30
VS Supply voltage, (VCC+) – (VCC–) V
All other devices 4.5 40
All NS and PS packages; All TL07xM devices (VCC–) + 2 (VCC+) + 0.1
VI Input voltage V
All other devices (VCC–) + 4 (VCC+) + 0.1
TL07xM –55 125
TL07xH –40 125
TA Specified temperature(2) °C
TL07xI –40 85
TL07xC 0 70

(1) VCC+ and VCC– are not required to be of equal magnitude, provided that the total VS ((VCC+) – (VCC–)) is between 10 V and 30 V.
(2) See also Section 9.1.1.

5.4 Thermal Information for Single Channel

TL071xx
D DCK DBV P PS
THERMAL METRIC(1) UNIT
(SOIC) (SC70) (SOT-23) (PDIP) (SO)
8 PINS 5 PINS 5 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 158.8 217.5 212.2 85 95 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 98.6 113.1 111.1 – – °C/W
RθJB Junction-to-board thermal resistance 102.3 63.8 79.4 – – °C/W
ψJT Junction-to-top characterization parameter 45.8 34.8 51.8 – – °C/W
ψJB Junction-to-board characterization parameter 101.5 63.5 79.0 – – °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A N/A °C/W

(1) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

5.5 Thermal Information for Dual Channel

TL072xx
D DDF FK JG P PS PW U
THERMAL METRIC(1) UNIT
(SOIC) (SOT-23) (LCCC) (CDIP) (PDIP) (SO) (TSSOP) (CFP)
8 PINS 8 PINS 20 PINS 8 PINS 8 PINS 8 PINS 8 PINS 10 PINS
Junction-to-ambient
RθJA 147.8 181.5 – – 85 95 200.3 169.8 °C/W
thermal resistance
Junction-to-case (top)
RθJC(top) 88.2 112.5 5.61 15.05 – – 89.4 62.1 °C/W
thermal resistance
Junction-to-board
RθJB 91.4 98.2 – – – – 131.0 176.2 °C/W
thermal resistance
Junction-to-top
ψJT characterization 36.8 17.2 – – – – 22.2 48.4 °C/W
parameter
Junction-to-board
ψJB characterization 90.6 97.6 – – – – 129.3 144.1 °C/W
parameter
Junction-to-case
RθJC(bot) (bottom) thermal N/A N/A – – – – N/A 5.4 °C/W
resistance

(1) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A TL074B TL074H TL074M
TL071, TL071A, TL071B, TL071H
TL072, TL072A, TL072B, TL072H, TL072M
TL074, TL074A, TL074B, TL074H, TL074M
SLOS080W – SEPTEMBER 1978 – REVISED JULY 2025 www.ti.com

(1) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

12 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

5.7 Electrical Characteristics for TL07xH

at VS = (VCC+) – (VCC–) = 4.5 V to 40 V (±2.25 V to ±20 V), TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VOUT = VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
±1 ±4
VOS Input offset voltage mV
TA = –40°C to +125°C ±5
dVOS/dT Input offset voltage drift TA = –40°C to +125°C ±2 µV/℃
Input offset voltage versus VS = 5 V to 40 V,
PSRR TA = –40°C to +125°C ±1 ±10 μV/V
power supply VCM = VS / 2
Channel separation f = 0 Hz 10 µV/V
INPUT BIAS CURRENT
±1 ±120 pA
IB Input bias current DCK and DBV packages ±1 ±300 pA
TA = –40°C to +125°C(1) ±5 nA
±0.5 ±120 pA
IOS Input offset current DCK and DBV packages ±0.5 ±250 pA
TA = –40°C to +125°C(1) ±5 nA
NOISE
9.2 μVPP
EN Input voltage noise f = 0.1 Hz to 10 Hz
1.4 µVRMS
f = 1 kHz 37
eN Input voltage noise density nV/√Hz
f = 10 kHz 21
iN Input current noise f = 1 kHz 80 fA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage (VCC–) + 1.5 (VCC+) V

VS = 40 V, (VCC–) + 2.5 V < 100 105 dB

VCM < (VCC+) – 1.5 V TA = –40°C to +125°C 95 dB
Common-mode rejection
CMRR
ratio 90 105 dB
VS = 40 V, (VCC–) + 2.5 V <
VCM < (VCC+) TA = –40°C to +125°C 80 dB
INPUT CAPACITANCE
ZID Differential 100 || 2 MΩ || pF
ZICM Common-mode 6 || 1 TΩ || pF
OPEN-LOOP GAIN
VS = 40 V, VCM = VS / 2,
AOL Open-loop voltage gain (VCC–) + 0.3 V < VO < (VCC+) TA = –40°C to +125°C 118 125 dB
– 0.3 V
VS = 40 V, VCM = VS / 2,
AOL Open-loop voltage gain RL = 2 kΩ, (VCC–) + 1.2 V < TA = –40°C to +125°C 115 120 dB
VO < (VCC+) – 1.2 V
FREQUENCY RESPONSE
GBW Gain-bandwidth product 5.25 MHz
SR Slew rate VS = 40 V, G = +1, CL = 20 pF 20 V/μs
To 0.1%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF 0.63
To 0.1%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF 0.56
tS Settling time μs
To 0.01%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF 0.91
To 0.01%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF 0.48
Phase margin G = +1, RL = 10kΩ, CL = 20 pF 56 °
Overload recovery time VIN × gain > VS 300 ns
Total harmonic distortion +
THD+N VS = 40 V, VO = 6 VRMS, G = +1, f = 1 kHz 0.00012 %
noise
EMIRR EMI rejection ratio f = 1 GHz 53 dB

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A TL074B TL074H TL074M
TL071, TL071A, TL071B, TL071H
TL072, TL072A, TL072B, TL072H, TL072M
TL074, TL074A, TL074B, TL074H, TL074M
SLOS080W – SEPTEMBER 1978 – REVISED JULY 2025 www.ti.com

5.7 Electrical Characteristics for TL07xH (continued)

at VS = (VCC+) – (VCC–) = 4.5 V to 40 V (±2.25 V to ±20 V), TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VOUT = VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT
VS = 40 V, RL = 10 kΩ 115 210
Positive rail headroom
Voltage output swing from VS = 40 V, RL = 2 kΩ 520 965
mV
rail VS = 40 V, RL = 10 kΩ 105 215
Negative rail headroom
VS = 40 V, RL = 2 kΩ 500 1030
ISC Short-circuit current ±26 mA
CLOAD Capacitive load drive 300 pF
Open-loop output
ZO f = 1 MHz, IO = 0 A 125 Ω
impedance
POWER SUPPLY
IO = 0 A 937.5 1125
IO = 0 A, (TL071H) 960 1156
Quiescent current per
IQ IO = 0 A 1130 µA
amplifier
IO = 0 A, (TL072H) TA = –40°C to +125°C 1143
IO = 0 A, (TL071H) 1160
Turn-on time At TA = 25°C, VS = 40 V, VS ramp rate > 0.3 V/µs 60 μs

(1) Maximum IB and IOS data are specified based on characterization results.

14 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

5.8 Electrical Characteristics (DC) for TL07xC, TL07xAC, TL07xBC, TL07xI, TL07xM
at VS = (VCC+) – (VCC–) = ±15 V and TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS(1) (2) MIN TYP MAX UNIT
DC
3 10
TL07xC
TA = Full range 13
3 6
TL07xAC
TA = Full range 7.5
2 3
TL07xBC
VO = 0 V TA = Full range 5
VOS Input offset voltage mV
RS = 50 Ω 3 6
TL07xI
TA = Full range 8
3 6
TL071M, TL072M
TA = Full range 9
3 9
TL074M
TA = Full range 15
Input offset voltage
dVOS/dT VO = 0 V, RS = 50 Ω TA = Full range ±18 µV/℃
drift
5 100 pA
TL07xC
TA = Full range 10 nA

TL07xAC, TL07xBC, 5 100 pA

IOS Input offset current VO = 0 V
TL07xI TA = Full range 2 nA
5 100 pA
TL07xM
TA = Full range 20 nA

TL07xC, TL07xAC, 65 200 pA

TL07xBC, TL07xI TA = Full range 7 nA
65 200 pA
IB Input bias current VO = 0 V TL071M, TL072M
TA = Full range 50 nA
65 200 pA
TL074M
TA = Full range 20 nA
Common-mode
VCM ±11 –12 to 15 V
voltage
RL = 10 kΩ ±12 ±13.5
Maximum peak output
VOM RL ≥ 10 kΩ ±12 V
voltage swing TA = Full range
RL ≥ 2 kΩ ±10
25 200
TL07xC
TA = Full range 15

Open-loop voltage TL07xAC, TL07xBC, 50 200

AOL VO = 0 V V/mV
gain TL07xI TA = Full range 25
35 200
TL07xM
TA = Full range 15

Gain-bandwidth All NS and PS packages; All TL07xM devices 3

GBW MHz
product All other devices 5.25
Common-mode input
RID 1 TΩ
resistance
TL07xC 70 100
VIC = VICR(min)
Common-mode
CMRR VO = 0 V TL07xAC, TL07xBC, TL07xI 75 100 dB
rejection ratio
RS = 50 Ω
TL07xM 80 86
TL07xC 70 100
VS = ±9 V to ± 18 V
Input offset voltage
PSRR VO = 0 V TL07xAC, TL07xBC, TL07xI 80 100 dB
versus power supply
RS = 50 Ω
TL07xM 80 86

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A TL074B TL074H TL074M
TL071, TL071A, TL071B, TL071H
TL072, TL072A, TL072B, TL072H, TL072M
TL074, TL074A, TL074B, TL074H, TL074M
SLOS080W – SEPTEMBER 1978 – REVISED JULY 2025 www.ti.com

5.8 Electrical Characteristics (DC) for TL07xC, TL07xAC, TL07xBC, TL07xI, TL07xM (continued)
at VS = (VCC+) – (VCC–) = ±15 V and TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS(1) (2) MIN TYP MAX UNIT
Quiescent current per
IQ VO = 0 V, no load 1.4 2.5 mA
amplifier
Channel separation f = 0 Hz 1 µV/V

(1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.
(2) Full range is TA = 0°C to 70°C for the TL07xC, TL07xAC, and TL07xBC; TA = –40°C to +85°C for the TL07xI; and TA = –55°C to
+125°C for the TL07xM.

5.9 Electrical Characteristics (AC) for TL07xC, TL07xAC, TL07xBC, TL07xI, TL07xM
at VS = (VCC+) – (VCC–) = ±15 V and TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC
TL07xM 5 20 V/μs
VI = 10 V, CL = 100 pF,
SR Slew rate TL07xC, TL07xAC,
RL = 2 kΩ 8 20 V/μs
TL07xBC, TL07xI
0.1 μs
tS Settling time VI = 20 V, CL = 100 pF, RL = 2 kΩ
20%
All PS and NS packages,
RS = 20 Ω, f = 1 kHz 18 nV/√Hz
all TL07xM devices
eN Input voltage noise density
f = 1 kHz 37
All other devices nV/√Hz
f = 10 kHz 21
All PS and NS packages, RS = 20 Ω,
4 μVRMS
EN Input voltage noise all TL07xM devices f = 10 Hz to 10 kHz
All other devices f = 0.1 Hz to 10 Hz 1.4 µVRMS
iN Input current noise RS = 20 Ω, f = 1 kHz 10 fA/√Hz
TL07xC, TL07xAC, G = +1, RL = 10kΩ,
Phase margin 56 °
TL07xBC, TL07xI CL = 20 pF
Overload recovery time VIN × gain > VS 300 ns
All PS and NS packages, VO = 6 VRMS, RL ≥ 2 kΩ,
0.003 %
Total harmonic distortion + all TL07xM devices f = 1 kHz, G = +1, RS ≤ 1 kΩ
THD+N
noise VS = 40 V, VO = 6 VRMS,
All other devices 0.00012 %
G = +1, f = 1 kHz
TL07xC, TL07xAC,
EMIRR EMI rejection ratio f = 1 GHz 53 dB
TL07xBC, TL07xI
Open-loop output TL07xC, TL07xAC,
ZO f = 1 MHz, IO = 0 A 125 Ω
impedance TL07xBC, TL07xI

16 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

5.10 Typical Characteristics: TL07xH

at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted)

TA = 25°C

Figure 5-1. Offset Voltage Production Distribution Figure 5-2. Offset Voltage Drift Distribution

VCM = VS / 2 TA = 25°C

Figure 5-3. Offset Voltage vs Temperature Figure 5-4. Offset Voltage vs Common-Mode Voltage

TA = 125°C TA = –40°C

Figure 5-5. Offset Voltage vs Common-Mode Voltage Figure 5-6. Offset Voltage vs Common-Mode Voltage

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A TL074B TL074H TL074M
TL071, TL071A, TL071B, TL071H
TL072, TL072A, TL072B, TL072H, TL072M
TL074, TL074A, TL074B, TL074H, TL074M
SLOS080W – SEPTEMBER 1978 – REVISED JULY 2025 www.ti.com

5.10 Typical Characteristics: TL07xH (continued)

at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted)

Figure 5-7. Offset Voltage vs Power Supply Figure 5-8. Open-Loop Gain and Phase vs Frequency

Figure 5-9. Closed-Loop Gain vs Frequency Figure 5-10. Input Bias Current vs Common-Mode Voltage

Figure 5-11. Input Bias Current vs Temperature Figure 5-12. Output Voltage Swing vs Output Current (Sourcing)

18 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

5.10 Typical Characteristics: TL07xH (continued)

at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted)

Figure 5-13. Output Voltage Swing vs Output Current (Sinking) Figure 5-14. CMRR and PSRR vs Frequency

f = 0 Hz f = 0 Hz

Figure 5-15. CMRR vs Temperature (dB) Figure 5-16. PSRR vs Temperature (dB)

Figure 5-17. 0.1-Hz to 10-Hz Noise Figure 5-18. Input Voltage Noise Spectral Density vs Frequency

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A TL074B TL074H TL074M
TL071, TL071A, TL071B, TL071H
TL072, TL072A, TL072B, TL072H, TL072M
TL074, TL074A, TL074B, TL074H, TL074M
SLOS080W – SEPTEMBER 1978 – REVISED JULY 2025 www.ti.com

5.10 Typical Characteristics: TL07xH (continued)

at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted)

VCM = VS / 2

Figure 5-19. Quiescent Current vs Supply Voltage Figure 5-20. Quiescent Current vs Temperature

Figure 5-21. Open-Loop Voltage Gain vs Temperature Figure 5-22. Open-Loop Output Impedance vs Frequency

G = –1, 25-mV output step G = 1, 10-mV output step

Figure 5-23. Small-Signal Overshoot vs Capacitive Load Figure 5-24. Small-Signal Overshoot vs Capacitive Load

20 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

5.10 Typical Characteristics: TL07xH (continued)

at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted)

VS = ±10 V, VIN = VOUT

Figure 5-25. Phase Margin vs Capacitive Load Figure 5-26. No Phase Reversal

G = –10 G = –10

Figure 5-27. Positive Overload Recovery Figure 5-28. Negative Overload Recovery

CL = 20 pF, G = 1, 10-mV step response CL = 20 pF, G = 1, 10-mV step response

Figure 5-29. Small-Signal Step Response, Rising Figure 5-30. Small-Signal Step Response, Falling

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A TL074B TL074H TL074M
TL071, TL071A, TL071B, TL071H
TL072, TL072A, TL072B, TL072H, TL072M
TL074, TL074A, TL074B, TL074H, TL074M
SLOS080W – SEPTEMBER 1978 – REVISED JULY 2025 www.ti.com

5.10 Typical Characteristics: TL07xH (continued)

at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted)

CL = 20 pF, G = 1 CL = 20 pF, G = 1

Figure 5-31. Large-Signal Step Response (Rising) Figure 5-32. Large-Signal Step Response (Falling)

CL = 20 pF, G = 1

Figure 5-33. Large-Signal Step Response Figure 5-34. Short-Circuit Current vs Temperature

Figure 5-35. Maximum Output Voltage vs Frequency Figure 5-36. Channel Separation vs Frequency

22 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

5.10 Typical Characteristics: TL07xH (continued)

at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted)

Figure 5-37. EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A TL074B TL074H TL074M
TL071, TL071A, TL071B, TL071H
TL072, TL072A, TL072B, TL072H, TL072M
TL074, TL074A, TL074B, TL074H, TL074M
SLOS080W – SEPTEMBER 1978 – REVISED JULY 2025 www.ti.com

5.11 Typical Characteristics: All Devices Except TL07xH

100 ±15
VCC± = ±15 V VCC± = ±15 V RL = 10 kΩ

VOM − Maximum Peak Output Voltage − V

TA = 25°C
±12.5 See Figure 2
IB Input Bias Current − nA

10
±10
VCC± = ±10 V

1 ±7.5

±5 VCC± = ±5 V
IIIB−

0.1

±2.5

VOM
0.01 0
−75 −50 −25 0 25 50 75 100 125 100 1k 10 k 100 k 1M 10 M
TA − Free-Air Temperature − °C f − Frequency − Hz

Figure 5-38. Input Bias Current vs Free-Air Temperature Figure 5-39. Maximum Peak Output Voltage vs Frequency
±15
RL = 2 kΩ
VOM − Maximum Peak Output Voltage − V

VCC± = ±15 V TA = 25°C

±12.5 See Figure 2

±10

VCC± = ±10 V
±7.5

±5
VCC± = ±5 V
VOM

±2.5
8

0
100 1k 10 k 100 k 1M 10 M
f − Frequency − Hz

Figure 5-40. Maximum Peak Output Voltage vs Frequency Figure 5-41. Maximum Peak Output Voltage vs Frequency
±15 ±15
RL = 10 kΩ
VCC± = ±15 V
OM − Maximum Peak Output Voltage − V

VOM − Maximum Peak Output Voltage − V

TA = 25°C
±12.5 ±12.5 See Figure 2
RL = 2 kΩ

±10 ±10

±7.5 ±7.5

±5 ±5

±2.5 ±2.5
VOM

VOM

VCC± = ±15 V
8 8
V

See Figure 2
0 0
−75 −50 −25 0 25 50 75 100 125 0.1 0.2 0.4 0.7 1 2 4 7 10
TA − Free-Air Temperature − °C RL − Load Resistance − kΩ

Figure 5-42. Maximum Peak Output Voltage vs Free-Air Figure 5-43. Maximum Peak Output Voltage vs Load Resistance
Temperature

24 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

5.11 Typical Characteristics: All Devices Except TL07xH (continued)

±15 1000
RL = 10 kΩ
VOM − Maximum Peak Output Voltage − V

TA = 25°C 400
±12.5

VD − Large-Signal Differential
Voltage Amplification − V/mV
200

±10 100

40
±7.5
20

±5 10

AAVD
4 VCC± = ±15 V
±2.5
VOM

VO = ±10 V
2 RL = 2 kΩ
0 1
0 2 4 6 8 10 12 14 16 −75 −50 −25 0 25 50 75 100 125
|VCC±| − Supply Voltage − V TA − Free-Air Temperature − °C

Figure 5-44. Maximum Peak Output Voltage vs Supply Voltage Figure 5-45. Large-Signal Differential Voltage Amplification vs
Free-Air Temperature
1.3 1.03

1.2 Unity-Gain Bandwidth 1.02

Normalized Unity-Gain Bandwidth

Normalized Phase Shift

1.1 1.01

Phase Shift 1
1

0.9 0.99

VCC± = ±15 V
0.8 0.98
RL = 2 kΩ
f = B1 for Phase Shift

0.7 0.97
−75 −50 −25 0 25 50 75 100 125
TA − Free-Air Temperature − °C

Figure 5-46. Large-Signal Differential Voltage Amplification and Figure 5-47. Normalized Unity-Gain Bandwidth and Phase Shift
Phase Shift vs Frequency vs Free-Air Temperature
89 2
VCC± = ±15 V
CMRR − Common-Mode Rejection Ratio − dB

TA = 25°C
ICC − Supply Current Per Amplifier − mA

RL = 10 kΩ 1.8 No Signal
88 No Load
1.6

1.4
87
1.2

86 1

0.8
85
0.6

0.4
84
I CC±

0.2

83 0
−75 −50 −25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16
TA − Free-Air Temperature − °C |VCC±| − Supply Voltage − V

Figure 5-48. Common-Mode Rejection Ratio vs Free-Air Figure 5-49. Supply Current Per Amplifier vs Supply Voltage
Temperature

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A TL074B TL074H TL074M
TL071, TL071A, TL071B, TL071H
TL072, TL072A, TL072B, TL072H, TL072M
TL074, TL074A, TL074B, TL074H, TL074M
SLOS080W – SEPTEMBER 1978 – REVISED JULY 2025 www.ti.com

5.11 Typical Characteristics: All Devices Except TL07xH (continued)

2 250
VCC± = ±15 V VCC± =±15 V
ICC − Supply Current Per Amplifier − mA

1.8 No Signal 225 No Signal

PD − Total Power Dissipation − mW

No Load No Load
1.6 200

1.4 175
TL074
1.2 150

1 125

0.8 100
TL072
0.6 75

0.4 50 TL071
I CC±

0.2 25

0 0
−75 −50 −25 0 25 50 75 100 125 −75 −50 −25 0 25 50 75 100 125
TA − Free-Air Temperature − °C TA − Free-Air Temperature −C
°

Figure 5-50. Supply Current Per Amplifier vs Free-Air Figure 5-51. Total Power Dissipation vs Free-Air Temperature
Temperature
50

nV/ Hz
VCC± = ±15 V

V n − Equivalent Input Noise Voltage − nV/Hz

AVD = 10
RS = 20 Ω
40 TA = 25°C

0
10 40 100 400 1 k 4 k 10 k 40 k 100 k
f − Frequency − Hz

Figure 5-52. Normalized Slew Rate vs Free-Air Temperature Figure 5-53. Equivalent Input Noise Voltage vs Frequency
1 6
VCC± = ±15 V VCC± = ±15 V
VI and VO − Input and Output Voltages − V

AVD = 1 RL = 2 kΩ
0.4
THD − Total Harmonic Distortion − %

VI(RMS) = 6 V 4 CL = 100 pF
TA = 25°C TA = 25°C
Output
0.1 2

0.04
0

0.01 −2
Input
0.004
−4

0.001 −6
100 400 1k 4 k 10 k 40 k 100 k 0 0.5 1 1.5 2 2.5 3 3.5
f − Frequency − Hz t − Time − µs

Figure 5-54. Total Harmonic Distortion vs Frequency Figure 5-55. Voltage-Follower Large-Signal Pulse Response

26 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

5.11 Typical Characteristics: All Devices Except TL07xH (continued)

10
VCCr = r15 V
8

VIO (mV)
0

-2

-4

-6

-8

-10
-13 -11 -9 -7 -5 -3 -1 1 3 5 7 9 11 13 15 17
VCM (V) D003

Figure 5-56. Output Voltage vs Elapsed Time Figure 5-57. VIO vs VCM

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A TL074B TL074H TL074M
TL071, TL071A, TL071B, TL071H
TL072, TL072A, TL072B, TL072H, TL072M
TL074, TL074A, TL074B, TL074H, TL074M
SLOS080W – SEPTEMBER 1978 – REVISED JULY 2025 www.ti.com

6 Parameter Measurement Information

OUT
VI +

CL = 100 pF RL = 2 kΩ

Figure 6-1. Unity-Gain Amplifier

10 kΩ

1 kΩ
−
VI
OUT
+
RL CL = 100 pF

Figure 6-2. Gain-of-10 Inverting Amplifier

Figure 6-3. Input Offset-Voltage Null Circuit

for PS Package (SO, 8) Only

28 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

7 Detailed Description
7.1 Overview
The TL07xH (TL071H, TL072H, and TL074H) family of devices are the next-generation versions of the industry-
standard TL07x (TL071, TL072, and TL074) devices. These devices provide outstanding value for cost-sensitive
applications, with features including low offset (1 mV, typical), high slew rate (20 V/μs, typical), and common-
mode input to the positive supply. High ESD (2 kV, HBM), integrated EMI and RF filters, and operation across
the full –40°C to 125°C enable the TL07xH devices to be used in the most rugged and demanding applications.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from −40°C to +85°C. The M-suffix devices are characterized for operation over the full military
temperature range of −55°C to +125°C.
7.2 Functional Block Diagram
V+

V V
IN+ IN–

V Class AB
BIAS1
Control V
O
Circuitry
V
BIAS2

Reference
Current

V–
(Ground)

7.3 Feature Description

The TL07xH family of devices improve many specifications as compared to the industry-standard TL07x family.
Several comparisons of key specifications between these families are included in the following sections to show
the advantages of the TL07xH family.
7.3.1 Total Harmonic Distortion
Harmonic distortions to an audio signal are created by electronic components in a circuit. Total harmonic
distortion (THD) is a measure of harmonic distortions accumulated by a signal in an audio system. These
devices have a very low THD of 0.003% meaning that the TL07x device adds little harmonic distortion when
used in audio signal applications.
7.3.2 Slew Rate
The slew rate is the rate at which an operational amplifier can change the output when there is a change on the
input. These devices have a 20-V/μs slew rate.
7.4 Device Functional Modes
These devices are powered on when the supply is connected. These devices can be operated as a single-supply
operational amplifier or dual-supply amplifier depending on the application.

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A TL074B TL074H TL074M
TL071, TL071A, TL071B, TL071H
TL072, TL072A, TL072B, TL072H, TL072M
TL074, TL074A, TL074B, TL074H, TL074M
SLOS080W – SEPTEMBER 1978 – REVISED JULY 2025 www.ti.com

8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information

A typical application for an operational amplifier is an inverting amplifier. This amplifier takes a positive voltage
on the input, and makes the voltage a negative voltage. In the same manner, the amplifier makes negative
voltages positive.
8.2 Typical Applications
8.2.1 Inverting Amplifier
RF

RI Vsup+

VOUT
+
VIN
Vsup-

Figure 8-1. Inverting Amplifier

8.2.1.1 Design Requirements

The supply voltage must be selected so the supply voltage is larger than the input voltage range and output
range. For instance, this application scales a signal of ±0.5 V to ±1.8 V. Setting the supply at ±12 V is sufficient
to accommodate this application.
8.2.1.2 Detailed Design Procedure
Determine the gain required by the inverting amplifier:

AV = VOUT
VIN (1)

1.8
AV = −0.5 = − 3.6 (2)

After the desired gain is determined, select a value for RI or RF. Selecting a value in the kilohm range is
desirable because the amplifier circuit uses currents in the milliamp range. This example uses 10 kΩ for RI,
which means 36 kΩ is used for RF. The gain is determined by Equation 3.

AV = − RF
RI (3)

30 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

8.2.1.3 Application Curve

2
VIN
1.5
VOUT
1

0.5
Volts
0

-0.5

-1

-1.5

-2
0 0.5 1 1.5 2
Time (ms)
Figure 8-2. Input and Output Voltages of the Inverting Amplifier

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 31

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A TL074B TL074H TL074M
TL071, TL071A, TL071B, TL071H
TL072, TL072A, TL072B, TL072H, TL072M
TL074, TL074A, TL074B, TL074H, TL074M
SLOS080W – SEPTEMBER 1978 – REVISED JULY 2025 www.ti.com

8.3 Power Supply Recommendations

CAUTION
Supply voltages larger than 36 V for a single-supply or outside the range of ±18 V for a dual-supply
can permanently damage the device (see Section 5.1).

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or
high-impedance power supplies. For more detailed information on bypass capacitor placement, see Section 8.4.
8.4 Layout
8.4.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from VCC+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are typically devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to physically separate
digital and analog grounds, paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible.
If not possible, then better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy
trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance; see also Section 8.4.2.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.

32 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

8.4.2 Layout Example

Place components close to
device and to each other to
reduce parasitic errors
Run the input traces as far
away from the supply lines RF
as possible
NC NC VS+
Use low-ESR, ceramic
RG bypass capacitor
GND IN1í VCC+

VIN IN1+ OUT

RIN
VCCí NC GND
Only needed for
dual-supply
operation
GND VS-
(or GND for single supply) VOUT Ground (GND) plane on another layer

Figure 8-3. Operational Amplifier Board Layout for Noninverting Configuration

RIN
VIN +
VOUT

RG RF

Figure 8-4. Operational Amplifier Schematic for Noninverting Configuration

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 33

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A TL074B TL074H TL074M
TL071, TL071A, TL071B, TL071H
TL072, TL072A, TL072B, TL072H, TL072M
TL074, TL074A, TL074B, TL074H, TL074M
SLOS080W – SEPTEMBER 1978 – REVISED JULY 2025 www.ti.com

9 Device and Documentation Support

9.1 Device Support
9.1.1 Device Nomenclature
Table 9-1. Device Nomenclature
PART NUMBER DEFINITION
x is the channel count
If y = H, the die is manufactured on the latest flow (CSO: RFB).
Section 5.7 and Section 5.10 describe the performance of the new die.
If y ≠ H and y ≠ M, the die is manufactured on the legacy flow (CSO: SFAB) or the latest flow (CSO: RFB).
Section 5.8, Section 5.9, and Section 5.11 describe the performance of the original die.
TL07xyzzzzzz
Section 5.7 and Section 5.10 describe the performance of the new die.
If y = M, the device is specified for the extended temperature range of –55°C to +125°C. The die is
manufactured on the legacy flow (CSO:SFAB).
The letters and numbers represented by z are grade-out and package options described in Section 5.8 and
the Package Option Addendum at the end of this data sheet.

9.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

9.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision V (April 2023) to Revision W (July 2025) Page
• Deleted references to trim function from all packages except PS (SO, 8) package...........................................1
• Changed Vn from 18nV/√Hz to 37nV/√Hz in Features ...................................................................................... 1
• Updated Device Information table to match Package Option Addendum ......................................................... 1
• Updated front page image to show which device uses the PS package only.................................................... 1
• Updated Pin Configuration and Functions to show that only PS package (PDIP, 8) has trim function...............3

34 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

• Added note regarding old and new dies...........................................................................................................10

• Deleted Figure 5-19, THD+N Ratio vs Frequency and Figure 5-20, THD+N vs Output Amplitude .................17
• Added "for PS Package (SO, 8) Only" to Figure 7-3 caption............................................................................28
• Deleted Unity Gain Buffer and System Examples sections..............................................................................30
• Deleted Equation 1 from Detailed Design Procedure ......................................................................................30
• Deleted "This ensures the part does not draw too much current." from Detailed Design Procedure .............. 30
• Added Device Nomenclature table................................................................................................................... 34

Changes from Revision U (December 2022) to Revision V (April 2023) Page

• Updated Overview, Functional Block Diagram, and Feature Description sections ......................................... 29

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 35

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A TL074B TL074H TL074M
PACKAGE OPTION ADDENDUM

www.ti.com 12-Sep-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

81023052A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 81023052A
TL072MFKB
8102305HA Active Production CFP (U) | 10 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8102305HA
TL072M
8102305PA Active Production CDIP (JG) | 8 50 | TUBE No SNPB N/A for Pkg Type -55 to 125 8102305PA
TL072M
81023062A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 81023062A
TL074MFKB
8102306CA Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8102306CA
TL074MJB
8102306DA Active Production CFP (W) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8102306DA
TL074MWB
JM38510/11905BPA Active Production CDIP (JG) | 8 50 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510
/11905BPA
JM38510/11905BPA.A Active Production CDIP (JG) | 8 50 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510
/11905BPA
M38510/11905BPA Active Production CDIP (JG) | 8 50 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510
/11905BPA
TL071ACDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 071AC
TL071ACDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 071AC
TL071ACP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL071ACP
TL071ACP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL071ACP
TL071BCDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 071BC
TL071BCDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 071BC
TL071BCP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL071BCP
TL071BCP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL071BCP
TL071CDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL071C
TL071CDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL071C
TL071CDRE4 Active Production SOIC (D) | 8 2500 | LARGE T&R - Call TI Call TI 0 to 70
TL071CDRG4 Active Production SOIC (D) | 8 2500 | LARGE T&R - Call TI Call TI 0 to 70
TL071CP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL071CP

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 12-Sep-2025

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

TL071CP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL071CP
TL071CPE4 Active Production PDIP (P) | 8 50 | TUBE - Call TI Call TI 0 to 70
TL071CPSR Active Production SO (PS) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T071
TL071CPSR.A Active Production SO (PS) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T071
TL071HIDBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 T71V
TL071HIDBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T71V
TL071HIDBVR.B Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T71V
TL071HIDBVRG4 Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T71V
TL071HIDBVRG4.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T71V
TL071HIDCKR Active Production SC70 (DCK) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 1IO
TL071HIDCKR.A Active Production SC70 (DCK) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 1IO
TL071HIDR Active Production SOIC (D) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL071D
TL071HIDR.A Active Production SOIC (D) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL071D
TL071IDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL071I
TL071IDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL071I
TL071IDR1G4 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL071I
TL071IDR1G4.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL071I
TL071IDRG4 Active Production SOIC (D) | 8 2500 | LARGE T&R - Call TI Call TI -40 to 85
TL071IP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL071IP
TL071IP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL071IP
TL072ACDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 072AC
TL072ACDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 072AC
TL072ACDRE4 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 072AC
TL072ACDRG4 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 072AC
TL072ACP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL072ACP
TL072ACP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL072ACP
TL072ACPE4 Active Production PDIP (P) | 8 50 | TUBE - Call TI Call TI 0 to 70
TL072ACPS Active Production SO (PS) | 8 80 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T072A
TL072ACPS.A Active Production SO (PS) | 8 80 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T072A
TL072BCD Obsolete Production SOIC (D) | 8 - - Call TI Call TI 0 to 70 072BC
TL072BCDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 072BC

Addendum-Page 2
PACKAGE OPTION ADDENDUM

www.ti.com 12-Sep-2025

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

TL072BCDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 072BC
TL072BCP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL072BCP
TL072BCP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL072BCP
TL072CDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL072C
TL072CDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL072C
TL072CP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL072CP
TL072CP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL072CP
TL072CPS Active Production SO (PS) | 8 80 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T072
TL072CPS.A Active Production SO (PS) | 8 80 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T072
TL072CPSR Active Production SO (PS) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T072
TL072CPSR.A Active Production SO (PS) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T072
TL072CPSRG4 Active Production SO (PS) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T072
TL072CPWR Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T072
TL072CPWR.A Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T072
TL072CPWRE4 Active Production TSSOP (PW) | 8 2000 | LARGE T&R - Call TI Call TI 0 to 70
TL072CPWRG4 Active Production TSSOP (PW) | 8 2000 | LARGE T&R - Call TI Call TI 0 to 70
TL072HIDDFR Active Production SOT-23-THIN (DDF) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 O72F
TL072HIDDFR.A Active Production SOT-23-THIN (DDF) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 O72F
TL072HIDDFR.B Active Production SOT-23-THIN (DDF) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 O72F
TL072HIDR Active Production SOIC (D) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL072D
TL072HIDR.A Active Production SOIC (D) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL072D
TL072HIPWR Active Production TSSOP (PW) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 072HPW
TL072HIPWR.A Active Production TSSOP (PW) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 072HPW
TL072IDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL072I
TL072IDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL072I
TL072IP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL072IP
TL072IP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL072IP
TL072IPE4 Active Production PDIP (P) | 8 50 | TUBE - Call TI Call TI -40 to 85
TL072MFKB Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 81023052A
TL072MFKB

Addendum-Page 3
PACKAGE OPTION ADDENDUM

www.ti.com 12-Sep-2025

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

TL072MFKB.A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 81023052A
TL072MFKB
TL072MJG Active Production CDIP (JG) | 8 50 | TUBE No SNPB N/A for Pkg Type -55 to 125 TL072MJG
TL072MJG.A Active Production CDIP (JG) | 8 50 | TUBE No SNPB N/A for Pkg Type -55 to 125 TL072MJG
TL072MJGB Active Production CDIP (JG) | 8 50 | TUBE No SNPB N/A for Pkg Type -55 to 125 8102305PA
TL072M
TL072MJGB.A Active Production CDIP (JG) | 8 50 | TUBE No SNPB N/A for Pkg Type -55 to 125 8102305PA
TL072M
TL072MUB Active Production CFP (U) | 10 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8102305HA
TL072M
TL072MUB.A Active Production CFP (U) | 10 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8102305HA
TL072M
TL074ACDR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC
TL074ACDR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC
TL074ACN Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL074ACN
TL074ACN.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL074ACN
TL074ACNSR Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL074A
TL074ACNSR.A Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL074A
TL074BCD Obsolete Production SOIC (D) | 14 - - Call TI Call TI 0 to 70 TL074BC
TL074BCDR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL074BC
TL074BCDR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL074BC
TL074BCDR.B Active Production SOIC (D) | 14 2500 | LARGE T&R - Call TI Call TI 0 to 70
TL074BCDRE4 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL074BC
TL074BCDRG4 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL074BC
TL074BCN Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL074BCN
TL074BCN.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL074BCN
TL074CD Obsolete Production SOIC (D) | 14 - - Call TI Call TI 0 to 70 TL074C
TL074CDBR Active Production SSOP (DB) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T074
TL074CDBR.A Active Production SSOP (DB) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T074
TL074CDR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL074C
TL074CDR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL074C
TL074CDR.B Active Production SOIC (D) | 14 2500 | LARGE T&R - Call TI Call TI -40 to 85

Addendum-Page 4
PACKAGE OPTION ADDENDUM

www.ti.com 12-Sep-2025

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

TL074CDRG4 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL074C
TL074CDRG4.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL074C
TL074CN Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL074CN
TL074CN.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL074CN
TL074CNSR Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL074
TL074CNSR.A Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL074
TL074CPW Obsolete Production TSSOP (PW) | 14 - - Call TI Call TI 0 to 70 T074
TL074CPWR Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T074
TL074CPWR.A Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T074
TL074CPWRE4 Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T074
TL074CPWRG4 Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T074
TL074HIDR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL074HID
TL074HIDR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL074HID
TL074HIDR.B Active Production SOIC (D) | 14 2500 | LARGE T&R - Call TI Call TI -40 to 125
TL074HIDRG4 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL074HID
TL074HIDRG4.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL074HID
TL074HIDYYR Active Production SOT-23-THIN 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T074HDYY
(DYY) | 14
TL074HIDYYR.A Active Production SOT-23-THIN 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T074HDYY
(DYY) | 14
TL074HIDYYR.B Active Production SOT-23-THIN 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T074HDYY
(DYY) | 14
TL074HIPWR Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL074PW
TL074HIPWR.A Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL074PW
TL074ID Obsolete Production SOIC (D) | 14 - - Call TI Call TI -40 to 85 TL074I
TL074IDR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL074I
TL074IDR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL074I
TL074IDR.B Active Production SOIC (D) | 14 2500 | LARGE T&R - Call TI Call TI -40 to 85
TL074IDRE4 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL074I
TL074IDRG4 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL074I
TL074IN Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL074IN

Addendum-Page 5
PACKAGE OPTION ADDENDUM

www.ti.com 12-Sep-2025

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

TL074IN.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL074IN
TL074ING4 Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL074IN
TL074ING4.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL074IN
TL074MFK Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 TL074MFK
TL074MFK.A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 TL074MFK
TL074MFKB Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 81023062A
TL074MFKB
TL074MFKB.A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 81023062A
TL074MFKB
TL074MJ Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 TL074MJ
TL074MJ.A Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 TL074MJ
TL074MJB Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8102306CA
TL074MJB
TL074MJB.A Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8102306CA
TL074MJB
TL074MWB Active Production CFP (W) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8102306DA
TL074MWB
TL074MWB.A Active Production CFP (W) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8102306DA
TL074MWB

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

Addendum-Page 6
PACKAGE OPTION ADDENDUM

www.ti.com 12-Sep-2025

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TL072, TL072M, TL074, TL074M :

• Catalog : TL072, TL074

• Enhanced Product : TL072-EP, TL072-EP, TL074-EP, TL074-EP
• Military : TL072M, TL074M

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications

Addendum-Page 7
PACKAGE MATERIALS INFORMATION

www.ti.com 6-Sep-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TL071ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL071BCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL071CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL071CPSR SO PS 8 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
TL071HIDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TL071HIDBVRG4 SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TL071HIDCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
TL071HIDR SOIC D 8 3000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL071IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL071IDR1G4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL072ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL072ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL072BCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL072CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL072CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL072CPSR SO PS 8 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 6-Sep-2025

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TL072CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TL072HIDDFR SOT-23- DDF 8 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
THIN
TL072HIDR SOIC D 8 3000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL072HIPWR TSSOP PW 8 3000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TL072IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL072IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL074ACDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL074ACDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL074ACNSR SOP NS 14 2000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 Q1
TL074BCDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL074BCDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL074CDBR SSOP DB 14 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
TL074CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL074CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL074CDRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL074CDRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL074CNSR SOP NS 14 2000 330.0 16.4 8.45 10.55 2.5 12.0 16.2 Q1
TL074CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TL074CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TL074HIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL074HIDRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL074HIDYYR SOT-23- DYY 14 3000 330.0 12.4 4.8 3.6 1.6 8.0 12.0 Q3
THIN
TL074HIPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TL074IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 6-Sep-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL071ACDR SOIC D 8 2500 353.0 353.0 32.0
TL071BCDR SOIC D 8 2500 353.0 353.0 32.0
TL071CDR SOIC D 8 2500 353.0 353.0 32.0
TL071CPSR SO PS 8 2000 353.0 353.0 32.0
TL071HIDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TL071HIDBVRG4 SOT-23 DBV 5 3000 210.0 185.0 35.0
TL071HIDCKR SC70 DCK 5 3000 190.0 190.0 30.0
TL071HIDR SOIC D 8 3000 353.0 353.0 32.0
TL071IDR SOIC D 8 2500 353.0 353.0 32.0
TL071IDR1G4 SOIC D 8 2500 353.0 353.0 32.0
TL072ACDR SOIC D 8 2500 353.0 353.0 32.0
TL072ACDR SOIC D 8 2500 353.0 353.0 32.0
TL072BCDR SOIC D 8 2500 353.0 353.0 32.0
TL072CDR SOIC D 8 2500 353.0 353.0 32.0
TL072CDR SOIC D 8 2500 353.0 353.0 32.0
TL072CPSR SO PS 8 2000 353.0 353.0 32.0
TL072CPWR TSSOP PW 8 2000 353.0 353.0 32.0
TL072HIDDFR SOT-23-THIN DDF 8 3000 210.0 185.0 35.0

Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION

www.ti.com 6-Sep-2025

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL072HIDR SOIC D 8 3000 353.0 353.0 32.0
TL072HIPWR TSSOP PW 8 3000 353.0 353.0 32.0
TL072IDR SOIC D 8 2500 353.0 353.0 32.0
TL072IDR SOIC D 8 2500 353.0 353.0 32.0
TL074ACDR SOIC D 14 2500 353.0 353.0 32.0
TL074ACDR SOIC D 14 2500 353.0 353.0 32.0
TL074ACNSR SOP NS 14 2000 353.0 353.0 32.0
TL074BCDR SOIC D 14 2500 353.0 353.0 32.0
TL074BCDR SOIC D 14 2500 353.0 353.0 32.0
TL074CDBR SSOP DB 14 2000 353.0 353.0 32.0
TL074CDR SOIC D 14 2500 353.0 353.0 32.0
TL074CDR SOIC D 14 2500 353.0 353.0 32.0
TL074CDRG4 SOIC D 14 2500 353.0 353.0 32.0
TL074CDRG4 SOIC D 14 2500 340.5 336.1 32.0
TL074CNSR SOP NS 14 2000 353.0 353.0 32.0
TL074CPWR TSSOP PW 14 2000 353.0 353.0 32.0
TL074CPWR TSSOP PW 14 2000 353.0 353.0 32.0
TL074HIDR SOIC D 14 2500 353.0 353.0 32.0
TL074HIDRG4 SOIC D 14 2500 353.0 353.0 32.0
TL074HIDYYR SOT-23-THIN DYY 14 3000 336.6 336.6 31.8
TL074HIPWR TSSOP PW 14 2000 353.0 353.0 32.0
TL074IDR SOIC D 14 2500 353.0 353.0 32.0

Pack Materials-Page 4
PACKAGE MATERIALS INFORMATION

www.ti.com 6-Sep-2025

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
81023052A FK LCCC 20 55 506.98 12.06 2030 NA
8102305HA U CFP 10 25 506.98 26.16 6220 NA
81023062A FK LCCC 20 55 506.98 12.06 2030 NA
8102306DA W CFP 14 25 506.98 26.16 6220 NA
TL071ACP P PDIP 8 50 506 13.97 11230 4.32
TL071ACP.A P PDIP 8 50 506 13.97 11230 4.32
TL071BCP P PDIP 8 50 506 13.97 11230 4.32
TL071BCP.A P PDIP 8 50 506 13.97 11230 4.32
TL071CP P PDIP 8 50 506 13.97 11230 4.32
TL071CP.A P PDIP 8 50 506 13.97 11230 4.32
TL071IP P PDIP 8 50 506 13.97 11230 4.32
TL071IP.A P PDIP 8 50 506 13.97 11230 4.32
TL072ACP P PDIP 8 50 506 13.97 11230 4.32
TL072ACP.A P PDIP 8 50 506 13.97 11230 4.32
TL072ACPS PS SOP 8 80 530 10.5 4000 4.1
TL072ACPS.A PS SOP 8 80 530 10.5 4000 4.1
TL072BCP P PDIP 8 50 506 13.97 11230 4.32
TL072BCP.A P PDIP 8 50 506 13.97 11230 4.32
TL072CP P PDIP 8 50 506 13.97 11230 4.32
TL072CP.A P PDIP 8 50 506 13.97 11230 4.32
TL072CPS PS SOP 8 80 530 10.5 4000 4.1
TL072CPS.A PS SOP 8 80 530 10.5 4000 4.1
TL072IP P PDIP 8 50 506 13.97 11230 4.32
TL072IP.A P PDIP 8 50 506 13.97 11230 4.32
TL072MFKB FK LCCC 20 55 506.98 12.06 2030 NA
TL072MFKB.A FK LCCC 20 55 506.98 12.06 2030 NA
TL072MUB U CFP 10 25 506.98 26.16 6220 NA
TL072MUB.A U CFP 10 25 506.98 26.16 6220 NA
TL074ACN N PDIP 14 25 506 13.97 11230 4.32

Pack Materials-Page 5
PACKAGE MATERIALS INFORMATION

www.ti.com 6-Sep-2025

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TL074ACN N PDIP 14 25 506 13.97 11230 4.32
TL074ACN.A N PDIP 14 25 506 13.97 11230 4.32
TL074ACN.A N PDIP 14 25 506 13.97 11230 4.32
TL074BCN N PDIP 14 25 506 13.97 11230 4.32
TL074BCN N PDIP 14 25 506 13.97 11230 4.32
TL074BCN.A N PDIP 14 25 506 13.97 11230 4.32
TL074BCN.A N PDIP 14 25 506 13.97 11230 4.32
TL074CN N PDIP 14 25 506 13.97 11230 4.32
TL074CN.A N PDIP 14 25 506 13.97 11230 4.32
TL074IN N PDIP 14 25 506 13.97 11230 4.32
TL074IN.A N PDIP 14 25 506 13.97 11230 4.32
TL074ING4 N PDIP 14 25 506 13.97 11230 4.32
TL074ING4.A N PDIP 14 25 506 13.97 11230 4.32
TL074MFK FK LCCC 20 55 506.98 12.06 2030 NA
TL074MFK.A FK LCCC 20 55 506.98 12.06 2030 NA
TL074MFKB FK LCCC 20 55 506.98 12.06 2030 NA
TL074MFKB.A FK LCCC 20 55 506.98 12.06 2030 NA
TL074MWB W CFP 14 25 506.98 26.16 6220 NA
TL074MWB.A W CFP 14 25 506.98 26.16 6220 NA

Pack Materials-Page 6
PACKAGE OUTLINE
DB0014A SCALE 2.000
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

C
8.2
TYP
A 7.4
0.1 C
PIN 1 INDEX AREA SEATING
PLANE
12X 0.65
14
1

2X
6.5
3.9
5.9
NOTE 3

7
8 0.38
14X
0.22
0.15 C A B
5.6
B
5.0
NOTE 4

0.25
0.09

SEE DETAIL A
2 MAX
0.25
GAGE PLANE

0.95 0.05 MIN

0 -8 0.55

DETAIL A
A 15

TYPICAL

4220762/A 05/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-150.

www.ti.com
EXAMPLE BOARD LAYOUT
DB0014A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

14X (1.85) SYMM

1 (R0.05) TYP

14X (0.45) 14

SYMM

12X (0.65)

7 8

(7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4220762/A 05/2024
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
DB0014A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

14X (1.85) SYMM

(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220762/A 05/2024
NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
GENERIC PACKAGE VIEW
FK 20 LCCC - 2.03 mm max height
8.89 x 8.89, 1.27 mm pitch LEADLESS CERAMIC CHIP CARRIER

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229370\/A\

www.ti.com
PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
PACKAGE OUTLINE
DCK0005A SCALE 5.600
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

C
2.4
1.8 0.1 C
1.4
B A 1.1 MAX
PIN 1 1.1
INDEX AREA

1 5

2X 0.65 NOTE 4

2.15
1.3 (0.15) 1.3
2 1.85

(0.1)

4
0.33 3
5X
0.15
0.1 C A B 4X 0 -12 0.1
(0.9) TYP
NOTE 5 0.0

4X 4 -15

0.15
GAGE PLANE 0.22
TYP
0.08

8 0.46
TYP TYP
0 0.26
SEATING PLANE

4214834/G 11/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
5. Lead width does not comply with JEDEC.
6. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.25mm per side

www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

PKG
5X (0.95)

1
5
5X (0.4)

SYMM
(1.3)
2
2X (0.65)

3 4

(R0.05) TYP (2.2)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:18X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214834/G 11/2024

NOTES: (continued)

7. Publication IPC-7351 may have alternate designs.

8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

PKG
5X (0.95)
1
5
5X (0.4)

SYMM
(1.3)
2
2X(0.65)

3 4

(R0.05) TYP
(2.2)

SOLDER PASTE EXAMPLE

BASED ON 0.125 THICK STENCIL
SCALE:18X

4214834/G 11/2024

NOTES: (continued)

9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
10. Board assembly site may have different recommendations for stencil design.

www.ti.com
PACKAGE OUTLINE
DDF0008A SCALE 4.000
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE

C
2.95 SEATING PLANE
TYP
2.65

A PIN 1 ID 0.1 C
AREA

6X 0.65
8
1

2.95
2.85 2X
NOTE 3 1.95

4 4X 0 -15
5
0.38
8X
0.22
1.65 0.1 C A B
B 1.1
1.55
MAX

4X 4 -15

0.20
TYP
0.08

SEE DETAIL A

0.25
GAGE PLANE

0.1
0 -8 0.6 0.0
0.3
DETAIL A
TYPICAL

4222047/E 07/2024

NOTES:

www.ti.com
EXAMPLE BOARD LAYOUT
DDF0008A SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE

8X (1.05)
SYMM
1
8

8X (0.45)
SYMM

6X (0.65)
5
4

(R0.05)
TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.05 MAX EXPOSED EXPOSED

METAL 0.05 MIN
ALL AROUND ALL AROUND METAL

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4222047/E 07/2024
NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
DDF0008A SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE

8X (1.05) SYMM
(R0.05) TYP
1
8

8X (0.45)
SYMM

6X (0.65)
5
4

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4222047/E 07/2024
NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.

www.ti.com
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
PACKAGE OUTLINE
PW0014A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
12X 0.65
14
1

2X
5.1 3.9
4.9
NOTE 3

4X (0 -12 )
7
8
0.30
14X
0.17
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220202/B 12/2023

NOTES:

www.ti.com
EXAMPLE BOARD LAYOUT
PW0014A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

14X (1.5) SYMM

(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220202/B 12/2023
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
PW0014A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

14X (1.5) SYMM

(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220202/B 12/2023
NOTES: (continued)

www.ti.com
PACKAGE OUTLINE
PW0008A SCALE 2.800
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

C
6.6 SEATING PLANE
TYP
6.2

A PIN 1 ID 0.1 C
AREA
6X 0.65
8
1

3.1 2X
2.9
NOTE 3 1.95

4
5
0.30
8X
0.19
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE

0.75 0.15
0 -8 0.05
0.50

DETAIL A
TYPICAL

4221848/A 02/2015

NOTES:

www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

8X (1.5)
8X (0.45) SYMM
(R0.05)
1 TYP
8

SYMM

6X (0.65)
5
4

(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221848/A 02/2015
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

8X (1.5)
SYMM (R0.05) TYP
8X (0.45)
1
8

SYMM

6X (0.65)
5
4

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:10X

4221848/A 02/2015
NOTES: (continued)

www.ti.com
PACKAGE OUTLINE
JG0008A CDIP - 5.08 mm max height
CERAMIC DUAL IN-LINE PACKAGE

7.11
B 1.60
A 6.22
0.38

6X 2.54

1.65
10.16 4X
1.14
9.00

4X (0.94)

0.58
8X
0.51 3.30 0.38
MIN MIN 0.25 C A B

5.08 MAX
7.87 SEATING PLANE
7.37 C

0.36 0 -15 TYP

TYP
0.20

4230036/A 09/2023
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package can be hermetically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification.
5. Falls within MIL STD 1835 GDIP1-T8

www.ti.com
EXAMPLE BOARD LAYOUT
JG0008A CDIP - 5.08 mm max height
CERAMIC DUAL IN-LINE PACKAGE

(7.62)

0.05 MAX
ALL AROUND
TYP
1 8
(1.6)

6X (2.54) (R0.05) TYP

SYMM

7X ( 1.6)

8X ( 1)
THRU

METAL
TYP 5
4

SOLDER MASK
OPENING SYMM
TYP

LAND PATTERN EXAMPLE

NON SOLDER MASK DEFINED
SCALE: 9X

4230036/A 09/2023

www.ti.com
PACKAGE OUTLINE
U0010A SCALE 1.400
CFP - 2.03 mm max height
CERAMIC FLATPACK

.27 MAX .005 MIN

.045 MAX .010 .002 PIN 1 ID GLASS TYP
TYP
1

10
8X .050 .005

.27 MAX
GLASS

10X .017 .002 5 6

+.019
5X .32 .01 .241 5X .32 .01
-.003

.005 .001
+.013
.067
-.012

.045
.026

4225582/A 01/2020

NOTES:

1. All linear dimensions are in inches. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1 5

2X 0.95 (0.1)
3.05
2.75
1.9 1.9
2
(0.15)

4
3
0.5
5X
0.3
0.15
0.2 C A B NOTE 5 4X 0 -15 (1.1) TYP
0.00
1.45
0.90
4X 4 -15

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/K 08/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.

www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/K 08/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/K 08/2024

NOTES: (continued)

www.ti.com
PACKAGE OUTLINE
DYY0014A SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE

3.36 C
3.16 SEATING PLANE

A PIN 1 INDEX
AREA 0.1 C

12X 0.5
14
1

4.3 2X
4.1
NOTE 3 3

7
8 4X 0° - 15°

1.1 MAX
14X 0.3
0.11
B 2.1
1.9 0.1 C A B

4X 4° - 15°

0.2 TYP
0.08

SEE DETAIL A

0.25
GAUGE PLANE

0°- 8° 0.63 0.1

0.33 0.0
DETAIL A
TYP

4224643/D 07/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side.
5. Reference JEDEC Registration MO-345, Variation AB

www.ti.com
EXAMPLE BOARD LAYOUT
DYY0014A SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE

SYMM
14X (1.05)

1 14

14X (0.3)

SYMM

12X (0.5)

8
7

(R0.05) TYP
(3)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 20X

SOLDER MASK METAL UNDER

OPENING SOLDER MASK SOLDER MASK
METAL OPENING

NON- SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4224643/D 07/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
DYY0014A SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE

SYMM
14X (1.05)

1 14

14X (0.3)

SYMM

12X (0.5)

8
7

(R0.05) TYP
(3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 20X

4224643/D 07/2024

NOTES: (continued)

www.ti.com
PACKAGE OUTLINE
D0014A SCALE 1.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

C
6.2
TYP SEATING PLANE
5.8

A PIN 1 ID 0.1 C
AREA
12X 1.27
14
1

8.75 2X
8.55 7.62
NOTE 3

7
8
0.51
14X
4.0 0.31
B 1.75 MAX
3.8 0.25 C A B
NOTE 4

0.25
TYP
0.13
SEE DETAIL A
0.25
GAGE PLANE

0.25
0 -8 1.27 0.10
0.40

DETAIL A
TYPICAL

4220718/A 09/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side.
5. Reference JEDEC registration MS-012, variation AB.

www.ti.com
EXAMPLE BOARD LAYOUT
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55) SYMM

1
14

14X (0.6)

12X (1.27)
SYMM

7 8

(R0.05)
TYP
(5.4)

LAND PATTERN EXAMPLE

SCALE:8X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220718/A 09/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55) SYMM

1
14

14X (0.6)

12X (1.27)
SYMM

7 8

(5.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:8X

4220718/A 09/2016
NOTES: (continued)

www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

TL07 XX
No ratings yet
TL07 XX
51 pages
TL071A
No ratings yet
TL071A
48 pages
TL 071
No ratings yet
TL 071
47 pages
TL07x Low-Noise JFET-Input Operational Amplifiers: 1 Features 2 Description
No ratings yet
TL07x Low-Noise JFET-Input Operational Amplifiers: 1 Features 2 Description
47 pages
TL07xx Low-Noise JFET-Input Operational Amplifiers Datasheet (Rev. N)
No ratings yet
TL07xx Low-Noise JFET-Input Operational Amplifiers Datasheet (Rev. N)
69 pages
Ti TL074
No ratings yet
Ti TL074
80 pages
TL 082
No ratings yet
TL 082
78 pages
TL 081
No ratings yet
TL 081
80 pages
TL 084
No ratings yet
TL 084
78 pages
TL061CDR
No ratings yet
TL061CDR
43 pages
TL062 DataSheet
No ratings yet
TL062 DataSheet
52 pages
TL 062
No ratings yet
TL 062
53 pages
TL 064
No ratings yet
TL 064
53 pages
TL08xx FET-Input Op Amps Guide
No ratings yet
TL08xx FET-Input Op Amps Guide
80 pages
TL08xx FET-Input Op Amps Guide
No ratings yet
TL08xx FET-Input Op Amps Guide
81 pages
TL 084
No ratings yet
TL 084
81 pages
TL 081
No ratings yet
TL 081
80 pages
TL08xx FET-Input Operational Amplifiers: 1 Features 3 Description
No ratings yet
TL08xx FET-Input Operational Amplifiers: 1 Features 3 Description
81 pages
TL08xx - Complete
No ratings yet
TL08xx - Complete
81 pages
TL 081
No ratings yet
TL 081
80 pages
TL 081
No ratings yet
TL 081
81 pages
TL07xx Low-Noise FET-Input Operational Amplifiers: 1 Features
No ratings yet
TL07xx Low-Noise FET-Input Operational Amplifiers: 1 Features
87 pages
TL 071
No ratings yet
TL 071
85 pages
tl062 Pre2bandas
No ratings yet
tl062 Pre2bandas
56 pages
tlc2272 q1 PDF
No ratings yet
tlc2272 q1 PDF
44 pages
tl084 PDF
No ratings yet
tl084 PDF
50 pages
TL 082
No ratings yet
TL 082
50 pages
TL08xx JFET-Input Operational Amplifiers: 1 Features 3 Description
No ratings yet
TL08xx JFET-Input Operational Amplifiers: 1 Features 3 Description
50 pages
TL 071
No ratings yet
TL 071
90 pages
JFET-Input Dual Operational Amplifier TL072H SOIC8
No ratings yet
JFET-Input Dual Operational Amplifier TL072H SOIC8
85 pages
tl072 2
No ratings yet
tl072 2
88 pages
TL07xx Low-Noise FET-Input Operational Amplifiers: 1 Features
No ratings yet
TL07xx Low-Noise FET-Input Operational Amplifiers: 1 Features
85 pages
Amplifier TL071
No ratings yet
Amplifier TL071
86 pages
TL 074
No ratings yet
TL 074
85 pages
TL 071
No ratings yet
TL 071
88 pages
TL 071
No ratings yet
TL 071
85 pages
TLV767 1-A, 16-V Precision Linear Voltage Regulator: 1 Features 3 Description
No ratings yet
TLV767 1-A, 16-V Precision Linear Voltage Regulator: 1 Features 3 Description
34 pages
TL074
No ratings yet
TL074
18 pages
TL 071
No ratings yet
TL 071
18 pages
TL07xx Low-Noise JFET-Input Operational Amplifiers: 1 Features 3 Description
No ratings yet
TL07xx Low-Noise JFET-Input Operational Amplifiers: 1 Features 3 Description
70 pages
Texasinstruments Tl072cp Datasheets 0843
No ratings yet
Texasinstruments Tl072cp Datasheets 0843
31 pages
TLV700 200-Ma, Low-I, Low-Dropout Regulator For Portable Devices
No ratings yet
TLV700 200-Ma, Low-I, Low-Dropout Regulator For Portable Devices
37 pages
TL 072
No ratings yet
TL 072
48 pages
TL 071
No ratings yet
TL 071
43 pages
TL 071
No ratings yet
TL 071
47 pages
TL331B-Q1, TL391B-Q1 and TL331-Q1 Automotive Single Comparators
No ratings yet
TL331B-Q1, TL391B-Q1 and TL331-Q1 Automotive Single Comparators
27 pages
TL071
No ratings yet
TL071
11 pages
Tl77Xxa Supply-Voltage Supervisors: 1 Features 3 Description
No ratings yet
Tl77Xxa Supply-Voltage Supervisors: 1 Features 3 Description
27 pages
Tl77Xxa Supply-Voltage Supervisors: 1 Features 3 Description
No ratings yet
Tl77Xxa Supply-Voltage Supervisors: 1 Features 3 Description
28 pages
Polymetron 9610 SC Online Silica Analyser: Lower Maintenance, Less Downtime
No ratings yet
Polymetron 9610 SC Online Silica Analyser: Lower Maintenance, Less Downtime
2 pages
Buffer, Driver & Relay
No ratings yet
Buffer, Driver & Relay
6 pages
Unit 2 Semiconductor
No ratings yet
Unit 2 Semiconductor
131 pages
Emisor Tsal
No ratings yet
Emisor Tsal
3 pages
Fractal Capasitors
No ratings yet
Fractal Capasitors
7 pages
DS14C335 3.3V Supply TIA/EIA-232 3 X 5 Driver/Receiver: General Description Features
No ratings yet
DS14C335 3.3V Supply TIA/EIA-232 3 X 5 Driver/Receiver: General Description Features
12 pages
Rf360 Next Gen Product Brief
No ratings yet
Rf360 Next Gen Product Brief
2 pages
ECE Syllabus
No ratings yet
ECE Syllabus
88 pages
ZS6312 V1.0
No ratings yet
ZS6312 V1.0
12 pages
Car Audio Basics - Basic DC Electronics - 999001
No ratings yet
Car Audio Basics - Basic DC Electronics - 999001
4 pages
Capacitance Type Fqis
No ratings yet
Capacitance Type Fqis
16 pages
Unit 2. Electronics Project #1: 1. Resistance (Ohm)
No ratings yet
Unit 2. Electronics Project #1: 1. Resistance (Ohm)
25 pages
gf1xx Gse
No ratings yet
gf1xx Gse
2 pages
Solar Pump Plant Proposal
No ratings yet
Solar Pump Plant Proposal
5 pages
Mil HDBK 217F Change Notice 1
No ratings yet
Mil HDBK 217F Change Notice 1
37 pages
Metal Detector Circuit Basics
100% (1)
Metal Detector Circuit Basics
24 pages
Rectifiers: Half-Wave vs Full-Wave
No ratings yet
Rectifiers: Half-Wave vs Full-Wave
6 pages
EM700 Installation Guide
100% (2)
EM700 Installation Guide
39 pages
Lgdp4524: 176Rgbx220-Dot, 262,144-Color 1-Chip TFT LCD Driver Ic
No ratings yet
Lgdp4524: 176Rgbx220-Dot, 262,144-Color 1-Chip TFT LCD Driver Ic
130 pages
MCP 3008
No ratings yet
MCP 3008
8 pages
Analogue Electronics Module Guide
No ratings yet
Analogue Electronics Module Guide
3 pages
Precision Temperature Sensors Guide
No ratings yet
Precision Temperature Sensors Guide
3 pages
Sinusoidal Steady-State Analysis (II) (II) : (Chapter 9)
No ratings yet
Sinusoidal Steady-State Analysis (II) (II) : (Chapter 9)
33 pages
CMOS Layers, RC of An Interconnect
No ratings yet
CMOS Layers, RC of An Interconnect
9 pages
Project Report On Automatic Street Light Using LDR
67% (3)
Project Report On Automatic Street Light Using LDR
5 pages
IRF7103 (Dual)
No ratings yet
IRF7103 (Dual)
9 pages
ADSL Line Driver Design Guide, Part 2
No ratings yet
ADSL Line Driver Design Guide, Part 2
10 pages
Solution Manual Power Electronics Daniel PDF
0% (1)
Solution Manual Power Electronics Daniel PDF
8 pages
Rectangular Patch Antenna Design With Ansoft
No ratings yet
Rectangular Patch Antenna Design With Ansoft
35 pages
ELTE 307 Optical Electronics PDF
No ratings yet
ELTE 307 Optical Electronics PDF
144 pages