III Congresso Brasileiro de Energia Solar - Belém, 21 a 24 de setembro de 2010

HYBRID INVERTER FOR WITH ASSOCIATION OF A FIVE LEVEL

INVERTER AND A THREE LEVEL TWO SWITCH INVERTER
Carlos Alberto Gallo – gallo@ufu.br
Universidade Federal de Uberlândia, Faculdade de Engenharia Mecânica

Resumo. This paper presents the most important topologies like diode-clamped inverter (neutral-point clamped),
capacitor-clamped (flying capacitor), and cascaded multicell with separate dc sources. Emerging topologies like
asymmetric hybrid cells and soft-switched multilevel inverters are also discussed. This paper also presents the most
relevant control and modulation methods developed for this family of converters: multilevel sinusoidal pulse width
modulation, multilevel selective harmonic elimination, and space-vector modulation. The voltage regulation is
obtained by means of a switched power stage, composed of two current sources used to modulate the desired RMS
value and waveform in the output stage. Mathematical analysis, experimental and simulation results are presented.

Palavras-chave: Inverter Multipulse, Hybrid Inverte

1. INTRODUCTION

Multilevel inverters include an array of power semiconductors and capacitor voltage sources, the output of which
generate voltages with stepped waveforms. The commutation of the switches permits the addition of the capacitor
voltages, which reach high voltage at the output, while the power semiconductors must withstand only reduced
voltages. A two-level inverter generates an output voltage with two values (levels) with respect to the negative terminal
of the capacitor, while the three-level inverter generates three voltages, and so on.
Today, it is hard to connect a single power semiconductor switch directly to medium voltage grids. For these reasons, a
new family of multilevel inverters has emerged as the solution for working with higher voltage levels [1]-[3].
The term multilevel starts with the three-level inverter introduced [4]. By increasing the number of levels in the
inverter, the output voltages have more steps generating a staircase waveform, which has a reduced harmonic distortion.
However, a high number of levels increases the control complexity and introduces voltage imbalance problems.
Three different topologies have been proposed for multilevel inverters: diode-clamped (neutral-clamped) [4]; capacitor-
clamped (flying capacitors) [5], [6], [7]; and cascaded multicell with separate dc sources [5], [6], [8]-[10]. In addition,
several modulation and control strategies have been developed or adopted for multilevel inverters including the
following: multilevel sinusoidal pulse width modulation (PWM), multilevel selective harmonic elimination, and space-
vector modulation (SVM).
The most attractive features of multilevel inverters are as follows.
1) They can generate output voltages with extremely low distortion and lower dv/dt.
2) They draw input current with very low distortion.
3) They generate smaller common-mode (CM) voltage, thus reducing the stress in the motor bearings. In addition,
using sophisticated modulation methods, CM voltages can be eliminated [8].
4) They can operate with a lower switching frequency.
The results of a patent search show that multilevel inverter circuits have been around for more than 25 years. An early
traceable patent appeared in 1975 [9], in which the cascade inverter was first defined with a format that connects
separately dc-sourced full-bridge cells in series to synthesize a staircase ac output voltage. Through manipulation of the
cascade inverter, with diodes blocking the sources, the diode-clamped multilevel inverter was then derived [10].
The diode-clamped inverter was also called the neutral-point clamped (NPC) inverter when it was first used in a three-
level inverter in which the mid-voltage level was defined as the neutral point. Because the NPC inverter effectively
doubles the device voltage level without requiring precise voltage matching, the circuit topology prevailed in the 1980s.

2. INVERTER TOPOLOGIES

A- Capacitor-Clamped Inverter
Fig. 1 illustrates the fundamental building block of a phase-leg capacitor-clamped inverter. The circuit has been called
the flying capacitor inverter [5], [6], [7] with independent capacitors clamping the device voltage to one capacitor
voltage level. The inverter in Fig. 3(a) provides a three-level output across a and n, i.e., Van=Vdc/2, 0, or
-Van=Vdc/2. For voltage level Vdc/2, switches S1 and S2 need to be turned on; for -Van=Vdc/2, switches S1’ and S2’ need
to be turned on; and for the 0 level, either pair (S1, S1’) or (S2, S2’) needs to be turned on. Clamping capacitor C1 is
 III Congresso Brasileiro de Energia Solar - Belém, 21 a 24 de setembro de 2010

charged when S1 and S1’ are turned on, and is discharged when S2 and S2’are turned on. The charge of can be balanced
by proper selection of the 0-level switch combination.

S1

C1

D1 S2

Vdc
n a

S3
D2

C2
S4

Fig. 1 – Three level capacitor clamped multilevel inverter.

Van

a)

Van

b)

Fig. 2 – Voltage waveform: a) three level; b) five level.

 III Congresso Brasileiro de Energia Solar - Belém, 21 a 24 de setembro de 2010

S1

C1

C3 S2

C2 S1

C1

S2
Vdc
C3 C1
n

S3

C1
C2 S4

C3

S3

C1
S4

Fig. 3 - Five level capacitor clamped multilevel inverter.

The voltage synthesis in a five-level capacitor-clamped converter has more flexibility than a diode-clamped converter.
Using Fig. 3 as the example, the voltage of the five-level phase-leg a output with respect to the neutral point n, Van, can
be synthesized by the following switch combinations, as showed in Fig. 2 the voltages waveforms for three level
inverter and five level inverter.
1) For voltage level Van=Vdc/2, turn on all upper switches
S1–S4.
2) For voltage level Van=Vdc/4, there are three combinations:
S1, S2, S3, S1’ (Van=Vdc/2 of upper C4’s -Vdc/4 of C1);
S2, S3, S4, S4’ (Van=3Vdc/4 of upper C3’s -Vdc/2 of C4)
S1, S3, S4, S4’ (Van=Vdc/2 of upper C4’s -3Vdc/4 of C3’+Vdc/2 of C2’s).
3) For voltage level Van=0, there are six combinations:
S1, S2, S1’, S2’ (Van=Vdc/2 of upper C4’s -Vdc/2 of C2’s);
S3, S4, S3’, S4’ (Van=Vdc/2 of upper C2 -Vdc/2 of lower C4);
S1, S3, S1’, S3’ (Van=Vdc/2 of upper C4’s -3Vdc/4 of C3’s+ Vdc/2 of C2’s-Vdc/4 of C1);
S1, S4, S2’, S3’ (Van=Vdc/2 of upper C4’s -3Vdc/4 of C3’s+ Vdc/2 -Vdc/4 of C2’s of lower C4’s);
S2, S4, S2’, S4’ (Van=3Vdc/4 -Vdc/2 of C2’s of upper C3’s -3Vdc/4 +Vdc/4 of C1’s of C3’s+ Vdc/2 of C2’s+Vdc/4 of C1);
S2, S3, S1’, S4’ (Van=3Vdc/4 of C3’s -Vdc/4 of C1’s
-Vdc/2 of C1’s of lower C4’s).
4) For voltage level Van=-Vdc/4, there are three combinations:
S1, S1’, S2’, S3’ (Van=Vdc/2 of upper C4’s -3Vdc/4 of C3’s);
S4, S2’, S3’, S4’ (Van=Vdc/4 of C1’s -Vdc/2 of lower C4’s);
S3, S1’, S3’, S4’ (Van=Vdc/2 of C2’s -Vdc/4 of C1’s -Vdc/2 of lower C4’s);
5) For voltage level Van=-Vdc/2, turn on all lower switches, S1’– S4’.
In the preceding description, the capacitors with positive signs are in discharging mode, while those with negative sign
are in charging mode. By proper selection of capacitor combinations, it is possible to balance the capacitor charge.
Similar to diode clamping, the capacitor clamping requires a large number of bulk capacitors to clamp the voltage.
Provided that the voltage rating of each capacitor used is the same as that of the main power switch, an -level converter
will require a total of clamping capacitors per phase leg in addition to main dc-bus capacitors.

B- Capacitor-Clamped Inverter
The Fig. 4 shows the switched audio amplifier operating as a three level Proposed Three Level Half Bridge Inverter half
bridge inverter, where this new DC-AC converter have, like output, a sinusoidal voltage with 127V AC RMS, with a
frequency of 60 Hz.
 III Congresso Brasileiro de Energia Solar - Belém, 21 a 24 de setembro de 2010

Fig. 4 – Half proposed bridge inverter.

Fig. 5 - Operating stages.

The Proposed Three Level Half Bridge Inverter has the circuit operation for the cases of ILoad>0 and ILoad<0 are
symmetrical. The operational principle is summarized referring to the ILoad>0 with waveforms as shown in Fig. 4.
1st STAGE (t0,t1): This stage begins at instant t0, where switch M1 turns on and the resonant inductor changes linearly.
During this stage, capacitor C1 discharge occurs which is limited by inductor L1.
2nd STAGE (t1,t2): This stage begins when switch M1 is turned off. This is the freewheeling stage for the inductor L2,
where the current flows through diode D2 and the voltage on the load remains clamped by the filter capacitor C3.
3rd STAGE (t2,t3): This stage begins when filter capacitor C3 discharges completely, when the freewheeling remains
between inductor L2 and diode D2.
The other cell (M2) analysis is the same.
 III Congresso Brasileiro de Energia Solar - Belém, 21 a 24 de setembro de 2010

Gate to t1 t2 t3

IL1
Io

ID1

ID2

IS1

VS1

Io

Fig. 6 - The circuit operational waveforms.

If all the elements of the circuit are considered as ideal, it can be assumed that the input power is equal the output
power, as in (1):
VCC1 . I i = VC . I O (1)
Where Io is the sum of the currents in the capacitor and the load.
The output current Io is equal to the product between the inductor current and the duty cycle of the switches
accreting to the Fig. 4.it is:
IO = D . I L (2)
Analogously, the input current Ii is equal to the output current Io, when the switches are on, except for the current
that flows through the diodes when the switches are turned off. Where, it can be written:
I i = D . I L − (1 − D ). I L (3)
I i = (2 . D − 1). I L (4)
Substituting (2) and (4) in (1), it gives:
Vi
=
( 2 . D − 1)
(5)
Vo D

Fig. 7 - Voltage output and current output.

 III Congresso Brasileiro de Energia Solar - Belém, 21 a 24 de setembro de 2010

Fig. 8 - Voltage and current waveforms through the resonant capacitors and inductor.
Even though the multipulse inverter has already been built in laboratory, an experimental prototype of the Three Level
Half Bridge Inverter is yet to be fully implemented and associated to the aforementioned topology, constituting the
proposed Hybrid Inverter with output AC. Therefore additional experimental results will be presented at the final
version of this paper.

3. FUNDAMENTAL PRINCIPLES

The Fig. 3 shows the five level capacitor clamped multilevel inverter and shows the principle of constructing an input
line voltage through two components and , obtained when the multilevel inverter, in this case operating on five levels.
The proposed converter allows the improvement of the input line voltage by reducing its THD. It is important to notice
that, only a fraction of the total output power is required to flow through the converter parallel circuits, supporting a
competitive economic impact. It was experimentally observed that for the multilevel inverter operating as a inverter,
just about 20% of the total output power is processed by the parallel inverter and a less than 14% in the input line
voltage can be achieved. Besides, one can observe that a variety of harmonic content restrictions imposed by IEEE std
519–1992 can be easily meet by the hybrid inverter presented in this paper, as one can see in Fig. 9. For example, is
imposed through the inverter parallel, the input line voltage, will be built of the combination of and with a very low
(around 5%). In this case, the converters will supply about 45% of the rated power. Thus, this flexibility is a very good
characteristic of the proposed hybrid power inverter system when compared to other multipulse inverter structures.

Fig. 9 - Theoretical waveforms for hybrid inverter THD in the input line voltage.

Depending on the kind of application, the proposed hybrid inverter can operate in accordance to the harmonic content
restrictions of the input line current with the parallel inverter processing just the minimum power. Therefore, the whole
structure presents reduced cost, volume and, higher efficiency when compared to other multilevel inverters. Moreover,
the economical benefits of this new topology are extremely valuable for high power installations, because around 33%
maximum value of rated power will be processed in the parallel circuits (Proposed Three Level Half Bridge Inverter), in
order to reduce the to a very low value (around 5%).
This feature allows higher efficiency and payback in a very short time for the investment. Moreover, when used in
retrofitting applications, the available total rated power will increase to 133% of the original output power, with obvious
improvements on power quality. In this paper, the authors show the proposed hybrid inverter operating as a
conventional five level inverter. The imposition of a sinusoidal input voltage waveform is under progress and will be
reported in the future.
It should be emphasized that for isolation to Proposed Three Level Half Bridge Inverter fed through transformers, there
is galvanic isolation, as shown in Fig. 10. As a result, such structure is able to replace inverter, but with the obvious
drawbacks (volume, weight and cost) of requiring extra magnetic devices. The authors discuss in [20] the
implementation higher frequency transformer.
 III Congresso Brasileiro de Energia Solar - Belém, 21 a 24 de setembro de 2010

Hence, the control of the Proposed Three Level Half Bridge Inverter current is no longer lost resulting that the desired
input line voltage waveform can be achieved. It is important to emphasize that, even using single-phase isolating
transformers, the proposed hybrid deploying a inverter with 2 switches to make the complementation of waveform for a
sinusoidal output waveform is still more attractive than the multipulse inverter structures presented in [12], [13], [14].

Souce Load

TC
Lb1

E1
Cr S1

Cf

Lr

S2
E2
Lb2

Fig. 10 - New hybrid inverter.

4. PROPOSED CONTROL STRATEGY [15]

The main control circuit objective is to impose the input line voltage at low THD. Therefore, the control strategy must
focus on establishing the best relationship between the input voltage of the standard multilevel inverter and the input
voltage of the controlled Proposed Three Level Half Bridge Inverter, in order to achieve a desirable input line voltage
THD. As example, if a twelve pulses ac current waveform is desired, the control strategy of the controlled proposed
inverter can be established as shown in the diagram of Fig. 11.
In order to compose the waveform of the input line voltage, a sample of the input line-to-neutral voltage must be
inverted and compared with dc voltage levels in order to generate a synchronized square wave to impose the input half
bridge inverter depicted. The voltage is the reference voltage waveform and can be supplied either by analog or digital
devices. It was found that, when operating as a conventional five level inverter, the lowest input line current THD is
achieved when the magnitude of the voltage is 33% of the magnitude of the principal inverter. Therefore, the reference
voltage must be multiplied by a fraction of the current of multilevel inverter providing a reference signal equal to ,
where k is equal to of the dc current through the output inductor filter of the three-phase five level inverter for the
minimum THD .
In order to generate a PWM reference signal, a saw tooth voltage waveform is added to the multiplier circuit signal.
Finally, the PWM reference signal must be compared with the cur rent flowing through the Proposed Three Level Half
Bridge Inverter to generate the gate-drive signal for switch. Hence, the current through the voltage signal will follow the
imposed reference through a very simple PWM control strategy

Ref Half Ref Source

Bridge

Gate

Ref Cf
Ref

Fig. 11 - Proposed control strategy.

 III Congresso Brasileiro de Energia Solar - Belém, 21 a 24 de setembro de 2010

5. RERSULTS

In order to analyze the operation of the proposed Hybrid Inverter, a digital simulation was performed and then
compared with experimental results. Table I shows the system specifications. A multilevel inverter control strategy was
applied in order to control the proposed structure, waveform in the line input voltage. Thus, the proposed control shown
in Fig. 10 was implemented, and used for simulation analysis. An open loop control strategy, following the principles
depicted in Fig. 6 was implemented in power electronics simulation software.
The simulation results for the input line voltage composition are portrayed in Fig. 12 and Fig. 13. Fig. 12 shows the
input current from the controlled Proposed Half Bridge, considering highly dc inductive filters.
Fig. 14 shows the simulation of input voltage and voltage waveforms where it can be observed that multilevel inverter
input voltage waveform was imposed in the input line current, resulting in a THD near to 13.7%, for nominal output
power. Fig. 15 shows the frequency spectrum of the input line current, for rated load. The ripple voltage over the
average nominal output voltage is depicted on Fig. 16.
The simulation studies supported the best relationship between the magnitudes of current magnitude and current to be
about 33%. This relationship gives the lowest of 13.55% for a multilevel inverter waveform in the line input voltage, as
shown in Fig. 15 shows the power rating of Proposed Three Level Half Bridge Inverter in relation to the total output
power. Therefore, one can observe that, processing only 15.29% of the total output power, less than 14% of THD in the
line input current is achieved.

Table 1: Designed parameters and used semiconductors

Data Specifications
Total Output Power = 1.0 kW
Multipulse Inverter Three Level Associated Inverter
Input Voltage = 150V Input Symmetrical Voltage = 150V
Output Voltage = 127V RMS Output Voltage = 127V RMS
Output Power = 850W Output Power = 150W
Switches = IRFP460 Switches = IRFP460
Diodes = HF15TB60 Diodes = HF15TB60
Inductor (Lb) = 400μH
Capacitor (Cf) = 15μF

Fig. 12 - Input voltage Proposed Three Level Half Bridge Inverter.

Fig. 13 - Input voltage multilevel inverter.

 III Congresso Brasileiro de Energia Solar - Belém, 21 a 24 de setembro de 2010

Fig. 14 - Sinusoidal input voltage waveform of Proposed Hybrid Inverter

5,00E+00
Percentage of The Fundamental Component (%)

4,00E+00

3,00E+00

2,00E+00

1,00E+00

0,00E+00
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
Harmonic Order

Fig. 15 - Frequency spectrum of the output line voltage.

Fig. 16 - Output voltage.

6. CONCLUSION
This paper introduced a novel three-phase hybrid power inverter capable of achieving nearly unity output distortion
with programmable input line voltage THD. The paper presented comprehensive analysis, evaluation and design of a
system composed of single-phase Half Bridge Inverter connected to each leg of a standard uncontrolled three-phase six-
pulse diode rectifier. The parallel converters power rating is only a small fraction of the total output power supporting a
competitive economic impact.
Additional analyses were presented to determine the amount of power processed by the controlled rectifiers, in order to
obtain a given (and desirable) total harmonic distortion in the input line voltage . It was verified that for less than 15%
only 21% of the rated output power had to be processed by the Half Bridge Inverter. Therefore, this proposed structure
is recommended for high power installations, and retrofitting to existing installations is feasible since the parallel path
can be easily controlled by integration with the existing dc-link. The proposed structure provided a multipulse ac input
voltage with simplified design and reduced cost. In addition to the converter analysis and simulation results,
experimental results from a 1 kW simulation project were presented, in order to validate the proposed structure and
control strategy. The author is working on further developments towards a fully digital programmable control (using
DSP and FPGA devices) for the proposed converter

ACKNOWLEDGEMENT

The authors gratefully acknowledge CNPq and FAPEMIG for the financial support to this work (Proc. Nb.
574001/2008-5 - INCT-EIE) and also Texas Instruments and ON Semiconductor for sending us free samples.
 III Congresso Brasileiro de Energia Solar - Belém, 21 a 24 de setembro de 2010

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