UNIVERSITY IN! i B.E. Even Semester Midterm Examination, 2025-26 omputer Science & Enginecring Department Subject: Computer Organization & Architecture Subject code: PCC-CSE 402 21 tr, Full Marks: 15 Instruction: 1. a) Draw the structure of a single DRAM cell? -b) Explain different kinds of addressing modes using proper diagrams? [5+10]BLEWIPCCCSEA02246 B.E. 4th Semester Theoretical Examination 2023-2024 Subject : Computer Organization & Architecture Course : PCC-CSE-402 Time: 3 Hours Full Marks : 70 All questions carry equal marks, Figures in the margin indicate full marks, Answer any five questions. Write all the parts of a question together in one place. 1. (a) How many sets are there in a 2-way set associative cache memory with 32 Kbytes capacity and 64 Bytes lines and how many bits of addresses are used to select a set in this cache memory? What about an 8-way set associative cache with the same capacity and the same line length? (b) Mention the names of four cache replacement algorithms. 1044 2. (a) Draw the block diagram of the Execution Unit of an Intel 8086 processor and explain the function of various units within it, (b) What do we mean by ‘locality of reference’? 1242 3. Draw and explain the structural block diagram of the following: “I (a) Shared memory multi-processor system (b) Multiple Instruction stream single data stream (MISD) configuration 4. Draw the instruction flow charts of the following sequence if instructions processed within a 5-stage pipelined processor. Proper considerations must be done to avoid RAW data dependency hazards. AT (@) 1): ADD RI, R2, R3; 1,: MULT R4, RI, RS; I,:DIV RS. R6,R7; (b) 1,:SUB RI, R2,R3; 1: MULT R4, RI, RS; I;:XOR R4, RI, R6: Iy:CMP R7,R4, RI; 5. (a) Explain Interrupt Driven LO technique with suitable flow chart. (b) An un-pipelined processor with 8 ns cycle time and pipeline latches with 1 ns latency is given. Find the cycle times of pipelined versions of the processor with 2, 4, 8 and 16 stages if the data path logic is evenly divided among the pipeline stages, 10H 32055 Please Turn Over 82B.EsIV/PCC-CSE-402/24 @ 6. 7. Draw the structure of a low-order interleaved memory syste! - 1 unit. . med contro! (a) Draw and explain the block diagram of a Micro-program™ trol unit with resPect to speed ne c (a) Compare hardwired control unit and micro-programmed con! flexibility. banks with cn comprising of sremory location: Ti 4-locations within each banks. Find out the 4-bit addresses of each of 14 and analyze their contiguity. 3Yax4 . Write down differences between the following: () RAW Memory and ROM (b) SRAM and DRAM (©) RAM and EEPROM (@) Primary memory and Secondary memoryB.E.-IV/PCC-CSE-402/23 B.E. 4th Semester Theoretical Examination 2022-2023 Subject : Computer Organization & Architecture Course : PCC-CSE-402 Time: 3 Hours Full Marks : 70 All questions carry equal marks, Figures in the margin indicate full marks. Answer any five questions. Write all parts of the same question together in contiguity/adjacency. J. (a) Write down the differences between Von-Neumann and Harvard Architectural models of a computer. (b) Draw and explain the structure of a DRAM cell capable of storing 1-bit of data. 4410 2, Write down differences between the following: BH (a) SRAM vs. DRAM (b) RAV memory vs. ROM (©) Primary memory vs. Secondary memory (@) Hardwired vs. Micro-programmed Control Unit. 3. Explain Immediate, Direct, Indirect, Register, Register Indirect and Displacement addressing modes using suitable block diagrams. 14 4A. List out the effective address and corresponding content of accumulator according to various addressing modes (such as: Direct, Indirect, Immediate, Register Direct, Register Indirect, Relative and Indexing) based on the following info. 14 ‘Address Main Memory 1200 _| LOAD Acc | Addressing Mode 1201 Address = 1250 1202 Next Instruction 1240 1270 1250 1280 ee 1260 7290 [1270 | 6700=SsCd 1280 35600 2452 "7800 26728 Please Turn Over 76BLEIVIPCC-CSE~402/23 (2) ‘The table deplets a portion of the maln memory starting with locaton nddress of fq Where, the instruction LOAD Ace indicates losing value Info the Accumulator, The yg, 1250 stored in address location 1201 may be part of address calculation of Instruction LOA, Initially, the program counter PC contains the value 120, Gener! purpose register contains 1240 and the index register contains the value 10, S. (a) Drawa generic block diagram of a Micro-programmed Control init, (b) Draw the CPU internal organization structure and mention briefly the function of each spec purpose registers, At 6. (a) Draw three separate flow charts depicting Programmed-W/O, Interrupt driven 1/0. and DM techniques, (a) What is meant by the term “cycle stealing” during the direet memory access mechanism? 12- 7. (a) Find the execution time (in cycles) of the following instruction sequence executed in Pipelined processor with 5 evenly decomposed pipeline stages. Here, proper consideratio Should be done to neutralize any sort of pipeline hazards occurring due to data dependency particular stage over one or more previous stage, Also, draw the instruction flow chart solve this problem, 11: ADD R1, R2, R3; 12; SUB RS, R4,R1; 13: DIV R6,R1, R5; 14: MULT R7,R5, R6; (b) What is Flynn's Classification of computers? 104 8. Draw the block diagram of the internal structure of 1 an Intel 8086 processor and briefly expla different parts of its Execution Unit (EU). |B.E Even Semester Examinations 2021-22 Subject: Computer Organization & Architecture Code: PCC-CSE 402 Time: 3 Hours Full Marks: 70 Instructions: Answer any five questions Send this answer script to the mail id: witspeccse402,new.cse.reg@gmail.com ‘QNO. QUESTIONS MARKS 1. (a) | Write the differences between SRAM and DRAM, 4 (b) | Draw the structure of a DRAM cell and explain its operation. 10 2 Find the execution time (in cycles) of the following instruction sequence 14 executed in a pipelined processor with 5 evenly decomposed pipeline stages. Here, proper considerations should be done to neutralize any sort of pipeline hazards occurring due to data dependency of a particular stage over one or more previous stage. Also, draw the instruction flow-chart 10 solve this problem. I: ADD R1R2.R3; 12: SUB RSR4R1; 13: DIV R6R1.R: 14: MULT R7, RS.R6; 3. Draw and illustrate different types of Addressing Modes. 4 (a) | What are the different types of ROM? 4 (b) | Draw the CPU internal organization structure and mention briefly the function 10 of each special purpose registers.QNO. QUESTIONS MARKS 5. Draw the CPU Main memory mapping scheme for a CPU with 16 bit address 14 bus connected to a Kbyte memory comprising of 4 RAM chips of 128Bytes, each and a ROM chip of 512 Bytes. Also find out the starting and last addresses of each of such memory chips. 6. (a) | Write the relative advantages and disadvantages of Direct, Fully-Associative 10 and Set-Associative cache memory mapping techniques, {b) | Mention the names of four cache replacement policies. 4 7. (a) | What is Direct Memory Access (DMA)? How is it beneficial over 10 Programmed /O and Interrupt driven VO techniques? {b) | What is Von-Neumann bottleneck? Explain, 4 8. (a) | What is Flynn's Classification of computers? 4 {b) | Draw the block diagrams of MISD and MIMD machines, 10B.E. Odd Semester Midterm Examination, 2020-21 Subject: Computer Organization & Architecture Paper Code: PCC-CSE 402 [nstruction: Answer all questions on Ad sized pages with your Name, Roll Number and Registration Number at the top of the Ist page, Scan these pages to PDF format and send it via return mail within stipulated time for evaluation] Time: 1 Hr. Full Marks: 20 Answer all questions: 1. a) Explain different types of Addressing modes with suitable diagrammatic illustrations. {10} 2. ACPU with 16 bit addressing format is connected with a main memory comprising 4-RAM chips each of 1288ytes and a ROM chip of 512Bytes size. Draw the memory mapping scheme with mentioning of starting and ending addresses foreach chip. [10]BE-IV/CSE-401 Inter 19 B.E. 4th Semester Examination 2018-19 subject: Fundamentals of Computer Organization & Architecture Paper: CSE-401 (Intermedinte) gx 3 Hts Full Marks: 70 The figures in the margin indicate full marks, Candidates are required to give their answers in their own words as far as practicable. Answer Question No. 1 and another four questions such that one question nust be answered from each of the four groups. Ti Write all the parts of a particular question in adjacency. ‘Answer the following: Ix10=10 (a) What is a Cache memory? (p) Is hard disk a semiconductor memory? (c) What doa CPU register docs? (a) Where does DMA controller vary from other 1/O modules? (©) Mention the difference between a lateh and a flip-flop. 1 (f) What is the input signal of a T-state generator? (g) What are No Operation (NOP) states? (b) Give an example of zero-address instruction. (3) Mention one hazard felt in pipelined processors. (j) What is temporal parallelism? Group-A. 2. Write differences between the following: 3x5=15 (i) Read-Write memory vs. Read-Only memory (ii) Von-Neumann Architecture vs. Harvard Architecture (iii) Main Memory vs. Cache Memory (iv) SRAM vs, DRAM (v) RAM vs, EEPROM 3. (a) For a main memory comprising of 4RAM chips each 128Bytes, Design the main memory address mapping scheme and Fi ast address of exch of the mentioned RAM chips and the ROM chip. Here, the address lines connecting the processor with the main memory is assumed to be 10. cache memory with 64kByte eapacily d to in 2 set in this cache memory” to select a be memes) h of 128 Bytes and 2 ROM chip of ‘and Find out the starting and umber of (b) How many sets are there in an 8-way set-associntive and 128Byte lines? How many bits of address are use 463 Please urn Overs the value 10, (2) pE-IV/CSE-401(Interj/19 Group-B various types of Addressing modes with fatianle block diagrams, + Oe dress, two-nddress and three-address instructions, i a} Where, the instruction LOAD ae main memory starting with location address of ie ; 1250 stored in address location 120) man te cue. & value into the Accumulator. TH in}, Initially, the program counter PC coma Part of address calculation of instruction LE” 1240 and the index register contain value 1200, General purpose register R] ©(3) BE-IV/CSE-401(Inter\/19 Group-c Explain different input-output techniques n: driven 1/0 and direct memory access (DMA). 6 amely the programmed 1/0; interrupt (by Compare RISC and CISC architectures, 1045215 (a) Compare Hardwired Control Unit and Micro-programmed Control Unit. (b) Draw the structure of a Micro-programmed Control Unit and explain its functioning. 3+12=15 Group-D g, (a) “The speed-up factor of a k-stage pipeline is almost equal to k.”— Explain. (b) Find the execution time (in cycles) of the following instruction sequence executed in a pipelined processor with 5 evenly decomposed pipeline stages. Here, proper considerations should be done to neutralize any sort of pipeline hazards occurring due to data dependency of a particular stage over one or more previous stage. Also, draw the instruction flow-chart to solve this problem. Il: MULT RI,R2,R3; 12:DIV R5,R4,R1; 13: SUM R6,R1,R5; 14: CMP R7, RS,R6: 5+10=15 9, (a) Draw the structures of loosely coupled and tightly coupled SIMD machines and briefly explain their main differences. (b) Draw the block diagram of a shared memory multiprocessor system. 10+5=15