Low Dropout Voltage Regulator 2024-25

Chapter 1
INTRODUCTION
Power management is one of several critical concerns in the design of those devices in order
to meet product standards such as prolonged run time and reduced power consumption.
Because of its unrivalled qualities such as low cost, tiny output ripple, and low power
dissipation. The voltage regulator is one of the most widely used circuit components in this
industry. Voltage regulators are essential components of all modern electronic devices and
systems' power supply systems. Voltage regulators are power devices that maintain a constant
and stable output voltage even with the input voltage variations or load variations. Various
types of voltage regulators have been developed over time based on their design.
The Low Drop-out Voltage Regulator frequently referred as the LDO is a voltage regulator
with a low dropout voltage. Low-dropout regulators are defined by their ability to maintain
regulation even when supply and load voltages change by a tiny amount. LDOs have shown to
be effective instruments for achieving low power consumption and high-power efficiency in
modern environment, as battery powered devices pervade practically every part of life. Due to
the lack of a huge and expensive inductor, LDOs have a much lower footprint and greater
overall value when compared to other types of inductors. LDOs are a simple and cost-effective
way to regulate linear power. Low dropout voltage regulators serve two functions, the first of
which is to reduce an incoming supply (input) voltage to the lower voltage required by the load.
Another feature is the provision of a very low noise voltage source, even when noise is present.
In comparison to switching regulators, LDOs are primarily employed because of their low-
noise output voltage, low power consumption, small size, and low shutdown current, and
inexpensive cost. They're ideal for noise-sensitive, high-frequency applications because of the
clean voltage they provide. The pass element (pass transistor), error amplifier, and BGR circuit
(reference voltage source) are the three basic components of an LDO.
In the realm of LDO design using 180nm technology, designers face a host of challenges and
considerations that demand meticulous attention. With the continuous drive for smaller, more
efficient devices, these LDOs must navigate the intricacies of the 180nm process node,
balancing performance, power efficiency, and reliability. One of the foremost challenges lies in
mitigating the effects of process variations inherent in semiconductor manufacturing at this
scale. These variations can manifest in transistor threshold voltages, channel lengths, and oxide
thicknesses, potentially jeopardizing the stability and performance of the LDO.

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To counteract these variations, designers employ robust design techniques, such as device
sizing, compensation circuitry, and layout optimization, to ensure consistent operation across
manufacturing runs. Additionally, the drive for increased power efficiency necessitates
innovative approaches to minimize power dissipation while maintaining stringent voltage
regulation specifications. Achieving optimal trade-offs between quiescent current, dropout
voltage, and load regulation becomes paramount in this pursuit.
Furthermore, as LDOs find application in a diverse range of systems, from ultra-low-power IoT
devices to high-performance computing platforms, designers must tailor their designs to meet
specific application requirements, be it ultra-low quiescent current for battery-operated devices
or high load regulation for demanding applications. Through thorough analysis techniques,
such as transient analysis, small-signal analysis, and Monte Carlo simulations, designers can
gain valuable insights into the performance and robustness of their LDO designs, ensuring
reliability in real-world operating conditions. Thus, the design and analysis of LDOs using
180nm technology demand a holistic approach, integrating cutting-edge design methodologies
with a deep understanding of semiconductor physics and circuit theory.
1.1 Background
In the landscape of semiconductor technology, the design and analysis of Low Dropout (LDO)
voltage regulators utilizing the 180nm process node represent a convergence of precision
engineering and advanced manufacturing capabilities. The journey of LDO design begins with
the recognition of their pivotal role in providing stable and regulated power supplies across a
spectrum of electronic devices. This realization is particularly pronounced in the context of the
180nm technology node, which marks a significant advancement characterized by enhanced
performance metrics and reduced power consumption compared to its predecessors.
Within this context, the background of LDO design and analysis encompasses a nuanced
understanding of both the technology itself and the broader semiconductor ecosystem. At its
core, the operation of LDOs relies on intricate circuitry, including pass transistors, error
amplifiers, feedback networks, and voltage references. These components work harmoniously
to ensure that the output voltage remains constant, notwithstanding fluctuations in the input
voltage or variations in the load current.
Moreover, the choice of the 180nm technology node underscores a strategic decision informed
by its inherent advantages. This node offers a favorable balance between performance, power
efficiency, and cost-effectiveness, making it an attractive option for a myriad of applications.

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However, the transition to this advanced node introduces a unique set of challenges and
considerations. These include grappling with process variations that can exert a pronounced
impact on LDO performance, necessitating meticulous design strategies to uphold stability and
reliability.
Furthermore, the backdrop against which LDOs operate is characterized by an ever-evolving
landscape of technological innovation and market demands. As such, designers are tasked with
not only harnessing the capabilities of 180nm technology but also anticipating and responding
to emerging trends and application-specific requirements. Whether catering to the stringent
power constraints of battery-powered devices or the exacting performance demands of high-
speed data processing systems, LDO design must be adaptable and versatile.
In navigating this landscape, designers rely on a multifaceted approach that encompasses
rigorous analysis techniques and innovative design methodologies. Transient analysis, small-
signal analysis, and Monte Carlo simulations serve as invaluable tools for evaluating the
performance and robustness of LDO designs across a spectrum of operating conditions.
Through this iterative process of design refinement and validation, designers can unlock the full
potential of LDOs in the realm of 180nm technology, ushering in a new era of precision and
efficiency in integrated circuit design.
1.2 Problem statement
The problem statement "Design and simulation of LDO using 180nm technology" refers to the
task of designing and simulating a Low Dropout Regulator (LDO) using a 180nm CMOS
(Complementary Metal-Oxide-Semiconductor) technology process.
An LDO is a type of voltage regulator that can operate with a very small voltage difference
between the input and output, making it suitable for applications requiring a stable voltage
supply with minimal power loss.
In this project, we would need to design the circuitry of the LDO, considering the 180nm
technology constraints and requirements. After the design is completed, we would simulate the
LDO to verify its performance and ensure it meets the desired specifications.
1.3 Motivation
The motivation behind delving into the design and analysis of Low Dropout (LDO) voltage
regulators using 180nm technology is rooted in the pursuit of pushing the boundaries of
semiconductor engineering and advancing the state-of-the-art in integrated circuit design. At its
core, this endeavor is driven by a confluence of technological innovation, market demands, and

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the relentless quest for efficiency and performance optimization. first and foremost, the
transition to 180nm technology represents a pivotal milestone in semiconductor manufacturing,
offering a compelling blend of enhanced performance capabilities and reduced power
consumption compared to previous process nodes. This presents a ripe opportunity to explore
new frontiers in LDO design, leveraging the advantages of 180nm technology to develop
highly efficient, compact, and reliable voltage regulation solutions.
Furthermore, the motivation to delve into LDO design using 180nm technology is fueled by the
pressing need to address emerging challenges and capitalize on new opportunities in the
semiconductor landscape. As technology continues to evolve at a rapid pace, designers are
confronted with increasingly complex design constraints, including stringent power budgets,
shrinking form factors, and escalating performance demands. By embracing the capabilities of
180nm technology and employing advanced design methodologies and analysis techniques,
designers can navigate these challenges with confidence and deliver innovative LDO solutions
that meet the evolving needs of the market.
Ultimately, the motivation behind the design and analysis of LDOs using 180nm technology is
rooted in the relentless pursuit of excellence and innovation in semiconductor engineering. By
pushing the boundaries of what is possible, designers can not only enhance the performance
and efficiency of LDOs but also pave the way for transformative advancements in integrated
circuit design, ushering in a new era of technological progress and possibility.
1.4Scope
The scope of designing and simulating a Low Dropout Regulator (LDO) using 180nm
technology encompasses a comprehensive process of engineering analysis and simulation. It
begins with a thorough understanding of the LDO's specifications and requirements, including
voltage levels, load currents, and performance metrics like dropout voltage and transient
response. Subsequently, transistor sizing, topology selection, and control loop design are
undertaken to achieve optimal performance while considering trade-offs in area, power
consumption, and stability. The process involves rigorous simulation and verification using
electronic design automation tools to ensure compliance with design specifications across
process, voltage, and temperature variations. Additionally, layout design, parasitic extraction,
and post-layout simulation are crucial for accurately predicting real-world behavior and
optimizing the design for manufacturability and reliability. Through iterative optimization,
trade-off analysis, and consideration of factors like corner cases and yield, the design and
simulation process culminate in a robust and reliable LDO tailored to the requirements of the

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180nm technology node.

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1.5Objectives
The main objectives are:
 To design and analysis of Low-dropout regulator in 180nm technology by using
cadence virtuoso.
 To design a novel low-pass associated with the bandgap reference circuit in LDO, to
minimize the impact of bandgap noise, achieving highly filtered reference voltage and a
fast-settling time.
 To implement a dynamically operating current limiter using a decent current
comparator limits output current. Area and Power Consumption: In integrated circuit
design, minimizing silicon area and power consumption is crucial for cost-effectiveness
and overall system integration.
1.6Organization of the report
Chapter 1: This chapter provides an introduction to the topic and presents the motivation,
problem statement and objective of the Design and simulation of low drop out voltage regulator
using 180nm technology.
Chapter 2: This chapter describes the literature survey conducted on this topic.
Chapter 3: This chapter describes basic theory and principle of Low Drop out Voltage
Regulator using 180-NM Technology.
Chapter 4: This chapter describes the Design and simulation of low drop out voltage
regulator using 180nm technology methodology.
Chapter 5: This chapter provides output waveforms of Design and simulation of low drop out
voltage regulator using 180nm technology

Summary: This chapter provides a brief introduction to the Design and simulation of low drop
out voltage regulator using 180nm technology and includes the motivation, problem
description, scope and objectives of this topic.

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Chapter 2
LITERATURE SURVEY
This chapter gives in detail about the Literature Survey about proposed project “Design and
Analysis of low drop out voltage regulator using 180-NM CMOS technology” and as a part of
literature survey, many IEEE papers and journals are referred. Few of the papers are briefly
discussed in this section.
[1] A Fully-Integrated 180 nm CMOS 1.2 V Low-Dropout Regulator for Low-Power
Portable Applications (2021).
This paper presents the design and post layout simulation results of a capacitor-less low
dropout (LDO) regulator fully integrated in a low-cost standard 180 nm Complementary Metal-
Oxide-Semiconductor (CMOS) technology which regulates the output voltage at 1.2 V from a
3.3 to 1.3 V battery over a −40 to 120 °C temperature range. To meet with the constraints of
system-on-chip (SoC) battery-operated devices, ultralow power (Iq = 8.6 µA) and minimum
area consumption (0.109 mm2) are maintained, including a reference voltage Vref = 0.4 V. It
uses a high-gain dynamically biased folded-based error amplifier topology optimized for low-
voltage operation that achieves an enhanced regulation-fast transient performance trade-off.
[2] CMOS Low-Dropout Voltage Regulator Design Trends (2022).
Systems-on-Chip’s (SoC) design complexity demands a high-performance linear regulator
architecture to maintain a stable operation for the efficient power management of today’s
devices. Over the decades, the low-dropout (LDO) voltage regulator design has gained
attention due to its design scalability with better performance in various application domains.
Industry professionals as well as academia have put forward their innovations such as event-
driven explicit time-coding, exponential-ratio array, switched RC bandgap reference circuit,
etc., to make a trade-off between several performance parameters such as die area, ripple
rejection, supply voltage range, and current efficiency. However, current LDO architectures in
micro and nanometer complementary metal–oxide–semiconductor (CMOS) technology face
some challenges, such as short channel effects, gate leakage, fabrication difficulty, and
sensitivity to process variations at nanoscale. This review presents the LDO architectures,
optimization techniques, and performance comparisons in different LDO design domains such
as digital, analog, and hybrid. In this review, various state-of-the-art circuit topologies,
deployed for the betterment of LDO performance and focusing on the specific parameter up-
gradation to the overall improvement of the functionality, are framed, which will serve as a
comparative study and reference for researchers.

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[3] Design Trends and Perspectives of Digital Low Dropout Voltage Regulators for Low
Voltage Mobile Applications (2023).
Low-dropout (LDO) voltage regulator has fascinated industry professionals and academia for the past
few decades, and this trend is expected to continue in the coming years. The high demand for a stable
linear regulator architecture that performs well in systems-on-chip (SoC) power management integrated
circuits (PMICs) is a key factor driving innovation with different complementary metal-oxide-
semiconductor (CMOS) technologies. Yet, there are several performance parameter trade-offs to be
considered, such as transient response, output ripple, area, power efficiency, supply voltage range, and
current efficiency in the current LDO design architecture. All these parameter trade-offs become more
severe during the back-end CMOS processes with additional limitations, for example, channel length
modulation, stress sensitivity, and power leakage, among others.
[4] Evaluation and Perspective of Analog Low-Dropout Voltage Regulators (2022).
Low-dropout regulators (LDOs) are widely adopted in power management integrated circuits
(PMICs) and serve as a bridge between the switching regulators and individual on-chip
modules to provide a smooth, regulated output voltage. Compared to digital LDOs (DLDOs),
analog LDOs (ALDOs) lead in the advantage of low output ripple and large power supply
rejection (PSR). However, the preference of achieving high performance in terms of load
transient, high PSR, good load and line regulation, while maintaining a low quiescent current
and low dropout voltage for high efficiency, remains the key challenge in a LDO design.
For operation with a low quiescent current, the bandwidth is reduced due to low
transconductance, resulting in the limited gate driving capabilities in terms of charging and
discharging the large gate capacitance of the pass or output transistor. In addition, the
preference for system-on-chip design in the absence of large off-chip capacitors arises stability
issues. In this paper, recent reported state-of- the-art architectures for ALDOs are revisited and
reviewed. The performance of these ALDOs is compared and their applications are
investigated.
[5] Review on the recent developments in low dropout regulator technology in integrated
circuits (2023).
The low dropout regulator (LDO) is a vital part in power the executives, giving an exact and
stable result voltage against line/load varieties and power supply swell. From a writing audit,
we found that ordinary simple and computerized LDOs actually display challenges to
accomplish great transient reaction or power supply dismissal under specific situations. In this
way, it is clear to join them as a cross breed LDO, partaking in the advantages of the two

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geographies. Then, at that point, we can

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characterize the half and half LDO as simple helped advanced (AAD) and computerized helped
simple (DAA). This short survey relatively past chips away at AAD and DAA LDOs, sums up
their upsides and downsides, and examines conceivable application situations.
[6] A low power external capacitor-less low drop-out regulator with low over/undershoot
voltage and high PSR (2023).
This paper presents a new architecture for improving power supply rejection (PSR) and load
transient response in a capacitor-less low drop-out (LDO) voltage regulator. In the proposed
architecture, inserting a leading path from the power supply to the gate of the pass transistor
keeps the pass transistor gate-source voltage constant in the presence of the supply voltage
ripples that results in the PSR enhancement of the LDO.
In addition, by using a frequency compensation technique, the amount of undershoot and
overshoot voltages in the presence of a sudden change of load current are reduced. Because of
the creation of a zero in the LDO's transfer function, the effect of non-dominant pole on the
phase of LDO is reduced, and a 58° phase margin is achieved without any off-chip capacitor.
As reducing the power consumption as much as possible increases the battery life, therefore, in
addition to using the current- reused technique, the transistors of control circuit are biased in
the subthreshold region.
[7] A wide-temperature range (77–400 K) CMOS low-dropout voltage regulator system
(2020).
In this study, a low-dropout voltage regulator (LDO) system composed of two LDOs, which
can operate in the temperature range of 77–400 K, has been developed. Cryogenic and typical
transistor models of the 180 nm UMC CMOS process have been employed in the design
process. Both LDOs can provide a load current of 100 mA while generating four different
output voltage levels (0.9 V, 1.2 V, 1.5 V, 1.8 V). The LDO system provides 70 mV, 60 mV,
60 mV, and 50 mV dropout voltages at 77 K, and 111 mV, 108 mV, 110 mV, and 82 mV
dropout voltages at 400 K, for the output voltage levels 0.9 V, 1.2 V, 1.5 V, and 1.8 V,
respectively. Post-layout simulation results of the overall LDO system present that the output
voltage varies by 30 mV over the broad range of temperatures from 77 K to 400 K.

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Chapter 3
BASIC THEORY AND PRINCIPLES
An LDO, or Low Dropout Regulator, is a type of voltage regulator that maintains a steady
output voltage even when the input voltage is only slightly higher than the output. It works
using a pass element, usually a transistor, and a feedback control loop to adjust the output as
needed. The main aim is to provide clean and stable power to sensitive parts of a circuit. LDOs
are commonly used because they are easy to design with, don’t need complex components, and
help in reducing noise in analog and mixed-signal systems.

3.1 Voltage Regulators

A voltage regulator is a device engineered to automatically sustain a steady voltage level. It can
employ either a straightforward feed-forward design or incorporate negative feedback. The
regulator might utilize electromechanical mechanisms or electronic components, depending on
its construction. It is capable of regulating one or multiple AC or DC voltages, based on the
specific design.

Fig 3.1: Voltage Regulator

Electronic voltage regulators are commonly used in devices like computer power supplies to
stabilize the DC voltages required by processors and other components. In automobile
alternators and central power station generator plants, these regulators manage the output
voltage. Within an electric power distribution system, voltage regulators can be placed at
substations or along distribution lines to ensure all customers receive a consistent voltage,
regardless of the power drawn from the line. Electronic voltage regulators are commonly used
in devices like computer power supplies to stabilize the DC voltages required by processors and
other components. In automobile alternators and central power station generator plants, these
regulators manage the output voltage.
3.2Types of Voltage Regulator
There are two types of voltage regulator

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3.2.1 Linear Regulator

A linear voltage regulator employs an active pass device, such as a BJT or MOSFET, managed
by a high-gain operational amplifier. To sustain a stable output voltage, the regulator adjusts
the resistance of the pass device by comparing the internal voltage reference with the sampled
output voltage, working to nullify any error

Fig 3.2.1: MP2018 Linear Regulator

There are three types of linear voltage regulator
3.2.1.1 Low dropout voltage:
A low-dropout regulator (LDO regulator) is a DC linear voltage regulator that can operate even
when the supply voltage is very close to the output voltage. The advantages of an LDO
regulator over other DC- to-DC voltage regulators include the absence of switching noise (in
contrast to switching regulators) smaller device size (as neither large inductors nor transformers
are needed);and greater design simplicity (usually consists of a reference, an amplifier, and a
pass element). The disadvantage is that linear DC regulators must dissipate heat in order to
operate.
The main components are a power FET and a differential amplifier (error amplifier). One input
of the differential amplifier monitors the fraction of the output determined by the resistor ratio
of R1 and R2. The second input to the differential amplifier is from a stable voltage reference
(bandgap reference). If the output voltage rises too high relative to the reference voltage, the
drive to the power FET changes to maintain a constant output voltage.

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Fig 3.2.1.1: A low-dropout regulator

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Low-dropout (LDO) regulators function similarly to other linear voltage regulators, but they
differ mainly in their schematic topology. Unlike the emitter follower configuration used in
non-LDO regulators, LDO regulators use an open collector or open drain topology. This design
enables the transistor to be easily driven into saturation with the available voltages, resulting in
a lower voltage drop from the unregulated to the regulated voltage, limited only by the
transistor's saturation voltage.

𝑉OUT=(1+𝑅1/𝑅2) 𝑉REF
For the circuit given in the figure to the right, the output voltage is given as:

When a bipolar transistor is employed instead of a field-effect transistor (FET) or JFET,

additional power may be consumed to control it, unlike non-LDO regulators that derive this
power from the voltage drop itself. For high voltage applications with a very small difference
between input and output voltages, significant power loss can occur in the control circuit.
Additionally, since the power control element functions as an inverter, an additional inverting
amplifier is necessary for its control, making the schematic more complex compared to a
simple linear regulator.
3.2.1.2 Resistor Divider:
The two-resistor voltage divider is one of the most common and useful circuits used by
engineers. The primary purpose of this circuit is to scale down the input voltage to a lower
value based on the ratio of the two resistors. This calculator helps determine the output voltage
of the divider circuit given the input (or source) voltage and the resistor values. Take note that
the output voltage in actual circuits might be different, since resistor tolerance and load
resistance (where the output voltage is connected) become factors.
Output voltage equation: Vout=Vin∗R2/(R1+R2)

Fig 3.2.1.2: Resistor Divider

Fig 3.2.2.2 resister divider network

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3.2.1.3 Zener Diode as Voltage Regulator:

A Zener Diode, also referred to as a breakdown diode, is a specially doped semiconductor
device engineered to function in the reverse direction. When the voltage across a Zener diode’s
terminals is reversed and reaches the Zener Voltage (also known as the knee voltage), the
junction experiences a breakdown, allowing current to flow in the opposite direction. This
phenomenon, known as the Zener Effect, is a key characteristic of Zener diodes. A Zener diode
is a highly doped semiconductor device specifically designed to function in the reverse
direction. It is engineered with a wide range of Zener voltages (Vz), and certain types are even
adjustable to achieve variable voltage regulation.
A Zener diode functions similarly to a regular diode when forward-biased. However, in
reverse-biased mode, a small leakage current flows through the diode. As the reverse voltage
increases and reaches the predetermined breakdown voltage (Vz), current begins to flow
through the diode. This current reaches a maximum level determined by the series resistor, after
which it stabilizes and remains constant across a wide range of applied voltages.

Fig 3.2.1.3: Resistor Divider

3.2.2 Switching Regulator

Switching regulators are versatile, capable of functioning as step-down converters, step-up
converters, or a combination of both, giving them an edge over linear regulators. They offer
several advantages, including high efficiency, superior thermal performance, and support for
higher currents and wider input/output voltage ranges. Depending on the application, they can
achieve efficiency levels exceeding 95%. However, unlike linear regulators, switching power
supplies may necessitate additional external components like inductors, capacitors, FETs, or
feedback resistors. For instance, the HF920 serves as an example of a switching regulator
known for its reliability and efficient power regulation.

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Fig 3.2.2: HF920 Switching Regulator

There are four types of voltage regulator

3.2.2.1 Charge Pump:

A charge pump circuit, or charge pump regulator, is a kind of DC-DC converter that leverages
switched- capacitor techniques to either increase or decrease an input voltage level. As shown
in Figure 1, these circuit blocks generally consist of nothing but capacitors and switches (i.e
clock-controlled field-effect transistors or FETs) and work by carefully timing and controlling
these switches to exploit the charge transfer characteristics of capacitors. Discrete designs
usually use diodes rather than transistors to implement the required switching operation.

Fig 3.2.2.1: HF920 Switching Regulator

Through alternatively charging and discharging capacitors, a charge pump can increase or
decrease a given input voltage to the desired level. From a lower-level perspective, charge
pump circuits work on the basic principle that the voltage across a capacitor cannot change
instantaneously. As defined by the capacitor I-V equation, in order for a capacitor to change its
voltage instantaneously, it would require an

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infinite amount of current.

3.2.2.2 Buck Converter:
The buck converter, also referred to as a step-down converter, is a popular topology in power
electronics that converts a higher input voltage to a lower output voltage. It is crucial in various
applications, from portable devices to automotive systems, where specific components or
subsystems require a lower voltage level to operate. The primary advantage of the buck
converter is its simplicity, which enables efficient voltage conversion using a relatively small
number of components. The operating principle of the buck converter involves controlled
energy transfer from the input to the output through switches, an inductor, and a capacitor. A
high-side switch (usually a MOSFET) and a low-side switch (typically a diode) are employed
in the buck converter to control the current flow through the inductor. By adjusting the duty
cycle of the high-side switch, the average output voltage can be regulated proportionally to the
input voltage.

Fig 3.2.2.2: The Buck Converter Circuit Diagram

When the high-side switch of a buck converter is switched on, it allows current to flow through
the inductor, which stores energy in its magnetic field. This stored energy is then transferred to
the output, charging the output capacitor and powering the load. When the high-side switch is
turned off and the low-side switch is turned on, the inductor's magnetic field collapses,
releasing the stored energy and maintaining the current flow to the load. The buck converter is
designed to operate within a closed-loop control system, where a feedback mechanism
continuously compares the output voltage to a reference voltage to ensure that the output
voltage remains stable and regulated, regardless of changes in input voltage or load conditions.
3.2.2.3 Boost Converter:
Boost converters are a type of DC-DC switching converter that efficiently increase (step-up)
the input voltage to a higher output voltage. By storing energy in an inductor during the switch-
on phase and releasing it to the load during the switch-off phase, this voltage conversion is
made possible. Power

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electronics applications requiring a greater output voltage than the input source, in particular,
depend on boost converters.

Fig 3.2.2.3: The Boost Converter Circuit Diagram

In this converter topology, the magnetic energy of the inductor is used to transfer energy from a
lower voltage DC source to a higher load voltage. By turning on the switch S, the inductor is
connected to the DC power supply E. The diode D is reverse-biased by the voltage at the load
that is supplied with energy from the capacitor. Under the influence of voltage E, the inductor
current linearly increases from its minimum to maximum value.
3.2.2.4 Buck-Boost Converter:
The buck-boost converter is a type of DC-DC converter that can produce an output voltage that
is either higher or lower than the input voltage, making it a versatile power conversion topology
for various applications in power electronics where input voltage regulation and output voltage
requirements may vary. The buck-boost converter operates in two distinct modes: the "buck"
mode, where the output voltage is lower than the input voltage, and the "boost" mode, where
the output voltage is higher than the input voltage. The transition between these two modes is
smooth, enabling the converter to maintain a stable output voltage under varying input
conditions.

Fig 3.2.2.4: The buck-boost converter circuit diagram

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The buck-boost converter operates using a switch, typically a transistor, and a diode, which
control current flow through an inductor and a capacitor. During the switch's ON state, energy
is stored in the inductor, and during the OFF state, the energy is transferred to the output
through the diode. The duty cycle of the switch, or the ratio of ON time to the total period of
the switching cycle, determines the converter's output voltage. Adjusting the duty cycle allows
the output voltage to be controlled and maintained at the desired level.
3.3LDO Voltage Regulator
Low dropout regulators (LDOs) serve as crucial components in power management systems.
These systems, especially those for microprocessors and portable devices, often employ
multiple LDO regulators to furnish a regulated power supply voltage with minimal ripple.
LDOs are generally perceived as a simple and cost-effective means of regulating and
controlling an output voltage derived from a higher input voltage supply.
Linear regulators, including LDOs, dissipate power in the pass transistor or MOSFET used to
regulate and maintain the output voltage within the required accuracy. Consequently, the power
dissipation of an LDO can pose a significant drawback. Therefore, minimizing power losses is
vital for ensuring the efficient operation of LDOs.
3.3.1 LDO Design Parameters Selection:
a) Dropout Voltage
The dropout voltage in a low dropout regulator (LDO) refers to the difference between the
input and output voltages. Typically, it's specified as the input voltage level at which the output
voltage drops 100mV below its programmed, regulated value. As LDOs are tasked with
maintaining a constant voltage output even as the battery discharges, a small dropout voltage is
crucial. A smaller dropout voltage allows for a wider range of useful input voltages from the
battery, thereby extending the device's runtime.

Fig 3.3.1(a): A Typical Power Management System in Soc

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b) Quiescent Current
Also known as ground current, quiescent current refers to the current required to operate the
LDO, which isn't delivered to the load. This current is measured when the LDO is enabled and
the output or load current is zero. A low quiescent current is essential for optimizing LDO
output efficiency, minimizing heat generation, and prolonging battery life in battery-operated
devices.
c) Efficiency
Power efficiency, expressed as the percentage of input power delivered to the load, is a critical
metric in LDO performance. To optimize LDO efficiency, it's essential to minimize both the
output voltage to input voltage difference (Vout / Vin) and the quiescent current. This ensures
that a higher proportion of the input power is effectively utilized and delivered to the load,
enhancing overall efficiency.
d) Power Supply Rejection Ratio (PSSR)
The Power Supply Rejection Ratio (PSRR) assesses an LDO's capability to reject electrical
noise present at its power-supply input. It quantifies this rejection by measuring the alteration
in output noise voltage.
e) Noise
Noise sources in LDOs can generally be classified into two main categories: Intrinsic Noise and
Extrinsic Noise.
f) Output Current Range
The output current handling capacity of the regulated output voltage is a crucial aspect to
consider in LDO design. The minimum current limit is primarily determined by stability
requirements, ensuring that the LDO remains stable under varying load conditions. On the
other hand, the maximum current limit is influenced by factors such as the Safe Operating Area
(SOA) of the pass FET and the need to maintain the output voltage within regulation limits.
g) Output Capacitor Range
This parameter refers to the specified output capacitance that the regulator can handle without
becoming unstable, typically within a specified load current range.
h) Short Circuit Current Limit
This term denotes the current drawn when the output voltage is short-circuited to ground. The
lower limit is typically dictated by the maximum regulated load current, while the upper limit is
primarily determined by the Safe Operating Area (SOA) constraints and specified operational
requirements.
i) Overshoot
Reducing high transient voltages during start-up and load or line transients is crucial for

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ensuring the stability and reliability of the system.

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j) Regulation
There is two types of Static Regulation in LDO
 Line Regulation
Line regulation refers to the variation in output voltage as the supply voltage fluctuates from its
minimum to maximum value. It assesses the circuit's capacity to sustain the specified output
voltage despite fluctuations in the input voltage.
 Load Regulation
Load regulation characterizes the variation in output voltage as the load current ranges from its
minimum to maximum value. It evaluates the circuit's capability to uphold the specified output
voltage across different load conditions.

Fig 3.3.1(j): DC Line (left) Regulation, Load (right) Regulation of 5V Regulator

k) Transient Response
There are two types of transient response
 Line Transient
The line transient response denotes the maximum permissible variation in output voltage
resulting from an input voltage step change. It is influenced by factors such as the gain-
bandwidth of the LDO's control loop, as well as the magnitude and slew rate of the input
voltage alteration
 Load Transient
The load transient response signifies the maximum acceptable fluctuation in output voltage
following a load current step change. This response is determined by various factors, including
the value of the output capacitor and its equivalent series resistance (ESR), the addition of a
bypass capacitor to enhance load transient response, and the maximum load current.

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Fig 3.3.1(k): Transient Response (Left) Line transition, Load (right) transition

l) AC Open Loop Gain Analysis

The open-loop gain of an electronic amplifier refers to the amplification achieved when no
feedback is applied within the circuit. For numerous electronic amplifiers, this open-loop gain
is notably high. In ideal circumstances, an operational amplifier (op-amp) demonstrates an
infinite open-loop gain. This characterization of open-loop gain generally pertains to its value
at a specific frequency is

AOL = Vtest /Vret

3.3.2 Block Level Description

A linear Low Dropout regulator comprises several key components, including a Voltage
Reference, Error Amplifier, Pass Element (often a MOSFET), a feedback network (typically a
resistive voltage divider), an output capacitor, and an Equivalent Series Resistance (ESR).
 Reference Voltage
It serves as the initial reference point for any LDO, establishing the operating conditions for the
Error Amplifier. This component is linked to the inverting terminal of the Error Amplifier.

Figure 3.3.2: Block diagram of an LDO voltage regu1ator

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 Error Amplifier
The sensing element in a voltage regulator detects the difference in voltage between the
reference voltage and the output voltage. This difference is then transmitted to the non-
inverting terminal of the Error Amplifier through the voltage feedback network. The Error
Amplifier amplifies this difference, subsequently controlling the operation of the pass element,
and thus regulating the output voltage.
 Feedback Network
The resistive voltage feedback network functions to either attenuate or amplify the output
voltage, facilitating its comparison with the reference voltage by the Error Amplifier. By
feeding back a fraction of the output voltage to the Error Amplifier, a closed-loop system is
established. This closed-loop setup enhances stability within the system, thereby guaranteeing
precise regulation of the output voltage.
 Pass Element
Typically, the pass element in an LDO is an MOSFET (either PMOS or NMOS). The drain
terminal of the MOSFET is linked to the positive supply voltage, +Vdd. The MOSFET must
operate either in the linear region or the saturation region to facilitate the flow of current from
the input to the load. Its operation is governed by the Error Amplifier within the feedback loop.
3.3.3 Circuit Diagram of an LDO
An LDO typically comprises several essential components: a Voltage Reference, Error
Amplifier, Pass Element (often a MOSFET), feedback network (such as a resistive voltage
divider), output capacitor, and Equivalent Series Resistance (ESR).

Fig 3.3.3: Circuit diagram of an LDO voltage regulator with off-chip capacitor
The reference voltage serves as the initial reference for any LDO, establishing the operating
conditions for the Error Amplifier. Connected to the inverting terminal of the Error Amplifier,
it initiates the regulation process. The Error Amplifier functions as the sensing element,
detecting the voltage discrepancy between the reference voltage and the output voltage. This

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disparity is then conveyed to the non-inverting terminal of the Error Amplifier via the voltage
feedback network.

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The resistive voltage feedback network adjusts the output voltage, enabling its comparison to
the reference voltage by the Error Amplifier. This arrangement forms a closed-loop system,
with a fraction of the output voltage fed back to the Error Amplifier. If the feedback voltage is
lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more
current to pass and increasing the output voltage. Conversely, if the feedback voltage exceeds
the reference voltage, the gate of the PMOS device is pulled higher, reducing current flow and
decreasing the output voltage, thus ensuring stability. The pass element, typically an MOSFET
(PMOS or NMOS), has its drain terminal connected to +Vdd. Operating in either the linear or
saturation region, the MOSFET facilitates current flow from input to load under the control of
the Error Amplifier within the feedback loop.
In LDO regulators, the output capacitor plays a crucial role by ensuring immediate delivery of
current to the load during rapid load transient changes, bridging the gap until the Error
Amplifier stabilizes. The Equivalent Series Resistance (ESR) of the output capacitor prevents
excess current flow from the capacitor to the load, maintaining stability in the system.
3.4Types of LDO Voltage Regulator
There are two types of LDO voltage regulator
3.4.1 PMOS LDO:
The current flowing from input side to the output side passes through the pass element
(PMOS). The R- on resistance (RDS) of the pass element plays a crucial role in determining the
heat loss. Thus, lowering the R-on resistance of PMOS makes it possible to deliver the required
output voltage from a low input voltage and also lowering the heat loss.

Fig 3.4.1: The PMOS LDO circuit

Reference voltage is a steady and accurate voltage, which is used as a standard (reference) to
the error amplifier to determine whether the output voltage is higher or lower than the
required voltage. The

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voltage reference is typically a precision voltage source, such as a bandgap voltage reference or
a precision voltage regulator, that is designed to produce a stable and accurate output voltage.
Quiescent current applies to most integrated circuit (IC) designs, where amplifiers, boost and
buck converters, and low dropout regulators (LDOs) play a role in the amount of quiescent
current consumed.
Feedback circuit is connected between output pin (Vout) and ground. The output voltage is
divided by R1 and R2. The resulting voltage, VFB (which is a required voltage) is fed back to
an error amplifier. Feedback resistor is required because, even if the reference voltage (Vref) is
stable, the error amplifier will not be able make a correct assessment unless it is able to
correctly recognize the state of the output voltage (VFB). If there is any change in the output
voltage the error amplifier will adjust itself and drive the gate voltage of PMOS to certain
voltage level so that the output voltage always constant.
The error amplifier compares the reference voltage (Vref) and Feedback voltage (VFB) to
control the on resistance of pass element (PMOS) to ensure the output voltage (VOUT) is
maintained at the required voltage level. In order to regulate the desired output voltage, the
feedback loop controls the drain-to- source resistance (RDS). As VIN approaches VOUT, the
error amplifier will drive the gate-source voltage more negative in order to lower RDS and
maintain regulation.
3.4.2 NMOS LDO:

Fig 3.4.2: The MOS LDO circuit

In the case of an NMOS architecture, as shown in Figure, the feedback loop still controls RDS.
As VIN approaches VOUT (nom), however, the error amplifier will increase VGS in order to
lower the RDS and maintain regulation. At a certain point, VGS cannot increase any more,
since the error-amplifier output will saturate at the supply voltage, or VIN. When this condition

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is met, RDS is at its minimum value. Multiplying this value against the output current, or
IOUT, derives the dropout voltage. This presents
problem though, because as VIN approaches VOUT (nom), VGS will also decrease, since the
error- amplifier output saturates at VIN. This prevents ultra-low dropout.
3.5Basics of 180nm CMOS Technology
In VLSI (Very Large-Scale Integration), 180 nm technology refers to the semiconductor
manufacturing process node that has a minimum feature size of 180 nanometers. This
technology node represents the size of the smallest components that can be reliably
manufactured on a semiconductor chip. The 180 nm technology was commonly used in the
early 2000s for the production of integrated circuits and microprocessors. As technology has
advanced, smaller process nodes such as 90 nm, 65 nm, and smaller have become more
prevalent, allowing for higher levels of integration and improved performance in electronic
devices.
3.5.1 Features of 180-NM CMOS Technology:
 Feature Size: The most critical feature size in this technology node is 180 nanometers, which
refers to the smallest dimension that can be reliably manufactured on the semiconductor wafer.
 Transistor Characteristics: Transistors in 180nm CMOS technology typically have
characteristics suitable for low-power applications. They offer decent performance with
moderate switching speeds and relatively low power consumption compared to older nodes.
 Supply Voltage: The supply voltage in 180nm CMOS technology is typically in the range of
1.8 to 3.3 volts, depending on the specific design requirements. Lower supply voltages
contribute to lower power consumption.
 Power Consumption: Compared to older technologies, 180nm CMOS technology offers
improved power efficiency due to its smaller feature size and optimized transistor design. This
makes it suitable for battery-powered devices and other applications where power consumption
is critical.
 Integration Density: With a feature size of 180 nanometers, this technology node allows for
higher integration density compared to previous nodes, enabling more transistors to be packed
into a given chip area. This increased density facilitates the design of complex integrated
circuits with multiple functions.
 Cost: While not as cost-effective as newer, more advanced nodes, 180nm CMOS technology
offers a balance between performance, power consumption, and manufacturing cost. It is often
chosen for applications where cost is a significant factor, and the performance requirements do

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not necessitate the latest technology nodes.

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Chapter 4
METHODOLOGY
LDO regulator mainly focuses on achieving a stable and regulated output voltage with minimal
voltage difference between the input and output. The process begins by selecting the
appropriate pass element, usually a PMOS or NMOS transistor, depending on the desired
dropout voltage and control characteristics. A reference voltage generator, typically a bandgap
reference, is used to set a constant voltage that the output should follow. Then, an error
amplifier compares the output voltage with this reference and adjusts the gate of the pass
transistor to maintain regulation. Careful attention is given to the compensation network to
ensure the LDO remains stable across different load conditions. Additionally, parameters like
load regulation, line regulation, dropout voltage, and power supply rejection ratio (PSRR) are
analyzed and optimized. Simulations are carried out at various corners to verify performance
and ensure reliable operation under real-world variations.
4.1 Characterization of MOSFET
Characterization of a MOSFET in Cadence Virtuoso involves analyzing its electrical behavior
under various operating conditions to extract key parameters that define its performance. This
process is crucial for accurate circuit simulation and design validation, especially in analog and
digital VLSI design.
In Cadence Virtuoso, the characterization begins with creating a testbench schematic using the
Virtuoso Schematic Editor. The MOSFET device is selected from the technology library, and
appropriate biasing circuits are designed to perform DC, AC, and transient analyses. The
testbench typically includes a DC voltage source for the gate, drain, and bulk terminals, and a
current meter to measure the drain current. AC analysis is performed to study small-signal
parameters like gain and frequency response, while transient analysis can capture switching
behavior and delay. By plotting these simulation results in the waveform viewer, designers can
extract parameters like gm, ro, Vth, and intrinsic capacitances, which are critical for modeling
and circuit performance. Using the Analog Design Environment, simulations are configured to
sweep parameters such as gate voltage and drain voltage. For instance, sweeping Vgs while
keeping Vds constant gives the Id-Vgs characteristics, which help determine the threshold
voltage (Vth), transconductance (gm), and subthreshold behavior. Similarly, sweeping Vds for
a fixed Vgs yields the Id-Vds curve, useful for identifying the saturation region and output
resistance.

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Overall, MOSFET characterization in Cadence Virtuoso provides a detailed understanding of

device behavior, enabling precise and optimized circuit design in advanced CMOS
technologies.
4.1.1 Characterization of NMOS
Performing the characterization of NMOS involves the construction of circuit as shown in
below figure which involves the usage of NMOS from GPDK-180 library and standard Analog
lib library to use current sources, voltage sources and grounds. By performing this we get
important parameters of NMOS we are using such as Beff, Vth, transconductance, region of
operation of MOSFET and many other characteristics that defines the behavior of MOSFET.
We need to ensure that MOSFET or specifically NMOS is operating in saturation region as we
are dealing with amplifiers. Which can be made sure by simply making sure that the drain to
source voltage is greater then the difference between gate to source voltage and threshold
voltage, also the main purpose of characterization is that with help of beta effective one can
easily find out UnCox which in turn helps to find the aspect ratio of mosfet.
VDS >= VGS - VTH
Where, VDS = Drain to source voltage
VGS = Gate to source voltage
VTH = Threshold voltage

Fig 4.1: Characterization of NMOS

Table 4.1 Parameter of NMOS
Beta effective

Threshold Voltage

Transconductance

Region of operation 2

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In order to perform the characterization of MOSFET we have considered the length to be 1u

and width to be 10u.
from this we get to know UnCox,
Beta eff = UnCox (W / L)
Hence, UnCox = 300 u A/V2
4.1.2 Characterization of PMOS
Performing the characterization of NMOS involves the construction of circuit as shown in
below figure which involves the usage of NMOS from GPDK-180 library and standard Analog
lib library to use current sources, voltage sources and grounds. By performing this we get
important parameters of NMOS we are using such as Beff, Vth, transconductance, region of
operation of MOSFET and many other characteristics that defines the behavior of MOSFET.
We need to ensure that MOSFET or specifically NMOS is operating in saturation region as we
are dealing with amplifiers. Which can be made sure by simply making sure that the drain to
source voltage is greater than the difference between gate to source voltage and threshold
voltage, also the main purpose of characterization is that with help of beta effective one can
easily find out UnCox which in turn helps to find the aspect ratio of mosfet.
VDS >= VGS - VTH
Where, VDS = Drain to source voltage
VGS = Gate to source voltage
VTH = Threshold voltage

Fig 4.2: Characterization of NMOS

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Table 4.1 Parameter of NMOS

Beta effective

Threshold Voltage

Transconductance

Region of operation 2

In order to perform the characterization of MOSFET we have considered the length to be 1u

and width to be 10u.
from this we get to know UnCox,
Beta eff = UnCox (W / L)
Hence, UnCox = 300 u A/V2

4.2 Design of Differential amplifier

A differential amplifier is a fundamental building block in analog circuit design and is widely
used as the input stage of operational amplifiers and other analog systems. It amplifies the
difference between two input voltages while rejecting any common-mode signals. The
differential amplifier exhibits high input impedance and offers excellent common-mode
rejection ratio (CMRR) and power supply rejection ratio (PSRR), which are crucial for noise
immunity and stable operation in mixed-signal environments. In typical applications, it is
followed by gain and buffer stages to form a complete operational amplifier. A differential
amplifier features two primary transistors operating in active mode, with a current source in the
tail to provide biasing. It produces a differential output that reflects the amplified difference
between the input signals. This structure ensures good linearity, high gain, and low offset
voltage. In low dropout (LDO) regulator designs, the differential amplifier is often optimized
using body bias techniques to enhance its performance at low supply voltages and reduce the
dropout voltage. This allows for effective operation even when the input-output voltage
difference is small. Furthermore, careful design using PMOS or NMOS input pairs allows
trade-offs between noise, input range, and gain depending on the application.

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Fig 4.3: Design of schematic of Differential Amplifier

The following design consists of an NMOS differential amplifier with active load as the first
stage followed by a load capacitor a tail is connected by a NMOS which act as a load. A
differential amplifier consists of two inputs if two inputs have same signal then there is no any
change in output signal maintaining the constant voltage and if the signal at two inputs are
different then we can see the difference in the output signal which is different from that of
expected value. Figure 10 shows the schematic implementation of differential amplifier that
works as expected which is verified by its waveform.
Overall, the differential amplifier is essential in providing accurate error detection and signal
conditioning in analog circuits such as operational amplifiers and voltage regulators, enabling
precise control and regulation of the output voltage.
Table 4.1: Design parameters of differential amplifier

Parameters Values
DC Gain 40 dB
GBW
Phase Margin >=50
Slew Rate
Vdd 3.3 v
C 1u F

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ICMR
Power <= 300 uW
VN 400m V
VP 500m v
Idc 10 uA
L 500 n

4.3 Voltage Follower Configuration of Differential amplifier

A differential amplifier, or Differential Amplifier, is commonly used to amplify the difference

between two input signals. However, when configured as a voltage follower, its role shifts from
amplification to buffering. In this specific setup, one of the MOSFETs in the differential pair,
typically labelled as M1, has its drain shorted to the output. This configuration changes the
behaviour of the amplifier so that the output voltage follows the input voltage applied to the
gate of M1.

The differential pair generally consists of two identical MOSFETs, M1 and M2, with their
sources connected together and biased by a constant current source. Their gates receive the
differential inputs, while their drains go to a load or active load. In the voltage follower
configuration, when M1’s drain is shorted to the output node, and its gate is used as the input,
the circuit forms a negative feedback loop. This feedback forces the amplifier to continuously
adjust the output voltage such that the gate voltages of both M1 and M2 match. As a result, the
voltage at the output ends up following the input voltage, hence the name “voltage follower.”

This setup offers several advantages. Since the input is connected to the gate of a MOSFET, the
circuit has a very high input impedance, which is ideal for not loading the previous stage. The
feedback also provides low output impedance, allowing it to drive various loads effectively.
The gain is nearly unity, and the output tracks the input with minimal error. The voltage
follower configuration is especially useful in analog systems where signal buffering, isolation,
or impedance matching is needed.

The reason for shorting M1 to the output is to create a direct link between the input and output
through feedback. Any slight change in the input voltage at M1’s gate is sensed immediately,
and the circuit reacts to bring the output to the same level, minimizing the voltage difference

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between the gates of M1 and M2. This dynamic response makes the circuit stable and accurate,
especially when used in precision analog applications.

Fig 4.4: Voltage follower Configuration of differential amplifier

Fig 4.3.1differential amplifier as a voltage follower

The schematic shown is part of a Low Dropout Regulator (LDO) design, specifically
representing the error amplifier block, not the full LDO. The error amplifier is a crucial
component in any LDO architecture as it determines how accurately and quickly the regulator
can maintain a stable output voltage. This block compares the output feedback voltage with a
known reference and adjusts the control signal to the pass element accordingly.
In this circuit, the differential amplifier is implemented using a pair of NMOS transistors (m0
and m1) acting as the input stage. These are biased by a constant current source (I1 = 50 µA),
ensuring steady operation across supply variations. The output of the differential pair is fed into
a PMOS current mirror (m4, m5) that acts as an active load, converting the differential signal
into a single-ended output.
This output then drives a second NMOS stage (m6 or m8, depending on naming), possibly
forming a gain stage or buffer, which would ultimately control the gate of the pass transistor
in the full LDO (not shown here). The reference voltage source (Vref = 1.2V) is applied at
one of the differential inputs, and the output feedback (from the LDO's output node) is

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connected to the other. The capacitor (C0 = 10pF) is likely placed for compensation, to
ensure phase margin and stability.
4.4Design of LDO
A low dropout regulator (LDO) consists of a voltage reference, an error amplifier, a feedback
voltage divider, and a series pass element, usually a bipolar or CMOS transistor (see Figure 1).
Output current is controlled by the PMOS transistor, which in turn is controlled by the error
amplifier. This amplifier compares the reference voltage with the feedback voltage from the
output and amplifies the difference. If the feedback voltage is lower than the reference voltage,
the gate of the PMOS device is pulled lower, allowing more current to pass and increasing the
output voltage.
If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is
pulled higher, allowing less current to pass and decreasing the output voltage. Analog Devices
LDOs are designed to be stable over the specified operating temperature and voltage ranges
when the recommended capacitors are used. The ESR of the output capacitor affects the
stability of the LDO control loop. LDO regulators are used to derive lower output voltages
from a main supply or battery. The output voltage is ideally stable with line and load variations,
immune to changes in ambient temperature, and stable over time. LDOs should have as low a
difference between the input and output voltage.
Table 4.6: Design variables of LDO

Parameters Values
I_load 20mA
RL 12M
RF 12M
Vdd 3.3V
W_M3 2u
L_M3 1u
Ids 10u
W_M1 20u
L_M1 1u
W_TAIL 9u
L_TAIL 1u
W_PASS 4m
L_PASS 1u

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Fig 4.6: Schematic of LDO

1. Understanding the Design Goals

Before starting the actual design, I first focused on understanding what the LDO is supposed to do.
The goal is to step down the input voltage of 3.3V to a stable 2.4V while supplying up to 20mA to
the load. This means the regulator should maintain 2.4V at the output even when small variations
occur at the input or load. Since the dropout voltage is 0.9V, we have enough headroom to design a
traditional LDO without the need for boost circuits or charge pumps.

2. Choosing the Right Architecture

For this specification, we decided to use a PMOS-based LDO architecture. This type of design is
simpler to implement for lower current levels and works well without the need for additional high-
side driving circuits.
 PMOS pass elements allow easy gate control using ground-referenced amplifiers.
 They consume less static power in light-load applications like mine.
 I also avoided NMOS-based designs to keep the circuit compact and avoid extra complexity (like
charge pumps).

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3. Designing the Reference Voltage Source

Since the output voltage is 2.4V, we needed a reference voltage lower than that usually around 1.2V.
we used a fixed 1.2V DC voltage source in simulations to act as my reference. In real chip design,
this would be replaced by a bandgap reference, but for now, we kept it ideal to focus on the core
regulator behaviour.

4. Building the Error Amplifier

The core of the LDO is the error amplifier. we designed this as a differential pair using NMOS
transistors, biased by a constant current source. The amplifier compares the feedback voltage from
the output with the 1.2V reference and adjusts the gate voltage of the PMOS pass transistor to keep
the output stable.
Key points about my amplifier design:
 NMOS input pair for better matching and low offset.
 PMOS current mirror used as the load for high gain.
 Tail current source of around 10µA to ensure proper biasing.
 A compensation capacitor at the output for stability.

5. Connecting the Pass Transistor

The output of the error amplifier is connected to the gate of a PMOS pass transistor. This PMOS is
placed between the input (3.3V) and output (2.4V). It acts like a variable resistor, allowing just the
right amount of current to flow to maintain the target voltage.
To ensure that the pass transistor can deliver the required 20mA, we calculated its W/L ratio using
basic current equations and then verified its behaviour through simulation.

6. Adding Feedback and Voltage Divider

To allow the error amplifier to “sense” the output voltage, we connected a resistor divider from the
output back to one input of the amplifier. The other input is the 1.2V reference. The divider reduces
2.4V to 1.2V, so that the amplifier can regulate based on this comparison.
For example:
 If R1 = R2 = 12MΩ, then Vfb = 2.4V × (12M / (12M+ 12M)) = 1.2V
This simple method allowed me to control the regulation point accurately.

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7. Ensuring Stability with Compensation

One of the most important steps in LDO design is to make sure the system doesn’t oscillate. We
added a small compensation capacitor (around 1uF) at the amplifier output and also included a
capacitor at the LDO output terminal. These helped to stabilize the loop and improve phase margin.
 Output cap: Helps smooth transient changes in load current.
 Compensation cap: Ensures the loop gain rolls off properly.

8. Simulating and Validating the Design

Once all blocks were connected, we performed several simulations to check if the LDO behaves as
expected:
 DC Operating Point Analysis: Verified that Vout = 2.4V at steady state.
 Transient Simulation: Applied load steps (e.g., from 5mA to 20mA) to see if the output stays
regulated.
 Line Regulation Test: Varied Vin from 3.2V to 3.4V and checked Vout.
 Load Regulation Test: Changed load current from 0 to 20mA and observed the response.
We also checked the power consumption of the biasing and amplifier circuits to ensure the overall
design is power-efficient.

VDD

M3

VX
VIN M1

Design of M3 & M4
VDS1 > VGS1 – Vth1
VD1 > VG1 – Vth1
VX > 2.4 – 0.4
So, VDS3 = VDD - Vx
= 3.3 – 2.4
VDS3 = 0.9
We know that I3 = 15m A

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From current equation of MOSFET we get,

UpCox W 2
I 3= [V GS −V th ]
2 L
60 u W 2
15m A = [0.9−0.5]
2 L
W
=1
L

Design of Power FET

VDD

The current equation is given by,

UpCox W 2
I D= [Vs−Vg−Vth ]
2 L
We know that, ID = 20m A
UpCox = 60u
VS = 3.3 V
Vth = 0.5 V
VG = 2.4 V
So,
60 u W 2
20 m= [3.3−2.4−0.5]
2 L

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 Low Dropout Voltage Regulator 2024-25

W
=4000
L
Considering L to be 1u meter then,
W = 4m meter

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Chapter 5
RESULTS
5.1 DC Operating Point Analysis

The dc analysis of the LDO as shown in Fig 5.1 shows that the LDO operates from the range of
1.6V to 2V with a constant output voltage of 1.2V for the input voltage of 1.8V.

Fig 5.1. DC Operating Point

5.2 Analysis Involving Checking Transistor Regions

This type of analysis typically involves checking the operating regions of the transistors in the
LDO circuit to ensure proper functionality and performance. By this analysis , we seen that all
PMOS and NMOS transistors of LDO are operating in region 2 (Saturation Region ). In

saturation region all NMOS and PMOS specifies the condition for NMOS : Vds ≥ Vgs – Vth
and for PMOS : Vsd ≥ Vsg- Vth. In the saturation region, the transistor provides a stable and
high gain, which is essential for maintaining the regulator's output voltage.

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 Low Dropout Voltage Regulator 2024-25

Fig 5.2. Analysis of Transistor Regions

5.3 Line Regulation
Line regulation is the ability of a power supply to maintain a constant output voltage despite
changes to the input voltage, with the output current drawn from the power supply remaining
constant. It is desirable for a power supply to maintain a stable output regardless of changes in
the input voltage. The line regulation is important when the input voltage source is unstable or
unregulated and this would result in significant variations in the output voltage. The line
regulation for an unregulated power supply is usually very high for a majority of operations,
but this can be improved by using a voltage regulator.

Fig 5.1: Circuit of Line regulation

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 Low Dropout Voltage Regulator 2024-25

 Line regulation is the ability of a power supply to maintain a constant output voltage of
1.2volts, despite changes to the input voltage, input voltage is changed from 1.6V to 2V with
the output current drawn from the power supply remaining constant
5.4 Load regulation
Load regulation refers to the ability to maintain a constant voltage output from a power supply
despite changes or variability in the input load. Typically, we express load regulation as a
percentage of the max load condition, indicating how much output will vary. When it comes to
load regulation, the lower the percentage the better. An ideal system would vary 0 percent in
response to changes in load. Of course, this ideal scenario doesn’t exist in the real world, but
it’s possible to achieve load regulations of fractions of a percent with good design. We can
achieve load regulation in one of two ways: with a linear regulator or a switch-mode power
supply. We’ll explore linear regulators below, but you can learn more about switch-mode
power supplies.

Fig 5.2: Output of load regulation

 Load regulation refers to the ability to maintain a constant output voltage of 1.2V from a
power supply despite changes or variability in the input current from 100ua to 1mA. Typically,
we express load regulation as a percentage of the max load condition, indicating how much
output will vary. When it comes to load regulation, the lower the percentage the better.

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5.5 Parametric analysis

parametric analysis provides insight into how an analysis model responds to changes in its
constituent parameters (or independent variables). This is accomplished by selecting one or
more independent variables and vary them within a given range while observing how one or
more dependent variables react. Parametric analysis is used to evaluate a range of values for an
intervention (independent variable). For example, if you were determining the range of values
for “time out” that are most effective.

Fig 5.3.1: Waveform1 parametric analysis

Fig 5.3.2: Waveform2 parametric analysis

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5.6 Applications of LDO

1. Portable and Battery-Powered Devices:
LDOs are widely used in smartphones, tablets, laptops, and wearable devices to provide stable
voltage to sensitive components like processors and sensors, ensuring efficient battery usage
and extending battery life.
2. Communication Equipment:
In telecommunications and networking equipment, LDOs help maintain consistent voltage
levels for various circuits, ensuring reliable signal processing and communication.
3. Consumer Electronics:
Devices such as televisions, audio systems, and gaming consoles use LDOs to deliver stable
power to different electronic components, enhancing performance and reliability.
4. Medical Devices:
LDOs are crucial in medical equipment like patient monitors, diagnostic machines, and
portable medical devices, where stable and noise-free power is essential for accurate readings
and operation.
5. Automotive Electronics:
In automotive systems, LDOs are used to power sensors, microcontrollers, and other electronic
control units (ECUs), ensuring they operate correctly under varying voltage conditions.
6. Industrial Automation:
LDOs are employed in industrial control systems, robotics, and automation equipment to
provide clean and stable power to sensitive control circuits and sensors, improving system
reliability and precision.
7. RF and Analog Circuits:
LDOs are preferred in RF (Radio Frequency) and analog circuit applications because they offer
low noise performance, which is crucial for maintaining signal integrity and minimizing
interference.
8. Memory Modules:
In memory modules like DRAM and flash memory, LDOs provide precise voltage regulation,
ensuring data integrity and reliable operation.
9. LED Drivers:
LDOs are used in LED lighting applications to provide a consistent current, which helps in
maintaining uniform brightness and extending the lifespan of LEDs.

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10. FPGA and ASIC Power Supplies:

Field-Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits
(ASICs) often require multiple precise voltage levels, which LDOs can supply effectively.
5.7 Advantages of LDO
1. Simplicity:
LDOs are straightforward in design, requiring fewer external components compared to
switching regulators. This simplicity translates to easier implementation and reduced overall
design complexity.
2. Low Noise:
LDOs provide a very clean output voltage with low noise and ripple, making them ideal for
powering sensitive analog and RF circuits where noise can be a significant issue.
3. Fast Transient Response:
LDOs typically have a fast response to changes in load conditions, ensuring stable output
voltage even with sudden variations in load.
4. Compact Size:
Due to fewer external components, LDOs can be integrated into smaller packages, which is
beneficial for space-constrained applications.
5. Quicker Design Cycles:
The simplicity and fewer design considerations of LDOs allow for quicker design cycles and
faster time- to-market for products.
6. Cost-Effective:
With fewer components and simpler design, LDOs can be more cost-effective than switching
regulators, especially in low-power applications.
5.8 Disadvantages of LDO
1. Efficiency:
LDOs are generally less efficient compared to switching regulators, especially when there is a
significant difference between the input and output voltage. This inefficiency leads to higher
power dissipation and heat generation.
2. Heat Dissipation:
Because of their lower efficiency, LDOs dissipate more power as heat, requiring careful
thermal management and potentially larger heat sinks or more effective cooling solutions.

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3. Limited Input-Output Voltage Differential:

LDOs require the input voltage to be only slightly higher than the output voltage. If the input
voltage drops too close to the output voltage, the LDO may not be able to maintain regulation.
4. Lower Current Capability:
LDOs are typically suitable for low to moderate current applications. High current
demands can exacerbate efficiency and thermal management issues.
5. Noisy Input Sensitivity:
LDOs can be sensitive to input noise and may require additional filtering if the input voltage is
not clean.
6. Limited Applications for High Power:
Due to the efficiency and heat dissipation issues, LDOs are less suitable for high-power
applications compared to switching regulators.

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CONCLUSION
The proposed circuit has been simulated using 180nm technology in Cadence software and the
simulation results have been analyzed. The proposed circuit provides a constant output voltage
of 1.2V for the input voltage range of 1.6 to 2.0V with input current 60uA and reference
voltage 1.05V. The Drop-out Voltage is 300mV and the Power dissipation of the LDO is
9.75mWatt. According to the continuous survey, the supply voltage range and foundry of the
technology are both continuously decreasing as technology advances. Reduced technology
allows for decreased power usage.
Depending on the control signals, we can develop a low power, LDO that can produce a range
of output voltages. At the frequency of unity gain, the PSR of the LDO is high. A high pass
filter can be inserted to further. The addition of this block would enhance PSR at the necessary
high frequency without impairing low frequency PSR characteristics. The LDO's settling time
is a few microseconds or less. This is impacted on by the loop's low GBW. This can be made
better by increasing the LDO's GBW. However, this has an impact on stability or can be
achieved with more power.
The design and analysis of a Low Drop-Out (LDO) regulator using 180-nm CMOS technology
were conducted to achieve high performance in terms of power efficiency, output voltage
stability, and load regulation. The conclusions derived from this study highlight the
effectiveness of the chosen technology and design methodology, demonstrating the feasibility
of integrating LDO regulators into modern electronic systems with stringent power
requirements. The LDO regulator designed using 180-nm CMOS technology exhibited high
efficiency, particularly at low dropout voltages. Stability in the output voltage is critical for the
reliable operation of sensitive electronic circuits. The results showed a quick response time and
minimal voltage drop, showcasing the robustness of the design. The choice of 180-nm CMOS
technology provided a balance between performance, cost, and scalability. The smaller feature
size allowed for higher integration density, reduced parasitic capacitances, and improved
overall performance of the LDO regulator.

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BIBILOGRAPHY
[1] G.A. Rincon-Mora, and P. E. Allen, “A Low Voltage, Low Quiescent Current, Low
Drop-Out Regulator,” IEEE J. Solid State Circuits, vol. 33, no.1, pp.36-44, Jan.1998
[2] H. Lee, P. K. T Mok, K. N. Leung, "Design of Low-Power Analog Driver Based on
Slew-Rate Enhancement Circuit for CMOS Low-Dropout Regulators," IEEE Trans. on Circuits
and Systems II, vol. 52, no 9. pp. 563 – 567, Sept. 2005.
[3] K. N. Leung., P. K. T. Mok, “A Capacitor -Free CMOS Low-Dropout Regulator
with Damping- Factor-Control Frequency Compensation,” IEEE J. Solid State Circuits, vol. 38,
no. 10, pp. 1691-1702, Oct 2003.
[4]C-H. Lee, K. McClellan, and J. Choma Jr., “A supply noise insensitive CMOS PLL with a
voltage regulator using DC-DC capacitive converter,” IEEE J. Solid State Circuits, vol. 26, no.
10, pp. 1453- 1463, Oct. 2001.
[5] W. Oh and B. Bakkaloglu, “A CMOS Low -Dropout Regulator With Current-Mode
Feedback Bu ffer Amplifier,” IEEE Trans. on Circuit sand Systems II, vol 54, no. 10, pp.922 -
926, Oct.2007.
[6] S. K. Hoon, S. Chen, F. Maloberti, J. Chen, and B. Aravind, “A low noise, high power
supply rejection low dropout regulator for wireless system-on-chip applications,” Proc. IEEE,
Custom Integrated Circuits Conference. pp. 754 -757, Sept. 2005.
[7] C.K. Chava and J. Silva-Martinez, “A Frequency Compensation Scheme for LDO
Voltage R egulators,” IEEE Trans. on Circuits and Systems I, vol. 51, no 6. pp. 1041 – 1050,
June 2004.
[8] O. Moreira-Tamayo “A high current low dropout regulator with dual output stage and
dual control loop,”48th Midwest Symposium on Circuits and Systems, vol. 2, pp. 992 – 995,
2005.
[9] C. Lin and Q. Feng, “Design of current limiting circuit in low dropout linear voltage
regulator,” Microwave Conference Pro ceding, 2005.
[10] M. Hammes, C. Kranz, D. Seippel, J. Kissing, and A. Leyk, “Evolution on SoC
Integration: GSM Baseband-Radio in 0.13um CMOS Extended by Fully Integrated Power
Management Unit”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 1,
JANUARY 2008.
[11] Mohamed El-Nozahi, etal, "High PSR Low Drop-Out Regulator With Feed-Forward
Ripple Cancellation Technique", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45,

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 Low Dropout Voltage Regulator 2024-25

NO. 3, pp. 565- 577, Mar. 2010.

[12] G. Morita, ”Understand Low-Dropout Regulator (LDO) Concepts to Achieve Optimal
Designs “Analog Dialogue 48-12, December 2014

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[13] Y. Lu, M. Huang, R. P. Martins, “PID control considerations for Analog Digital
Hybrid Low Dropout Regulators”, Proceedings of IEEE ISCAS 2020.
[14] S. Gangopadhyay, Y. Lee, S. B. Nasir, A. Raychowdhury, “Modeling and Analysis of
Digital Linear Dropout Regulators with Adaptive Control for High Efficiency under Wide
Dynamic Range Digital Loads”
[15] E Sanchez Sinencio, "Low dropout voltage regulators”, Report Analog and Mixed-
Signal Center, Texas A&M University

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