The salient features of 8085 Microprocessor are:

1. It is a 8 bit microprocessor.
2. It is manufactured with N-MOS technology.
3. It contains 6200 transistors approx.
4. Its dimensions are164 mm x 222 mm.
5. It has 16-bit address bus and hence can address up to 216 = 65536 bytes (64KB)
memory locations through A0-A15.
6. The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0 – AD7.
7. Data bus is a group of 8 lines D0 – D7.
8. It supports external interrupt request.
9. A 16 bit program counter (PC)
10. A 16 bit stack pointer (SP)
11. Six 8-bit general purpose register (B, C, D, E, H, L) arranged in pairs: BC, DE, HL.
12. It requires a signal +5V power supply and operates at 3.2 MHZ single phase clock.
13. It is enclosed with 40 pins DIP (Dual in line package).
14. It has three advanced versions:8085 AH, 8085 AH1, 8085 AH2 These advanced
Versions are designed using HMOS technology.

Pin Diagram
 Pin 1 and Pin 2 (Input) [X1 & X2]: These are also called Crystal Input Pins. 8085 can
generate clock signals internally. To generate clock signals internally, 8085 requires
external inputs from X1 and X2.

Pin 3 (Output) [RESET OUT]: It is used to reset the peripheral devices and other ICs on
the circuit. It is an output signal. It is an active high signal. The output on this pin goes
high whenever RESET IN is given low signal. The output remains high as long as RESET
IN is kept low.

Pin 4 (Input) [SID (Serial Input Data)]: It takes 1 bit input from serial port of 8085.
Stores the bit at the 8th position (MSB) of the Accumulator. RIM (Read Interrupt Mask)
instruction is used to transfer the bit.

Pin 5 (Output)[ SOD (Serial Output Data)]: It takes 1 bit from Accumulator to serial
port of 8085. Takes the bit from the 8th position (MSB) of the Accumulator. SIM (Set
Interrupt Mask) instruction is used to transfer the bit.

Interrupt: It means interrupting (disturbing) the normal execution of the microprocessor.

When microprocessor receives interrupt signal, it discontinues whatever it was executing.
It starts executing new program indicated by the interrupt signal. Hardware interrupt
signals are generated by external peripheral devices.8085 microprocessor has five
hardware Interrupts: TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR. Whenever any
interrupt occurs the program control goes to specified address defined for respective
interrupt signal.
The addresses to which program control goes:
Interrupt Vector Address
Signal
RST 7.5 003C H

RST 6.5 0034 H

RST 5.5 002C H

TRAP 0024 H

[Note: Absolute address is calculated by multiplying the RST value with 0008 H.]
Whenever there exists a simultaneous request at two or more pins then the pin with higher
priority is selected by the microprocessor. Priorities of interrupt signals are as follows
Interrupt Priority
1. TRAP 1
2. RST 7.5 2
3. RST 6.5 3
4. RST 5.5 4
5. INTR 5
 Pin 6 (Input) [TRAP]: It is a non-maskable interrupt (it cannot be disabled by any
means.). It has the highest priority among all interrupt signals. It remains high for a
certain period of time. TRAP is usually used for power failure and emergency shutoff.

Pin 7 (Input) [ RST 7.5]: It is a maskable interrupt. It has the second highest priority. It is
positive edge triggered only (active high signal).

Pin 8 (Input) [RST 6.5]: It is a maskable interrupt. It has the third highest priority. The pin
has to be held high for a specific period of time. RST 6.5 can be enabled by EI
instruction. It can be disabled by DI instruction.

Pin 9 (Input) [RST 5.5]: It is a maskable interrupt. It has the fourth highest priority.

Pin 10 (Input) [INTR]: It is a maskable interrupt. It has the lowest priority. It is also level
triggered.

Pin 11 (Output)[ INTA]: It is an active low out going signal. Low output on this pin
indicates that microprocessor has acknowledged the INTR request.

Pin 12-19 (Bidirectional) [AD0 – AD7]: These pins serve the dual purpose of
transmitting lower order address and data byte. During 1st clock cycle, these pins act as
lower half of address. In remaining clock cycles, these pins act as data bus. The
separation of lower order address and data is done by address latch.

Pin 20 (Input) [VSS]: Ground signal is connected to VSS

Pin 21-28 (Unidirectional) [A8 – A15]: These pins carry the higher order of address bus.
The address is sent from microprocessor to memory.

Pin 30 (Output) [ALE]: It is used to enable Address Latch. It indicates whether bus
functions as address bus or data bus. If ALE = 1 then Bus functions as address bus. If
ALE = 0 then Bus functions as data bus.

Pin 29 (Output) and Pin 33 (Output) [S0 and S1]: S0 and S1 are called Status Signal
Pins.
They indicate the current operation which is in progress in 8085.
S0 S1 Operation
Pin 31 (Output)[ WR]: WR stands for Write. It is also active low control signal, used for
Write operation either into memory or into output device. A low signal indicates that data
on the data bus must be written into selected memory location or into output device.

Pin 32 (Output)[RD]: RD stands for Read. It is an active low control signal, used for Read
operation either from memory or from Input device. A low signal indicates that data on
the data bus must be placed either from selected memory location or from input device.
Pin 34 (Output)[IO/M]: IO/M indicates whether the Read/Write is to memory or l/O
devices. If it is high then microprocessor will performs the operation with I/O devices
whereas if it low, then microprocessor will perform the read/write operation with
memory.

Pin 35 (Input) [READY]: This pin is used to synchronize slower peripheral devices with
fast microprocessor. A low value causes the microprocessor to enter into wait state. The
microprocessor remains in wait state until the input at this pin goes high. If Ready is high
during a read or writes cycle, it indicates that the memory or peripheral is ready to send or
receive data

Pin 36 (Input) [RESET IN]: It is an active low input signal. Low signal on this pin resets
the microprocessor.

Pin 38 (Input)[HOLD]: HOLD pin is used to request the microprocessor for DMA
transfer. A high signal on this pin is a request to microprocessor to relinquish the hold on
buses. This request is sent by DMA controller.

Pin 39 (Output) [HLDA]: HLDA stands for Hold Acknowledge. The microprocessor uses
this pin to acknowledge the receipt of HOLD signal. When HLDA signal goes high,
address bus, data bus, RD, WR, IO/M pins are tri-stated. This means they are cut-off

from external environment. The control of these buses goes to DMA Controller and it
remains until HOLD is held high. Whenever HOLD goes low, HLDA also goes low and
the microprocessor takes control of the buses.

Pin 40 (Input): +5V power supply is connected to VCC.

Architecture of 8085The architecture of 8085 consist various components like.
1: Register.
2: ALU.
3: Instruction decoder and machine cycle encoder.
4: Address buffer.
5: Address/data buffer.
6: Inc/Dec latch.
7: Interrupt control
8: Serial i/o like SOD, SID.
9: Timing and Control circuit.

Arithmetic Logic Unit

The ALU performs the actual numerical and logic operation such as ‘add’, ‘subtract’,
‘AND’, ‘OR’, etc. Uses data from memory and from Accumulator to perform arithmetic.
Always stores result of operation in Accumulator.
Registers
The 8085/8080A-programming model includes six registers, one accumulator, and
one flag register, as shown in following figure.

General Purpose Register

The 8085/8080A has six general-purpose registers to store 8-bit data; these are identified
as B, C, D, E, H, and L as shown in the figure. They can be combined as register pairs -
BC, DE, and HL - to perform some 16-bit operations. The programmer can use these
registers to store or copy data into the registers by using data copy instructions. In
addition, it has two 16-bit registers: the stack pointer and the program counter.

Accumulator
The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This
register is used to store 8-bit data and to perform arithmetic and logical operations. The
result of an operation is stored in the accumulator. The accumulator is also identified as
register A.

Flags
It includes five flip-flops, which are set or reset after an operation according to data
conditions of the result in the accumulator and other registers. They are called Zero (Z),
Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags. The most commonly
used flags are Zero, Carry, and Sign. The microprocessor uses these flags to test data
conditions.

CY [Carry]: The carry status flag holds the carry out of the most significant bit resulting
from the execution of an arithmetic operation. If there is a carry from addition or a
borrow from subtraction (or comparison),the carry flag is set to 1;otherwise 0.
 P [Parity]: The parity status flag is set to 1 when the result of the operation contains even
number of 1s.It is set to zero when there is a odd number of 1s.

AC [Auxiliary Carry]: In an arithmetic operation, when a carry is generated by digit D3

and passed on digit D4( carry shifted from lower nibble to higher nibble) , the AC flag is
set.

Z [Zero]: The zero status flag Z is set to 1 if the result of an arithmetic or logical
operation is zero. For non-zero result it is set to 0.

S [Sign]: The sign status flag is set to 1 if the most significant bit of the result of an
arithmetic or logical operation is 1, otherwise 0.

Remaining three bits are undefined or reserve for the future use.

Program Counter (PC)

This 16-bit register deals with sequencing the execution of instructions. This register is a
memory pointer which points 16-bit Memory address of next byte is to be fetched. When
a byte (machine code) is being fetched, the program counter is incremented by one to
point to the next memory location.

Instruction Register/Decoder
It is used as a temporary store for the current instruction of a program. Instruction register
holds the instruction until it gets decode. Decoder then takes instruction and ‘decodes’ or
interprets the instruction. Decoded instruction then passed to next stage.
.
Stack Pointer (SP)
The stack pointer is also a 16-bit register and it holds the address of stack top. The stack
is an area of memory identified by the programmer for temporary storage of information.
The stack is a LIFO structure. The stack normally grows backwards into memory.
Programmer can defines the bottom of (SP) the stack and the stack grows up into
reducing address range. This register is always decremented/incremented by 2 during
PUSH and POP instructions respectively.
 The 8085 Addressing Modes
An instruction is a command to the microprocessor to perform a given task on specified
data. Each instruction has two parts; one is the task to be performed called operation code
or opcode. The second one is called the data to be operated on, known as an operand. The
operand can be specified in various ways. It may include 8 bit (or 16 bit) data, an internal
register, a memory location, or an 8-bit or 16-bit address. In some instructions, the
operand is implicit. Such various formats for specifying operands are called the
addressing modes. For 8085, they are:
1. Immediate Addressing.
2. Register Addressing.
3. Direct Addressing.
4. Indirect Addressing.
5. Implicit Addressing.

Immediate Addressing: In this addressing mode the operand is specified in the instruction
itself. It is used to load the immediate data to the destination provided.
Example: MVI R, data.
MVI A, 05 ;In this instruction, second byte represents data

Register Addressing: In this addressing mode, the data is provided in the instruction through
the registers. In other words we can say data resides in the register, and instruction part may
consist of that register.
Example: ADD B

Direct Addressing: In this mode of addressing the address of the operand (data) is given in
the instruction itself.
Example: STA 2400H
In this instruction 2400H is the memory address where data is to be stored. It is given in the
instruction itself.

Indirect Addressing: In this mode of addressing the address of the operand is specified by a
register pair.
Example: LXI H, 2500H
MOV A, M
HLT
In the above example, instruction MOV A, M is an example of register indirect addressing.
For this instruction the operand is in the memory. The address of the memory resides in H-L
pair.

Implicit Addressing: There are certain instructions which operate on the content of the
accumulator. Such instructions do not require the address of the operand.
Example: CMA, RAR, RAL etc.
Instruction Format

An instruction is a command to the microprocessor to perform a given task on a specified

data. Each instruction has two parts: one is task to be performed, called the operation code
(opcode), and the second is the data to be operated on, called the operand. The operand (or
data) can be specified in various ways. It may include 8-bit (or 16-bit ) data, an internal
register, a memory location, or 8-bit (or 16-bit) address. In some instructions, the operand is
implicit. The 8085 instruction set is classified into the following three groups according to
word size:
1. One-word or 1-byte instructions
2. Two-word or 2-byte instructions
3. Three-word or 3-byte

One-Byte Instruction
A One byte instruction includes the opcode and the operand in the same byte.
Example: ADD B
MOV C, A
CMA

Two-Byte Instructions:
The first byte specifies the operation code (opcode) and second byte specifies the operand.
These instructions would require two memory locations. First memory location is to be used
for opcode and second memory location for the operand.
Example: MVI A, 32H

Three Byte Instructions

In three byte instruction, the first byte specifies the opcode, and the following two bytes
specify the 16-bit address. Second byte is low order address and the third byte is the high
order address. Since it consists of three bytes, it would require minimum three memory
locations to store each binary code.
Example: LDA 2050H
JMP 2450H
  Instruction Sets

The 8085 instruction can be classified into five categories:

1. Data transfer (copy) operations: This group of instructions copies data from source
location to destination location without modifying the content of the source.
2. Arithmetic operations: The arithmetic instructions adds, subtracts, increment, or
decrement data in register or memory
3. Logical operations: This group of instructions performs the logical operations such as
AND, OR, Exclusive-OR on data in register/memory with the content of the
accumulator.
4. Branching operations: This group of instructions changes the normal sequential
program flow, either conditionally or unconditionally.
5. Machine-control operations

DATA TRANSFER INSTRUCTIONS

Sr. Instructions Description Example

No
MOV Rd, Rs This instruction copies the contents of the
1 MOV M,Rs source register into the destination register;
MOV Rd, M the contents of the source register are not MOV B, C
altered. If one of the operands is a memory MOV B, M
(Copy from source to
destination) location, its location is specified by the
contents of the HL registers.
[Rs: Source Reg. Rd: Destination Reg.]

2 MVI Rd, data The 8-bit data is stored in the destination

MVI M, data MVI B, 57H
register or memory. If the operand is a MVI M, 57H
memory location, its location is specified
(Move immediate 8-bit)
by the contents of the HL registers.

The contents of a memory location,

3 LDA 16-bit add. specified by a 16-bit address in the
LDA 2034H
operand, are copied to the accumulator.
(Load accumulator) The contents of the source are not altered.

LDAX B/D Reg pair The contents of the designated register pair
4 point to a memory location. This
(Load accumulator instruction copies the contents of that
indirect) memory location into the acc. The contents LDAX B
of either the register pair or the memory
location are not altered.
5 LXI Reg. pair, 16-bit data The instruction loads 16-bit data in the
(Load register pair LXI H, 2034H
register pair designated in the operand.
immediate 16-bit data)

The instruction copies the contents of the

6 LHLD 16-bit address memory location pointed out by the 16-bit
LHLD 2040H
address into register L and copies the
(Load H and L registers
direct) contents of the next memory location into
register H. The contents of source memory
locations are not altered

The contents of the accumulator are copied

into the memory location specified by the
7 STA 16-bit address STA 4350H
operand. This is a 3-byte instruction, the
(Store accumulator
direct) second byte specifies the low-order address
and the third byte specifies the high-order
address

The contents of the accumulator are copied

8 STAX Reg. pair into the memory location specified by the STAX B
(Store accumulator
contents of the operand (register pair). The
indirect)
contents of the accumulator are not altered.

The contents of register L are stored into

the memory location specified by the 16-
bit address in the operand and the contents
SHLD 16-bit address of H register are stored into the next SHLD 2470H
9
(Store H and L registers memory location by incrementing the
direct) operand. The contents of registers HL are
not altered. This is a 3-byte instruction, the
second byte specifies the low-order address
and the third byte specifies the high-order
address.

The contents of register H are exchanged

10 XCHG with the contents of register D, and the XCHG
(Exchange H and L with contents of register L are exchanged with
D and E)
the contents of register E.
 The instruction loads the contents of the H
and L registers into the stack pointer
11 SPHL register, the contents of the H register SPHL
provide the high-order address and the
(Copy H and L registers
to the stack pointer) contents of the L register provide the low-
order address. The contents of the H and L
registers are not altered.

The contents of the L register are

12 XTHL exchanged with the stack location pointed
. out by the contents of the stack pointer XTHL
(Exchange H and L with register. The contents of the H register are
top of stack) exchanged with the next stack location
(SP+1); however, the contents of the stack
pointer register are not altered.

The contents of the register pair designated

in the operand are copied onto the stack in
the following sequence. The stack pointer
register is decremented and the contents of
PUSH Reg. pair PUSH B
13 the high order register (B, D, H, A) are
(Push register pair onto copied into that location. The stack pointer PUSH A
stack) register is decremented again and the
contents of the low-order register (C, E, L,
flags) are copied to that location.

The contents of the memory location

pointed out by the stack pointer register are
copied to the low-order register (C, E, L,
POP Reg. pair status flags) of the operand. The stack
POP H
pointer is incremented by 1 and the
14 (Pop off stack to register
pair) contents of that memory location are POP A
copied to the high-order register (B, D, H,
A) of the operand. The stack pointer
register is again incremented by 1.

15 OUT 8-bit port address The contents of the accumulator are copied
(Output data from into the I/O port specified by the operand. OUT F8H
accumulator to a port
with 8-bit address)
 The contents of the input port designated in
16 IN 8-bit port address the operand are read and loaded into the IN 8CH
(Input data to accu. from
accumulator.
a port with 8-bit
address)

ARITHMETIC INSTRUCTIONS

Sr. Instructions Description Example

No

The contents of the operand (register or

17 ADD R memory) are M added to the contents of the
ADD M accumulator and the result is stored in the ADD B
(Add register or accumulator. If the operand is a memory ADD M
memory to location, its location is specified by the
accumulator) contents of the HL registers. All flags are
modified to reflect the result of the addition.

The contents of the operand (register or

18 ADC R memory) and M the Carry flag are added to
ADC M the contents of the accumulator and the ADC B
(Add register to result is stored in the accumulator. If the ADC M
accumulator with operand is a memory location, its location is
carry) specified by the contents of the HL
registers. All flags are modified to reflect
the result of the addition.

19 ADI 8-bit data The 8-bit data (operand) is added to the

(Add immediate data to contents of the accumulator and the result is ADI 45H
accumulator) stored in the accumulator. All flags are
modified to reflect the result of the addition.

The 8-bit data (operand) and the Carry flag

20 ACI 8-bit data are added to the contents of the accumulator
(Add immediate to and the result is stored in the accumulator. ACI 45H
accumulator with All flags are modified to reflect the result of
carry) the addition.

The 16-bit contents of the specified register

21 DAD Reg. pair pair are added to the contents of the HL
(Add register pair to H register and the sum is stored in the HL DAD H
and L registers) register. The contents of the source register
 pair are not altered. If the result is larger
than 16 bits, the CY flag is set. No other
flags are affected.

22 SUB R The contents of the operand (register or

SUB M memory) are M subtracted from the
(Subtract register or contents of the accumulator, and the result LHLD 2040H
memory from accu.) is stored in the accumulator. If the operand
is a memory location, its location is
specified by the contents of the HL
registers. All flags are modified to reflect
the result of the subtraction.

The contents of the operand (register or

memory) and M the Borrow flag are
23 SBB R subtracted from the contents of the
SBB M accumulator and the result is placed in the SBB B
(Subtract source and accumulator. If the operand is a memory SBB M
borrow from location, its location is specified by the
. accumulator) contents of the HL registers. All flags are
modified to reflect the result of the
subtraction.

The 8-bit data (operand) is subtracted from

24 SUI 8-bit data the contents of the accumulator and the
(Subtract immediate result is stored in the accumulator. All flags SUI 45H
data from accumulator) are modified to reflect the result of the
subtraction.

The 8-bit data (operand) and the Borrow

SBI 8-bit data flag are subtracted from the contents of the
25 (Subtract immediate accumulator and the result is stored in the SBI 45H
from accumulator with accumulator. All flags are modified to
borrow) reflect the result of the subtraction.

The contents of the designated register or

26 INR R memory) are M incremented by 1 and the
INR M result is stored in the same place. If the INR B
(Increment register or operand is a memory location, its location is INR M
memory by 1) specified by the contents of the HL
registers.

INX R The contents of the designated register pair

27 (Increment register pair are incremented by 1 and the result is stored INX H
by 1) in the same place.
28 DCR R The contents of the designated register or
. DCR M memory are M decremented by 1 and the DCR B
(Decrement register or result is stored in the same place. If the DCR M
memory by 1) operand is a memory location, its location is
specified by the contents of the HL
registers.

29 DCX R The contents of the designated register pair

(Decrement register are decremented by 1 and the result is stored DCX H
pair by 1) in the same place.

The contents of the accumulator are

changed from a binary value to two 4-bit
binary coded decimal (BCD) digits. This is
the only instruction that uses the auxiliary
30 DAA flag to perform the binary to BCD
conversion, and the conversion procedure is
(Decimal adjust described below. S, Z, AC, P, CY flags are DAA
accumulator) altered to reflect the results of the operation.
If the value of the low-order 4-bits in the
accumulator is greater than 9 or if AC flag
is set, the instruction adds 6 to the low-order
four bits. If the value of the high-order 4-
bits in the accumulator is greater than 9 or if
the Carry flag is set, the instruction adds 6
to the high-order four bits.

LOGICAL INSTRUCTIONS

Sr. Instructions Description Example

No

The contents of the operand (register or

memory) are M compared with the contents
31 CMP R of the accumulator. Both contents are CMP B
CMP M preserved. The result of the comparison is CMP M
shown by setting the flags of the PSW as
(Compare register or follows:
memory with if (A) < (reg/mem): carry flag is set
accumulator) if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero flags are
reset.
 The second byte (8-bit data) is compared
with the contents of the accumulator. The
CPI 8-bit data values being compared remain unchanged.
32 The result of the comparison is shown by
(Compare immediate setting the flags of the PSW as follows: CPI 89H
with accumulator) if (A) < data: carry flag is set
if (A) = data: zero flag is set
if (A) > data: carry and zero flags are reset

The contents of the accumulator are

logically ANDed with M the contents of the
ANA R operand (register or memory), and the result
33 ANA M is placed in the accumulator. If the operand
is a memory location, its address is ANA B
(Logical AND register specified by the contents of HL registers. S, ANA M
or memory with Z, P are modified to reflect the result of the
accumulator) Operation. CY is reset. AC is set.

34 ANI 8-bit data The contents of the accumulator are

logically ANDed with the 8-bit data
(Logical AND (operand) and the result is placed in the acc. ANI 86H
immediate with S, Z, P are modified to reflect the result of
accumulator) the operation. CY is reset. AC is set.

The contents of the accumulator are

35 XRA R Exclusive ORed with M the contents of the
XRA M operand (register or memory), and the result
is placed in the accumulator. If the operand XRA B
(Exclusive OR register is a memory location, its address is XRA M
or memory with specified by the contents of HL registers. S,
accumulator) Z, P are modified to reflect the result of the
operation. CY and AC are reset.

The contents of the accumulator are

36 XRI 8-bit data Exclusive ORed with the 8-bit data
(operand) and the result is placed in the XRI 86H
(Exclusive OR accumulator. S, Z, P are modified to reflect
immediate data with the result of the operation. CY and AC are
accumulator) reset.

The contents of the accumulator are

37 ORA R logically ORed with M the contents of the
ORA M operand (register or memory), and the result
is placed in the accumulator. If the operand ORA B
(Logical OR register or is a memory location, its address is ORA M
. memory with specified by the contents of HL registers. S,
accumulaotr) Z, P are modified to reflect the result of the
operation. CY and AC are reset.

The contents of the accumulator are

38 ORI 8-bit data logically ORed with the 8-bit data (operand)
(Logical OR immediate and the result is placed in the accumulator. ORI 86H
with accumulator) S, Z, P are modified to reflect the result of
the operation. CY and AC are reset.

Each binary bit of the accumulator is rotated

39 RLC left by one position. Bit D7 is placed in the
(Rotate accumulator position of D0 as well as in the Carry flag. RLC
left) CY is modified according to bit D7. S, Z, P,
AC are not affected.

Each binary bit of the accumulator is rotated

40 RRC right by one position. Bit D0 is placed in the
(Rotate accumulator position of D7 as well as in the Carry flag. RRC
right) CY is modified according to bit D0. S, Z, P,
AC are not affected.

Each binary bit of the accumulator is rotated

41 RAL left by one position through the Carry flag.
Bit D7 is placed in the Carry flag, and the
(Rotate accumulator Carry flag is placed in the least significant RAL
left through carry) position D0. CY is modified according to
bit D7. S, Z, P, AC
are not affected.

Each binary bit of the accumulator is rotated

RAR right by one position through the Carry flag.
42 Bit D0 is placed in the Carry flag, and the
. (Rotate accumulator Carry flag is placed in the most significant RAR
right through carry) position D7. CY is modified according to
bit D0. S, Z, P, AC are not affected.

The contents of the accumulator are

43 CMA complemented. No flags are affected. CMA
(Complement accu.)

44 CMC The Carry flag is complemented. No other CMC

(Complement carry) flags are affected.

45 STC The Carry flag is set to 1. No other flags are STC

(Set Carry) affected.
CONTROL INSTRUCTIONS

Sr. Instructions Description Example

No

46 NOP No operation is performed. The instruction

(No operation) is fetched and decoded. However no NOP
operation is executed.

47 HLT The CPU finishes executing the current

instruction and halts any further execution. HLT
(Halt and enter An interrupt or reset is necessary to exit
wait state) from the halt state.

48 DI The interrupt enable flip-flop is reset and all

(Disable the interrupts except the TRAP are disabled. DI
interrupts) No flags are affected.

The interrupt enable flip-flop is set and all

interrupts are enabled. No flags are affected.
After a system reset or the
49 EI acknowledgement of an interrupt, the
(Enable interrupts) interrupt enable flip flop is reset, thus EI
disabling the interrupts. This instruction is
necessary to re-enable the interrupts (except
TRAP).

50 RIM This is a multipurpose instruction used to

(Read interrupt read the status of interrupts 7.5, 6.5, 5.5 and RIM
mask) read serial data input bit.

51 SIM This is a multipurpose instruction and used

(Set interrupt to implement the 8085 interrupts 7.5, 6.5, SIM
mask) 5.5, and serial data output.
Branching Instructions

Sr. Instructions Description Example

No
JMP 16-bit address The program sequence is transferred to the
52 (Jump memory location specified by the 16-bit JMP 2034 H.
unconditionally) address given in the operand.

Jx 16-bit address The program sequence is transferred to the

53 (Jump memory location specified by the 16-bit JZ 2034 H.
unconditionally) address given in the operand based on the
specified flag of the PSW.

The program sequence is transferred to the

CALL 16-bit address memory location specified by the 16-bit
(CALL address given in the operand. Before the
54 conditionally) transfer, the address of the next instruction CALL 2034 H.
after CALL (the contents of the program
counter) is pushed onto the stack.

The program sequence is transferred to the

memory location specified by the 16-bit
Cx 16-bit address address given in the operand based on the
55
(CALL specified flag of the PSW. Before the CZ 2034 H
conditionally) transfer, the address of the next instruction
after the call (the contents of the program
counter) is pushed onto the stack.

The program sequence is transferred from

56 RET
the subroutine to the calling program. The RET
(RETURN two bytes from the top of the stack are
unconditionally) copied into the program counter, and
program execution begins at the new
address.

The program sequence is transferred from

Rx the subroutine to the calling program based
57 on the specified flag of the PSW. The two
(RETURN bytes from the top of the stack are copied RZ
unconditionally) into the program counter, and program
execution begins at the new address.

The RST instruction jumps the control to

one of eight memory locations depending
58 RST 0 –RST 7 upon the number. These are used as RST 3
software instructions in a program to
 transfer program execution to one of the
eight locations.
Jump Unconditionally

Call Conditionally
Return Conditionally

Restart Addressable Table

 INSTRUCTION SET SUMMARY

DATA TRANSFER INSTRUCTIONS

MOV Copy from source to destination
MVI Move immediate 8-bit
LDA Load accumulator
LDAX Load accumulator indirect
LXI Load registers pair immediate
LHLD Load H and L registers direct
STA Store accumulator direct
STAX Store accumulator indirect
SHLD Store H and L registers direct
XCHG Exchange H and L with D and E
SPHL Copy H and L registers to the stack pointer
XTHL Exchange H and L with top of stack
PUSH Push register pair onto stack
POP Pop of stack to register pair
OUT Output data from accumulator to a port with 8-bit address
IN Input data to accumulator from a port with 8-bit address

ARITHMETIC INSTRUCTIONS
ADD Add register or memory to accumulator
ADC Add register to accumulator with carry
ADI Add immediate to accumulator
ACI Add immediate to accumulator with carry
DAD Add register pair to H and L registers
SUB Subtract register or memory from accumulator
SBB Subtract source and borrow from accumulator
SUI Subtract immediate from accumulator
SBI Subtract immediate from accumulator with borrow
INR Increment register or memory by 1
INX Increment register pair by 1
DCR Decrement register or memory by 1
 DCX Decrement register pair by 1
DAA Decimal adjust accumulator
CONTROL INSTRUCTIONS
NOP No operation
HLT Halt
DI Disable interrupts
EI Enable interrupts
RIM Read interrupt mask
SIM Set interrupt mask

BRANCHING INSTRUCTIONS
JMP Jump unconditionally
JC Jump on carry
JNC Jump on no carry
JP Jump on positive
JM Jump on minus
JZ Jump on zero
JNZ Jump on no zero
JPE Jump on parity even
JPO Jump on parity odd
CALL Call unconditionally
CC Call on carry
CNC Call on no carry
CP Call on positive
CM Call on minus
CZ Call on zero
CNZ Call on no zero
CPE Call on parity even
CPO Call on parity odd
RET Return unconditionally
RC Return on carry
RNC Return on no carry
RP Return on positive
RM Return on minus
 RZ Return on zero
RNZ Return on no zero
RPE Return on parity even
RPO Return on parity odd
PCHL Load program counter with HL contents
RST Restart

LOGICAL INSTRUCTIONS
CMP Compare register or memory with accumulator
CPI Compare immediate with accumulator
ANA Logical AND register or memory with accumulator
ANI Logical AND immediate with accumulator
XRA Exclusive OR register or memory with accumulator
XRI Exclusive OR immediate with accumulator
ORA Logical OR register or memory with accumulator
ORI Logical OR immediate with accumulator
RLC Rotate accumulator left
RRC Rotate accumulator right
RAL Rotate accumulator left through carry
RAR Rotate accumulator right through carry
CMA Complement accumulator
CMC Complement carry
STC Set carry
Program 1: Addition of two 8-bit numbers; Sum 8-bits.
1. Add 23H and 41H.
2. First numbers is at memory location 6501H.
3. Second number is at memory location 6502H.
4. The result is to be stored at location 6503H

Memory Machine Mnemonics Operands Comments

Address Codes
2000 21,01,65 LXI H,6501H Get address of first no.in H-L pair
2003 7E MOV A,M First no. in accumulator
2004 23 INX H Increment content of H-L pair
2005 86 ADD M Add two numbers
2006 32,03,65 STA 6503H Store result of addition in 6503H
2009 76 HLT Stop the execution

Input Data: Output Data (Result):

6501: 23H 6503: 64H
6502: 41H
Program 2: Subtraction of two 8-bit numbers; Result 8-bits.
1. The first number 41H is at location 6501H.
2. Second number 23H is at location 6502H.
3. The result is to be stored in the memory location 6503H.
Memory Machin Mnemonics Operands Comments
Address e
Codes
2000 21,01,6 LXI H,6501H Get address of first no.in H-L pair
5
2003 7E MOV A,M First no. in accumulator
2004 23 INX H Increment content of H-L pair
2005 96 SUB M First numbers - second number
2006 23 INX H Content of HL pair becomes 6503H
2007 77 MOV M,A Stor result in 6503H
2008 76 HLT Stop
 Input Data: Output Data(Result):
6501: 41H 6503: 18H
6502: 23H
Program 3: Program to find larger of two numbers

1. The first number 65H is placed in the memory location 6501H.

2. Second number 54H is placed in the memory location 6502H.
3. The result is stored in the memory location 6503H.

Memor Machine Label Mnemonics Operands Comments

y Codes
Address
2000 21,01,65 LXI H,6501H Get address of first no. in H-L
pair
2003 7E MOV A,M First no. in accumulator
2004 23 INX H Address of second no. in H-L
pair
2005 BE CMP M Compare two numbers
Is second no.larger than first?
2006 D2,0A,20 JNC AHEAD No,Larger no.is in accumulator.
Go to label AHEAD
2009 7E MOV A,M Yes,Get second no. in
accumulator
200A 32,03,65 AHEA STA 6503H Store larger number in 6503H.
D
200D 76 HLT STOP

Input Data: Output Data (Result)

6501: 65H 6503: 65H
6502: 54H

Result is 65H and it is stored in memory location 6503H

8-BIT ADDITION USING ACCUMULATOR

PROGRAM:

Memor Machine Label Mnemonics Operands Comments

y Code
Address
8000 3A,00, 20 LDA 2000 Load contents of address 2000 (Input
1) into the accumulator
8003 47 MOV B,A Shift contents of accumulator to
register B
8004 3A,01, 20 LDA 2001 Load contents of address 2001(Input
2) into the accumulator
8007 80 ADD B Add data in B to accumulator & store
in the accumulator
8008 32, 02 ,20 STA 2002 Store the (Result) contents of
accumulator to address 2002
800B DA, 14 ,80 JC Loc1 Jump to Loc1 if carry is 1

800E 3E ,00 MVI A,00 Store value 00 in accumulator

8010 32 ,03 ,20 STA 2003 Store the (Carry) contents of

accumulator to address 2003
8013 76 HLT End of Program

8014 3E, 01 Loc 1 MVI A,01 Store value 01 in accumulator

8016 32, 03 ,20 STA 2003 Store the (Carry) contents of

accumulator to address 2003
8019 76 HLT End of Program

INPUT & OUTPUT:

Location Values
2000 42
2001 35
 2002 RESULT 77
2003 CARRY 00

Program 4: 8-BIT ADDITION WITH MEMORY POINTER

Program:

Memor Machine Label Mnemonics Operands Comments

y Code
Address
8000 21 01 82 LXI H, 8201 Setting pointer for getting data

8003 0E 00 MVI C ,00 Clearing register C for carry

8005 7E MOV A, M Getting Data 1 into the accumulator

from memory
8006 23 INX H Increment pointer to the next
memory location
8007 86 ADD M Add second data to Accumulator and
store it in accumulator
8008 D2 0C 80 JNC Ahead Ahead If carry is '0' , go to location
'Ahead'
800B 0C INR C If carry is '1' , Increment register C to
1
800C 23 Ahead INX H Increment pointer to the next
memory location
800D 77 MOV M,A Store Sum in memory

800E 23 INX H Increment pointer to the next

memory location
800F 71 MOV M,C Store Carry in memory

8010 76 HLT End of Program

INPUT & OUTPUT:

Location Values
8200 54
8201 A1
8202 RESULT F5
8203 CARRY 00