Keerti Thakur

Central Processing Unit

Notes

CONTENTS
Objectives
Introduction
An Overview of the CPU
General Register Organization
Stack Organization
Register Stack
Memory Stack
Instruction Format
Summary
Keywords
Self Assessment
Review Questions
Further Readings

Objectives

After studying this unit, you will be able to:

• Explain the functions of CPU
• Explain the general register organization
• Describe stack organization
• Discuss instruction format
Introduction
The Central Processing Unit (CPU) is the heart of a computer system. The
CPU along with the memory and the I/O sub-systems develops a powerful
computer system.
Companies such as AMD, IBM, Intel, Motorola, SGI, and Sun manufacture
CPUs that are used in various kinds of computers such as desktops,
mainframes, and supercomputers. A CPU comprises thin layers of thousands
of transistors. Transistors are microscopic bits of material that block
electricity at one voltage (non-conductor) and allow electricity to pass through
them at different voltage (conductor). These tiny bits of materials are the
semiconductors that take two electrical inputs and generate a different output
when one or both inputs are switched on. As CPUs are small, they are also
referred to as microprocessors.

Did u know? CPU is an old term that was used for processor or multiprocessor.
Modern CPUs are called as integrated chips. It is so called because several
types of components such as execution core, Arithmetic Logic Unit (ALU),
registers, instruction memory, cache memory, and the input/output controller
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are integrated into a single piece of silicon.

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Notes
Example: Intel makes Pentium series of processors, whereas AMD makes the
Athlon and Duron processors.
An Overview of the CPU
Central Processing Unit (CPU) is the most important unit in a computer system. It
is the component which controls all internal and external devices as well as
performs arithmetic and logic operations to execute the set of instructions
stored in the computer’s memory.
A CPU comprises three major components. They are:
• Register Set
• ALU
• Control Unit (CU)
Register Set
The register set differs from one system to another. The register set
comprises many registers which include general purpose registers and special
purpose registers. The general purpose registers do not perform any specific
function. They store the temporary data that is required by a program. The
special purpose registers perform specific functions for the CPU.

Example: Instruction Register (IR) is a special purpose register that

stores the instruction that is currently being executed.
ALU
The ALU performs all the arithmetic, logical, and shift operations by
providing necessary circuitry that supports these computations.
Control Unit
The control unit fetches the instructions from the main memory, decodes the
instructions, and then executes it. The control unit is discussed in detail in the
units ahead.

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Notes
Figure 1 illustrates the components of the CPU.

Figure .1: Components of CPU

As shown in figure .1, the CPU consists of the register set, ALU, and CU.
The CPU interacts with the main memory and input/output devices. The
CPU reads and writes data to and from the memory system and transfers data
to and from the I/O devices.
A simple execution cycle in the CPU can be described as below:
1. The CPU fetches the instruction to be executed from the main memory
and stores it in the Instruction Register (IR).
2. The instruction is decoded.
3. The operands are fetched from the memory system and stored in the CPU
registers.
4. The instructions are then executed.
5. The results are transferred from the CPU registers to the memory system.

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Notes Operand is the part of a computer instruction that is manipulated and operated.
In the addition of 5 + x, ‘5’ and ‘x’ are operands and ‘+’ is the operator.

If there are more instructions to be executed, the execution cycle repeats. Any
pending interrupts are also checked during the execution cycle.

Example: The interrupts such as I/O device request, arithmetic overflow,

or pages is checked during the execution cycle.
Notes The actions of the CPU are defined by the micro-orders issued by the
control unit. The micro- orders are the control signals, which are sent over
specified control lines.

Example: Suppose you need to execute an instruction that moves the contents
of register A to register B. If both the registers are connected to data bus C,
then the control unit issues a micro- order (control signal) to register A to
place its contents on the data bus C. Another micro-order is sent to register B
to read from data bus C. The control signals are activated either through
hardwired control or microprogramming.

Thus, CPU is the primary element of a computer system, which carries out
each instruction of a program to perform basic arithmetical, logical, and
input/output operations.
General Register Organization
A group of flip-flops form a register. A register is a special high speed storage
area in the CPU. They comprise combinational circuits that perform data
processing. The data is always represented in a register before processing.
The registers speed up the execution of programs.
Registers perform two important functions in the CPU operation. They are:
1. Providing a temporary storage area for data. This helps the currently
executing programs to have a quick access to the data, if needed.
2. Storing the status of the CPU as well as information about the currently
executing program.
Example: Address of the next program instruction, signals received from
the external devices and error messages, and such other information is stored
in the registers.
We know that referring to memory locations is considered difficult and time
consuming. Hence, storing the pointers, return addresses, temporary results,
and program counters into the register is more efficient than the memory. The
number of registers varies from one computer system to another.

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If a CPU contains a number of registers, then a common bus is used to

Notes
connect these registers. A general organization of seven CPU registers is
shown in figure 2.

Figure 2: General Organization of

Register s

As observed in figure 2, the CPU bus system is operated by the control unit.
The control unit directs the information flow through the ALU by selecting
the function of the ALU as well as components of the system.
Consider R1 R2 + R3, the following are the functions performed within the CPU:

MUX A Selector (SELA): It is used to place R2 into bus A

MUX B Selector (SELB): It is used to place R3 into bus B
ALU Operation Selector (OPR): It selects the arithmetic addition (ADD)
Decoder Destination Selector (SELD): It transfers the result into R1.
The multiplexers of 3-state gates are implemented with the buses. The state of 14
binary selection inputs specifies the control word. The 14-bit control word
specifies a micro-operation.

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Notes
The encoding of register selection fields are specified in table 1.
Table 1: Encoding of Register Selection Field

Binary Code SELA SELB SELD

000 Input Input None
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7

Various micro-operations are performed by the ALU. Some of the

operations performed by the ALU are listed in table 2.
OPR Operatio Symbo
Select n l
00000 Transfer A TSFA
00001 Increment INCA
A
00010 Add A + B ADD
00101 Subtract A SUB
-B
00110 Decrement DECA
A
01000 ADD A AND
and B
01010 OR A and OR
B
01100 XOR A XOR
and B
01110 Comple COMA
ment A
10000 Shift right SHRA
A
11000 Shift left A SHLA

Table 7.2: Encoding of ALU Operations

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Some of the ALU micro-operations are shown in the table 7.3:

Micro- SE SETable SE
7.3: ALU Micro-Operations
OP Control
oper ation LA LB LD R Word
R1  R2 – R2 R3 R1 SUB 010 011 001 001
R3 01
R4  R4 R4 R5 R4 OR 100 101 100 010
R5 10
R6  R6 + R6 - R6 INC 110 000 110 000
1 A 01
R7  R1 R7 - R1 TSF 001 000 111 000
A 00
Output  R2 - Non TSF 010 000 000 000
R2 e A 00
Output  Input - Non TSF 000 000 000 000
Input e A 00
R4  shl R4 - R4 SHL 100 000 100 110
R4 A 00
R5  0 R5 R5 R5 XO 101 101 101 011
R 00

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Types of Registers
There are many different types of register available in the market.
Some of them are:
1. Data Register: It is used to store data.
2. Accumulator Register: It is considered as a special data register.
3. Address Register: It holds the memory address.
4. Index Register: It holds the index of the memory address.
5. Condition Register: It determines whether the instruction should be
executed or not.
6. General Purpose Register: It stores data and addresses.
7. Special Purpose Register: It stores the status of the programs.
8. Floating Point Register: It is a kind of data register that stores the floating
point numbers.
9. Constant Register: It stores read-only values.
General purpose registers are also called as processor registers. These
processor registers provide the fastest means to access data.

Did u know? Processor register is mostly found at the top of the memory
hierarchy.
7.1 Stack Organization
Stack, also called as Last In First Out (LIFO) list, is the most useful feature in
the CPU. It stores information such that the item stored last is retrieved first.
Stack is a memory unit with an address register. This register holds the
address for the stack, which is called as Stack Pointer (SP). The stack pointer
always holds the address of the item that is placed at the top of the stack.
You can insert an item into or delete an item from the stack. The insertion
operation is called as push operation and the deletion operation is called as pop
operation. In a computer stack, these operations are simulated by incrementing
or decrementing the SP register.
7.1.1 Register Stack
Stack can be organized as a collection of memory words or registers. Consider a
64-word register stack organized as shown in figure 3.
The stack pointer register contains a binary number, which is the address of the
item present at the top of the stack. The three items A, B, and C are placed in
the stack. The item C is at the top of the stack and the stack pointer holds the
address of C that is, The top item is popped from the stack by reading memory
word at address 3 and decrementing the stack pointer by 1. Now, B is at the
top of the stack and the SP holds the address of B that is, 2. To insert a new
word, the stack is
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pushed by incrementing the stack pointer by 1 and inserting a word in that

incremented location.

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Notes Figure 3 depicts 64-word stack.

Figure 3: 64-word Stack

Here, the stack pointer contains 6 bits, since 26 = 64, and the SP cannot exceed 63
(111111 in binary) because if 63 is incremented by 1, then the result is 0(111111
+ 1= 1000000). SP holds only the six least significant bits. If 000000 is
decremented by 1 then the result is 111111. Thus, when the stack is full, the
one bit register ‘FULL’ is set to 1. If the stack is empty, then the one bit
register ‘EMTY’ is set to 1. The data register DR holds the binary data
which is written into or read out of the stack.
First the SP is set to 0, EMTY is set to 1, and FULL is set to 0. Now, as the
stack is not full (FULL = 0), a new item is inserted using the push operation.
The push operation is performed as below:
SP SP + 1, stack pointer is incremented
K[SP] DR, place an item on the top of
the stack If (SP = 0) then (FULL 1),
check if stack is full
EMTY 0, if stack is full, then mark the stack as not empty
The stack pointer is incremented by 1 and the address of the next higher word
is stored in the SP. The word from DR is inserted into the stack using the
memory write operation. As per figure 5.3, the first item is stored at address 1
and the last item is stored at address 0. If the stack pointer is at 0, then the
stack is full and ‘FULL’ is set to 1. This is the condition when the SP was in
location 63 and after incrementing SP , the last item is stored at address 0. Once
an item is stored at address 0, there are no more empty registers in the stack.
The stack is full and the ‘EMTY’ is set to 0.
You can perform pop operation (deletion) only if the stack is not empty. To
delete an item from the stack, the following micro-operations are performed.
DR K[SP], an item is read from the top
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of stack SP SP – 1, stack pointer is

decremented
If(SP = 0) then (EMTY 1), check if stack
is empty FULL 0, if stack empty, then
mark the stack empty
The top item from the stack is read and sent to DR and then the stack pointer
is decremented. If the stack pointer reaches 0, then the stack is empty and
‘EMTY’ is set to 1. This is the condition when the item in location 1 is read
out and the SP is decremented by 1.

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Notes

! If stack is pushed when FULL = 1 or popped when EMTY = 1, you get an erroneous
Caution
result.
7.1.2 Memory Stack
Stack can be implemented in the CPU by allotting a portion of the computer
memory to a stack operation and using a processor register as a stack pointer.
In this case, it is implemented in a random access memory attached to the
CPU.
In figure 7.4, a portion of the computer memory is divided into three
segments: program, data and stack. The address of the next instruction in the
program is stored in the pointer Program Counter (PC). The Address Register
(AR) points to an array of the data. SP always holds the address of the item
present at the top of the stack. The three registers that are connected to the
common bus are PC, AR, and SP. PC is used to read the instruction during
fetch phase. An operand is read during execute phase using address register.
An item is pushed into or popped from the stack using stack pointer. Figure
4 depicts the memory stack.

Figure 4: Memory Stack

In figure 4, the SP points to an initial value ‘2001’. Here, the stack grows
with decreasing addresses. The first item is stored at address 2000, the next
item is stored at address 1999 and the last item is stored at address 1000.
As we already know, data register is used to read an item into or from the stack.
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You use push operation to insert a new item into the stack.SP SP -1 K[SP] DR

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Notes To insert another item into the stack, the stack pointer is
decremented by 1 so that it points at the address of the next
location/word. A word from DR is inserted into the top of the
stack using memory write operation.
To delete an item from the stack, you need to use the pop operation:
DR K[SP]
SP SP + 1
The top item is read into the DR and then the stack pointer
is decremented to point to the next item in the stack.
Here, two processor registers are used to check the stack
limits. One processor register holds the upper limit (1000) and
the other holds the lower limit (2001). During push operation,
the SP is compared with the upper limit to check if the stack
is full. During pop operation, the SP is compared with the
lower limit to check if the stack is empty.
An item in the stack is pushed or popped using two micro-
operations. They are:
1. Accessing the memory through SP
2. Updating SP
A stack pointer is initially loaded with the bottom address of
the stack in memory. Thereafter, SP is automatically
incremented or decremented depending on the operation
performed (push or pop). As the address is automatically
updated in the stack pointer, the CPU can refer to the memory
stack without specifying the address.
7.2 Instruction Format
An instruction consists of a combination of operation codes
and operands that deal with the operation codes. Instruction
format basically provides the layout of bits in an instruction.
It includes fields such as opcode, operands, and addressing
mode. The instruction length is usually kept in multiples of
the character length, which is 8 bits. When the instruction
length is fixed, a number of bits are allocated to opcode,
operands, and addressing modes. The bits are distributed such
that if more number of bits is allocated to the opcode field,
then less number of bits are allocated to the operands and
addressing. The task of allocating bits in the instruction can be
simplified by considering the following factors:
1. Number of addressing modes
2. Number of operands
3. Number of CPU registers

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4. of register sets
Number of address lines
Figure 5 shows the general IA-32 (Intel Architecture- 32 bits)
instruction format. IA-32 is the instruction format that is used in
Intel’s most successful microprocessors. This instruction format
consists of four fields, namely opcode field, addressing mode
field, displacement field, and immediate field.

Figure 5: IA-32 Instruction

Format
Opcode Addressing Displacement Immediate
mode

1 or 2 1 or 2 1 or 4 1 or
4 bytes bytes bytes
bytes

As shown in figure 7.5, the opcode field has 1 or 2 bytes. The addressing
mode field also includes 1 or 2 bytes. In the addressing mode field, an
instruction needs only one byte if it uses only one register to generate the
effective address of an operand. The field that immediately follows the
addressing mode field is the displacement field. If an effective address for a
memory operand is calculated using the displacement value, then it uses either
one or four bytes to encode. If an operand is an immediate value, then it is
placed in the immediate field and it occupies either one or four bytes.
Instructions in a computer can be of different lengths with varying number of
addresses. The number of address fields in the instruction format of a
computer varies according to the organization of its registers. Based on the
number of address fields the instruction can be classified as three address
instructions, two address instructions, one address instruction, and zero address
instruction.

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Three Address Instructions Two

Address
The general format of a three address instruction is represented as: Instruct
operation source 1, source 2, ions
destination ADD A, B, C The
general
where A, B and C are the three variables that are assigned to a distinct format
location in the memory. ‘ADD’ is the operation that is performed on the of a two
operands. ‘A’ and ‘B’ are the source operands and ‘C’ is the destination address
operand. instructi
Here, bits are required to specify the three operands. n bit is required to specify on is
one operand (one memory address). Similarly, 3n bits are required to specify represen
three operands (three memory addresses). Bits are also required to specify the ted as:
ADD operation. operati
o
n

s
o
u
r
c
e
,

d
e
s
t

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ination ADD A,
Notes
B
where A and B are the two variables that are assigned to a distinct location
in the memory. ‘ADD’ is the operation that is performed on the operands. This
instruction adds the content of the variables A and B and stores the result in
variable B. Here, ‘A’ is the source operand and ‘B’ is considered as both source
and destination operands.
Here, bits are required to specify the two operands. n bit is required to specify one
operand (one memory address). Similarly, 2n bits are required to specify two
operands (two memory addresses). Bits are also required to specify the ADD
operation.
One Address Instruction
The general format of one address instruction is represented as:
operation source
ADD A
where A is the variable that is assigned to a distinct location in the memory.
‘ADD’ is the operation that is performed on the operand A. This instruction
adds the content of the variable A into the accumulator and stores the result in
the accumulator by replacing the content of the accumulator.
Some more examples of one address instructions are:
LOAD A: The content of memory location A is stored in the
accumulator. STORE B: The content of accumulator is stored
in the memory location B.
The operand in the instruction can either be the source or the destination,
depending on the instruction.

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Notes
Zero Address Instructions
The locations of the operands in zero address instructions are defined implicitly.
These instructions store operands in a structure called pushdown stack.
We now know that one address instruction uses less number of bits, whereas three
address instructions are uses more number of bits. Similarly, the three address
instructions require more memory access when compared to one address
instructions. Thus, three address instructions take more time to execute
instructions when compared to one address instructions.
To reduce the execution time of the instructions, it is advised to refer the
operands from the processor registers instead of referring the operands from
the memory.

1. Write an assembly language program to subtract two numbers.

Lab Exercise 2. Write an assembly language program to find the average of two
numbers.
7.3 Summary
• A Central Processing unit (CPU) is the main unit of a computer system.
• There are three main components of CPU, namely register set, ALU, and
control unit.
• Registers are the temporary storage, which are constructed from flip-
flops. They store the status of the CPU.
• Stack is considered as a memory unit with an address register. It has a stack
pointer, which always points at the top item in the stack.
• If stack is organized as a collection of registers, then stack is considered
as register stack. If implemented in a random access memory attached to
the CPU, then stack is considered as memory stack.
• Instruction format is the layout of bits in an instruction. An instruction
includes fields such as opcode, operands, and addressing mode.
7.4 Keywords
Bus: An electrical conductor that connects all internal computer components to
the CPU and the main memory.
Displacement Value: A value added to the contents of the address register and the
resulting value is used as the address of the operand.
Immediate Field: A field that includes the address offset field for branches,
load/store instructions, and jump target fields.
Multiplexer: A device that can combine several input signals into one output.

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7.5 Self Assessment 1. “Ce

ntra
1. State whether the following statements are true or false: l
(a) The control unit fetches the instructions from the registers, decodes Pro
and then executes it. cess
ing
(b) The registers store the status of the CPU as well as information
Uni
about the currently executing program.
t
(c) Memory stack is implemented in a random access memory attached to (CP
the CPU. U)
2. Fill in the blanks: is
the
(a) Pending interrupts are checked during . mos
(b) The CPU bus system is operated by the . t
imp
(c) Stack can be implemented in the CPU by allotting a portion of the orta
computer memory to a stack operation and using a as a stack nt
pointer. unit
(d) As instruction consists of a combination of and operands that deal in a
with these operation codes. co
mp
3. Select a suitable choice for every question:
uter
(a) The CPU reads and writes data to and from and transfers data syst
to and from I/O devices. em.
”
(i) Memory system
Just
(ii) Register ify.
(iii) Control unit 2. “A
(iv) Arithmetic and logic unit regi
ster
(b) Constant registers is used to store . is a
(i) Floating point numbers spe
cial
(ii) Read-only values hig
(iii) Addresses h
spe
(iv) Programs
ed
(c) The push and pop operations are simulated by incrementing or stor
decrementing the age
register. area
(i) Accumulator in
the
(ii) Address CP
(iii) Stack pointer U.”
Just
(iv) Index ify
7.6 Review Questions wit
h
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 Unit 7: Central Processing Unit

diagram.
Notes
3. “Stack can be implemented in the CPU by allotting a portion of the
computer memory to a stack operation and using a processor register as a
stack pointer.” Explain.
4. “Instruction format basically provides the layout of bits in an instruction”.
Discuss.
5. “The bits of the status register are modified according to the operations
performed in the ALU.” Discuss.

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Notes Answers: Self Assessment

1. (a) False (b) True (c) True

2. (a) Execution (b) Control unit (c) Processor (d) Operation
cycle (b) Read-only register codes
3. (a) Memory values (c) Stack pointer
system
7.7 Further Readings

Books Morris M. Computer System Architecture. Pearson Education.

A.P.Godse & D.A.Godse (2010). Computer Organization And
Architecture. Pune: Technical Publications.
Stallings. W (2009). Computer Organization and Architecture:
Designing for Performance. Prentice Hall.

Online links

www.mans.edu.eg/faceng/english/computers/PDFS/PDF4
/1.2.pdf www.ehow.com/list_7332165_types-addressing-
modes-computers.html

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Notes
Unit 8: Addressing Modes

Objectives
After studying this unit, you will be able to:
• List the addressing modes
• Explain data transfer and manipulation process
• Discuss program control instructions
• Differentiate between RISC and CISC architecture
Introduction
In almost all CPU designs, addressing modes are a part of the instruction set
architecture. Various addressing modes are defined in a given instruction set
architecture. These addressing modes describe the procedure by which language
instructions in instruction set architecture identify the operands of each
instruction. We can specify how to calculate the effective memory address of an
operand by using addressing modes. This is done by using information held in
registers and/or constants contained within a machine instruction or elsewhere.
RISC and CISC are the two most commonly used instruction sets, which are discussed in this
unit.
8.1 Need for Addressing Modes
The operands of the instructions can be located either in the main memory or
the CPU registers. If the operand is placed in the main memory, then the
instruction provides the location address in the operand field. Many methods
are followed to specify the operand address. The different methods/modes for
specifying the operand address in the instructions are known as addressing
modes. The exact addressing mode used in the instruction can be specified to
the control unit by using any of the following two methods:
1. The opcode explicitly specifies the addressing mode in the instruction.
2. A separate addressing mode field is specified in the instruction.

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Notes Some of the most common addressing modes used by the computers are:
1. Direct Addressing Mode
2. Indirect Addressing Mode
3. Register Addressing Mode
4. Immediate Addressing Mode
5. Index Addressing Mode
Figure 8.1 depicts the addressing mode field.

Figure 8.1: Addressing Mode Field

As seen in figure 8.1, the addressing mode field comprises an opcode, an

addressing mode, an operand field I, and an operand field II. The addressing
mode could be any of the five addressing modes mentioned above.
The addressing modes can be described as follows:
Direct Addressing Mode

Figure 8.2: Direct Addressing

In direct addressing mode, the operand address is explicitly specified in the

instruction. This mode can be illustrated using the below assembly language
statements:
LOAD R1, A //The content of memory location A is loaded into
register R1 MOV B, A //The content of memory location A is moved
to memory location B
JUMP A //The program control is transferred to the instruction at memory
location A
In direct addressing mode, the operand address is directly available in the
instruction. Hence, eliminating the operand address calculation step the
instruction cycle time decreases. However, the operand field in the instruction
limits the number of bits for the operand address.

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Notes Instruction cycle is the process in which the computer retrieves an instruction from its
memory, determines the actions, and performs those actions.

Indirect Addressing Mode

In indirect addressing mode, the address of the location ‘A’ contains address of
another location ‘B’, which actually holds the operand. It is represented as
below:
A = B, B = operand

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Thus, ‘A’ is considered as the pointer. By modifying the content of location

Notes
‘A’, you can change the value of ‘B’, without changing the instruction. The
below assembly language statement illustrates this mode.
MOVE (A), R1 //The content present in the address A is loaded into the
register R1.The figure 8.3 illustrates indirect addressing mode.

Figure 8.3: Indirect Addressing

The indirect addressing mode provides flexibility in programming. You can

change the address during program run-time without altering the contents of
the instruction. However, as there are two memory accesses even for the
single level indirect addressing, the instruction cycle time increases.
Register Addressing Mode
In register addressing mode, the register holds the operand. In the instruction, the
register number that holds the operand is specified. The long programs find
this mode useful as it helps to store the intermediate results in the registers.
The following assembly language statements illustrate this mode:
ADD R1, R2 //The contents of the registers R1 and R2 are added
and the result of the addition is stored in register R1.
STORE R1, M1 //The contents of the register R1 are stored in memory
address M1.
Here, the first operand uses register addressing mode and the second operand
uses direct addressing mode. The figure 8.4 depicts the register addressing
mode

Figure 8. 4: Register Addressing

The register addressing mode provides faster operand fetch without memory
access. However, the number of registers is limited. Hence, the programmers
must effectively utilize the registers.
Immediate Addressing Mode
In immediate addressing mode, the operand is a part of the instruction. Hence,
memory reference is not required to retrieve the operand. This mode is used to
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define constants and set initial values to the variable. The below assembly
language statements illustrate the immediate addressing mode:
MOVE #14, R1 or MVI R1, 14 //The binary equivalent of 14 is loaded in the register R1
ADD #14, R1 //The binary equivalent of 14 and the
contents of R1 are added and the result is stored in register R1
CMP #14, R1 //The binary equivalent if 14 is compared with
the contents of R1.
The ‘#’ sign indicates that the constant following the sign is the immediate operand.

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Notes The figure 8.5 depicts the immediate addressing mode.

Figure 8.5: Immediate Addressing

Once the instruction is fetched, the operand is also fetched in the instruction.
This reduces the instruction cycle time. However, the value of the operand is
limited because this mode is limited to the size of the address field.
Index Addressing Mode
Figure 8.6 depicts index addressing mode.

Figure 8.6: Index Addressing

The index addressing mode includes an index register which holds an

offset/displacement. The effective address of the operand is obtained by
adding the offset with the contents of the registers present in the instruction.
The start address of an array in the memory is obtained from the address field
in the instruction. The difference between the start address and the operand
address provides an index value for the operand. The index value is stored in the
index register. The operands are stored in consecutive locations in the memory.
Thus, by changing the value of the index or by incrementing the index value,
you can access any operand in the array.
Some CPUs possess auto-indexing feature, which automatically increments
the index registers when an instruction with index addressing is executed.
These addressing modes provide flexibility in writing efficient programs.
Addressing modes help in reducing the instruction length by including a
separate field for the address. This helps the programmers to handle complex
tasks such as loop control, program relocations, and indexing of an array.
8.2 Data Transfer and Manipulation
Computer systems consist of a set of instructions that help the users to easily
carry out their computational tasks. The instruction set differs from one
computer system to another. The operations are represented by binary codes
and the binary code assignment in the operation field of the instruction can be
different in different computers. However, the actual operations in the
instruction set are not very different from one computer system to another.
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The symbolic names of the instruction (assembly language notation) may

also differ from one computer to another. An instruction usually contains
opcode, addressing field, and operand field. There are different types of
opcodes and based on the type of opcode, the instructions can be classified as
follows:
1. Data Transfer Instructions
2. Data Manipulation Instructions
3. Program Control Instructions

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Notes
Data transfer instructions transfer data from one location to another without
causing any change in the content present in the binary form. Data
manipulation instructions perform arithmetic, logic, and shift operations.
Program control instructions provide decision making abilities and are able
to change the execution sequence. The program control instructions are
explained in the next section.
Data Transfer Instructions
Data transfer instructions move the data between memory and processor registers,
processor registers and I/O devices, and from one processor register to
another. There are eight commonly used data transfer instructions. Each
instruction is represented by a mnemonic symbol. Table 8.1 shows the eight data
transfer instructions and their
Tablerespective mnemonic
8.1: Data Transfer Instructions symbols.

Nam e Mnem onic

Symbols
Load LD
Store ST
Move MOV
Exchange XCH
Input In
Output OUT
Push PUSH
Pop POP

The instructions can be described as follows:

1. Load: The load instruction is used to transfer data from the memory to a
processor register, which is usually an accumulator.
2. Store: The store instruction transfers data from processor registers to memory.
3. Move: The move instruction transfers data from processor register to
memory or memory to processor register or between processor registers
itself.
4. Exchange: The exchange instruction swaps information either between two
registers or between a register and a memory word.
5. Input: The input instruction transfers data between processor register and input terminal.
6. Output: The output instruction transfers data between processor register and output terminal.
7. Push and Pop: The push and pop instructions transfer data between a
processor register and memory stack.
All these instructions are associated with a variety of addressing modes. Some
assembly language instructions use different mnemonic symbols just to
differentiate between the different addressing modes.

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Example: The mnemonic symbols for load immediate is LDI

Thus, it is necessary to be familiar with various addressing modes and
different types of instructions to write efficient assembly language programs
for a computer.

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Notes
Data Manipulation Instructions
Data manipulation instructions have computational capabilities. They perform
arithmetic, logic, and shift operations on data. There are three basic types of
data manipulation instructions:
1. Arithmetic Instructions
2. Logical and Bit Manipulation Instructions
3. Shift Instructions
During execution of the instruction, each instruction goes through the fetch
phase, where it reads the binary code of the instruction from the memory.
According to the rules of the instruction addressing mode, the operands are
brought in processor registers. Finally, the instruction in the processor is
executed.
Arithmetic Instructions
Arithmetic operations include addition, subtraction, multiplication and
division. Some computers provide instructions only for addition and
subtraction operations, and generate multiplication and division operations
from these two operations. Each instruction is represented by a mnemonic
symbol. Table 8.2 illustrates some of the arithmetic instructions and their
Table 8.2: Arithmetic Instructions
respective mnemonic symbols.

Name Mnem
onic
Increment INC
Decrement DEC
Add ADD
Subtract SUB
Multiply MUL
Divide DIV
Add with ADDC
Carr y
Subtract SUBB
with
Borrow
Negation NEG

The description of these instructions is as follows:

1. Increment: The increment instruction adds 1 to the value stored in register or
memory word.
2. Decrement: The decrement instruction subtracts 1 from the contents stored in
register or memory word.
3. Arithmetic Instructions: The arithmetic instructions are available for
different types of data such as floating point, binary, single precision, or
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double precision data.

During execution of arithmetic instructions, the processor status flags or
conditional codes are set to designate the outcome of the operation.

Example: For the conditions generated as a carry or borrow, the outcome

is either 0 or negative.

A flip-flop is used to store the carry from an addition operation. The add with
carry instruction performs the addition of two numbers along with the value of
carry from the previous computation. Similarly, the subtract with borrow
instruction performs the subtraction of two numbers and a borrow if any, from
the previous computation. The negation instruction represents the 2’s
complement of a number.

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Logical and Bit Manipulation Instructions

Notes
Logical instructions carry out binary operations on the bits stored in the registers.
In logical operations, each bit of the operand is treated as a Boolean variable.
Logical instructions can change bit value, clear a group of bits, or can even insert
new bit value into operands that are stored in registers or memory words. Each
logical instruction is represented by mnemonic symbols.

Notes Boolean variable is a numerical variable that can hold a single binary bit (0 or 1).

Table 8.3 illustrates some of the logical instructions andtheir respective mnemonic symbols.

Table 8.3: Logical Instructions

Name Mnemoni
c
Clear CLR
Complement COM
AND AND
OR OR
Exclusive- XOR
OR
Clear carry CLRC
Set carry SETC
Complement COMC
carry
Enable EI
interrupt
Disable DI
interrupt

The clear instruction replaces the specific operand by 0’s. The complement
instruction inverts all the bits of the operand and produces 1’s complement.
The AND, OR, and XOR instructions perform logical operations on each bit
or group of bits of the operand.
Logical instructions can also manipulate individual bits or group of bits. The bit
manipulation operation can clear a bit to 0, can set a bit to 1, or can
complement a bit.
The AND instruction can clear a bit or group of bits of an operand. For Boolean
variable a, the relationship ‘ab0 = 0’ and ‘ab1 = a’ indicates that the binary
variable when ANDed with 0 changes the value to 0. However, the variable
when ANDed with 1 does not change the value. Thus, bits of an operand can
be cleared by ANDing the operand with another operand that has to clear all 0
bits in its position. It is also known as mask because it masks 0s in selected
bit positions of an operand.
The OR instruction can set a bit or group of bits of an operand. For Boolean
variable a, the relationship ‘a + 1 =1’ and ‘a + 0 = a’ indicates that the binary
variable when ORed with 1, changes the value to 1. However, the variable when

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ORed with 0 does not change the value. Thus, OR instruction is used to set the
bits to 1 by ORing the bits of an operand with another operand that has 1s in
its bit positions.
The XOR instruction can complement bits of an operand. For Boolean
variable a, the relationship ‘a + 1 = a’ and ‘a + 0 = a’ indicates that the binary
variable is complemented when XORed with 1. However, the variable does
not change value when XORed with 0.
The carry bits can be cleared, set, or complemented with appropriate instructions.
The bit manipulation instructions can also enable or disable the interrupt
facility, which is controlled by the flip-flops.
Shift Instructions
Shift instruction helps to shift the bits of an operand to the right or to the
left. The direction of shift is based on specific instructions. The operand is
first loaded into the accumulator and then the shift operation is performed bit
by bit.

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Notes The shift-left operation shifts the zero into low-order vacated position.

Example: Operand in Accumulator

1111 0101 1000 1011

After a shift-left operation
1 1110 1011 0001 0110 zero is shifted in

High order bit is shifted out

In shift-right operations, zeros are shifted into high-order vacated position. The
bits that are shifted can also be the original value of the sign bit as in case of
arithmetic right shift or can be the bits that are shifted out of low-order position
of the accumulator-extension as in case of Rotate Right Accumulator and
Extension (RRAE). The main purpose of this RRAE is to fetch the bits from the
accumulator-extension position 15 and shift the bits back to the accumulator
position 0. This ensures that no bits are lost during the shift.
The shift operation can be ended either by decrementing the shift count to zero
or by shifting the bit value of 1 into the high-order position (bit 0) of the
accumulator.

Example: Consider the below example program to add

two numbers: NAME Addition //name of
the program PAGE 52,80
TITLE 8086 assembly language program to add two
numbers //Title of the program
.model small //implies that the program is a small
program
.stack 100 //memory allocation is 100
.data // data for the
program Number1 DB 63H
Number2 DB
2EH Result DW
?
.code //marks the beginning of
the code START: MOV AX, @data
MOV DS, AX
MOV AL,

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Number1 ADD
AL,
Number2 MOV
AH, 00H
ADC AH, 00H
MOV Result,
AX END
START

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In the above program,

Notes
1. .model specifies the mode for assembling the program.
2. DB allocates and initializes the bytes of storage.
3. Number1 DB 63H indicates the first number storage and
Number2 DB 2EH indicates the second number storage.
4. DW allocates and initializes the words of storage.
5. Result DW indicates that double byte is reserved for the
result.
6. The instructions MOV AX, @data and MOV DS, AX
initialize the data segment.
7. MOV AL, Number1 transfers the first number to AL.
8. ADD AL, Number2 adds the second number to AL.
9. MOV AH, 00H makes Most Significant Bit of result zero.
10. ADC AH, 00H puts carry in AH.
11. MOV Result, AX copies result to the memory.

8.3 Program Control

Instructions of the computer are always stored in consecutive memory locations.
These instructions are fetched from successive memory locations for
processing and executing. When an instruction is fetched from the memory,
the program counter is incremented by 1 so that it points to the address of
the next consecutive instruction in the memory. Once a data transfer and data
manipulation instruction is executed, the program control along with the program
counter, which holds the address of the next instruction to be fetched, is
returned to the fetch cycle.
Data transfer and manipulation instructions specify the conditions for data
processing operations, whereas the program control instructions specify the
conditions that can alter the content of the program counter. The change in the
content of program counter can cause an interrupt/break in the instruction
execution. However, the program control instructions control the flow of program
execution and are capable of branching to different program segments.
Some of the program control instructions are listed in table 8.4.

Table 8.4: Progr am Control Instructions

Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Call CALL
Return RET
Compare (by CMP
subtraction)
Test (by TST
ANDing)
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The branch is a one-address instruction. It is represented as BR ADR, where

ADR is a mnemonic for an address. The branch instruction transfers the value of
ADR into the program counter. The branch and jump instructions are
interchangeably used to mean the same. However, sometimes they denote
different addressing modes.

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Notes Branch and jump instructions can be conditional or unconditional. The

unconditional branch instruction creates a branch to the specified address
without any conditions.

Example: JMP Displaydiagram

The JMP instruction transfers the flow of execution,
without considering the actual condition of the flags, to the
indicated operator. The above instruction makes the control
jump to the part of the code where Displaydiagram is
specified.
The conditional branch instructions such as ‘branch if positive’, or ‘branch if
zero’ specify the condition to transfer the flow of execution. When the
condition is met, the branch address is loaded in the program counter.
Figure 8.7 depicts the conditional branch instructions.

Figure 8.7: Conditional

Branch

The compare instruction performs an arithmetic subtraction. Here, the result

of the operation is not saved; instead, the status bit conditions are set. The test
instruction performs the logical AND operation on two operands and updates
the status bits.

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Status Bit Conditions

Notes
The status register comprises the status bits. The bits of the status register are
modified according to the operations performed in the ALU. Figure 8.8
depicts a block diagram of an 8-bit ALU with a 4-bit status register.

Figure 8.8: Status Register Bits

In figure 8.8, if the end carry C8 is 1, then carry (C) is set to 1. If C8 is 0,

then C is cleared to 0. If the highest order bit F7 is 1, then Sign (S) is set
to 1. If F7 is 0, then S is set to 0.
If the output of ALU is 0, then zero (Z) is set to 1, otherwise Z is set to 0.
If XOR of the last two carries is equal to 1, then overflow (V) is set to 1,
otherwise V is cleared to 0.
The result of the 8-bit ALU operation is either 127 or -127.
Z is a status bit used to indicate the result obtained after comparing A and B.
Here, XOR operation is used to compare two numbers (Z = 0 if A = B).

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Notes Conditional Branch Instruction

The conditional branch instruction checks the conditions for branching using
the status bits. Some of the commonly used conditional branch instructions
are shown in table 8.5.

Mnemoni Condition Tested

c Condition
BZ Br anch if zer o Z=1
BNZ Br 8.5:
Table anch if notl zero
Conditiona InstructionsZ = 0
BC Br anch if carry C=1
BNC Br anch if no carr y C = 0
BP Br anch if plus S=0
BM Br anch if minus S=1
BV Br anch if overflow V = 1
BNV Br anch if no V=0
overflow
Unsigne d compar e conditions (A – B)
BHI Br anch if higher A>B
BHE Br anch if higher or A B
equal
BLO Br anch if lower A<B
BLOE Br anch if lower or A B
equal
BE Br anch if equal A=B
BEN Br anch if not equal A B
Signed compare cond itions (A – B)
BGT Br anch if greater A>B
than
BGE Br anch if greater or A B
equal
BLT Br anch if less than A < B
BLE Br anch if less or A B
equal
BE Br anch if equal A=B
BEN Br anch if not equal A B

Thus, when the status condition is true, the program control is transferred to
the address specified in the instruction, otherwise the control continues with the
instructions that are in the subsequent locations. The conditional instructions are
also associated with the program control instructions such as jump, call, or
return.
The zero status bit checks if the result of the ALU is zero or not. The carry bit
checks if the most significant bit position of the ALU has a carry out. It is also
used with rotate instruction to check whether or not the bit is shifted from the
end position of a register into a carry position. The sign bit indicates the state
of the most significant bit of the output from the ALU (S = 0 denotes positive
sign and S = 1 denotes negative sign). The branch if plus and branch if minus are
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used to check whether the value of the most significant bit represents a sign or
not. The overflow and underflow instructions are used in conjunction with
arithmetic operations performed on signed numbers. The higher and lower
words are used to denote the relations between unsigned numbers, whereas the
greater and lesser words are used to denote the relations between signed
numbers.

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Notes
Example: Consider two numbers M = 11110000 and N = 00010100.
When we perform M - N operation, the result obtained
is
M: 11110000
N: 00010100
M-N: 11011100
The compare instruction updates the
status bits: C =1: Carry out of the last
stage
S = 1: Left most bit is 1
Z = 0: Last two carries are
equal to 1 V = 0: Result is
not equal to 0
Consider the numeric value, where M = 60 and B =10
(unsigned numbers). Here, M > N and M N. Therefore,
the instructions that will cause branch are BHI, BHE and
BNE.
If M = -8 and N = 10, then we have M < N and M N.
Therefore, the instructions that will cause branch are BLT,
BLE, and BNE

8.4 RISC and CISC

The design of the instruction set for the processor is considered as an important
aspect of computer architecture. The machine language program is developed
based on the instruction set chosen for that particular computer.
Earlier, the hardware components of the computer were expensive and to
minimize this expense, the programmers started to build simple and small
instructions. With the advent of integrated circuits, the digital hardware became
cheaper and the computer instructions started to increase in number and
complexity. Many computers have more than 100 instruction sets. Such
computers with large number of instructions are classified as a Complex
Instruction Set Computers (CISC).
In 1980s, computer architects started to design computers with fewer instructions
in order to execute programs at a much faster rate within the CPU. Such
computers with less number of instructions are classified as a Reduced
Instruction Set Computer (RISC).
Complex Instruction Set Computer (CISC)
A Complex Instruction Set Computer (CISC) comprises a complex instruction
set. It incorporates variable length instruction format. Instructions that require
register operands may take only two bytes. However, the instructions that
require two memory addresses may take five bytes to include the complete

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instruction code. Thus, CISC has variable length encoding of instructions and
the execution of instructions may take varying number of clock cycles. The
CISC processor provides direct manipulation of operands that are in memory.

Example: An ADD instruction will use index addressing to specify one

operand in memory and direct addressing to specify second operand in
memory. This instruction would use another memory location to store the
result. Thus, this instruction would use three memory references for
execution.
Many CISC architectures read the inputs and write their outputs in the
memory system instead of a register file. As CISC architecture takes large
number of addressing modes, more hardware logic is required to implement
them. This reduces the computation speed.
Basically, the CISC architecture attempts to provide a single machine instruction
for the statements that are written in a high-level language.

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Notes
Example: The IBM 370 computer uses the CISC architecture.

Reduced Instruction Set Computer (RISC)

In Reduced Instruction Set Computer (RISC) architecture, the instruction set
of the computer is simplified to reduce the execution time. RISC has a small
set of instructions, which generally include register-to-register operations.
Thus, data is stored in processor registers for computations and results of the
computations are transferred to the memory using store instructions. All
operations are performed within the registers of the CPU. In RISC, all
instructions have simple register addressing and hence use less number of
addressing modes.
RISC uses relatively a simple instruction format and is easy to decode. Here,
the instruction length can be fixed and aligned on word boundaries. The RISC
processors have the ability to execute one instruction per clock cycle. This is
done using pipelining, which involves overlapping the fetch, decode, and
execute phases of two or three instructions.
As RISC takes relatively a large number of registers in the processor unit, it
takes less time to execute its program when compared to CISC.

Example: The Scalable Processor Architecture (SPARC) is an example of

RISC architecture.

8.4.1 RISC Instruction Set

RISC instruction set includes simpler instructions with hard-wired control,
large number of registers, simpler processor pipeline and increased clock-rate.
The RISC processor’s instruction set is restricted to load and store instructions
when there is an interaction between memory and CPU. All other instructions
are executed within registers without any reference to memory.

Example: Consider an example program for a RISC-type CPU, which

include load and store instructions that have one memory and one register
address, and arithmetic instructions that are specified by processor registers. The
below program evaluates X = (P + Q)*(R + S)
LO R1 P R M[P]
AD R2 Q 1 M[Q]
LO R3 R R M[R]
R4 S M[S]
AD 2
LO R
AD 3
LOA R4
D

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AD R1, R1, R2 R1 R1 +
D R2
AD R3, R3, R4 R3 R3 +
D R4
MU R1, R1, R3 R1 R1 +
L R3
STO X, R1 M[ R1
RE X]
The LOAD instructions transfer the operand P, Q, R and S
from memory to CPU registers R1, R2, R3, and R4
respectively. The ADD and MUL instructions execute the
addition and multiplication operations with the data in the
registers without referring to the memory. The STORE
instruction stores the result of the computation in the memory
(M[X]).

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8.4.2 RISC Versus CISC

Notes
There are some significant differences between RISC and CISC processors. The
comparison between the common characteristics of RISC and CISC processor
is shown in table 8.6:

Table 8. 6: Comparison Between RISC and CISC

RISC CISC
Few instructions Many instructions
Few addressing modes. Many addressing modes
Most instructions have
register to
register addressing modes
Includes simple instructions Includes complex instructions
and and
takes one cycle takes multiple cycles
Some of the instructions Most of the instructions refer to
refer to memory
memory
Hardwar e executes the Microprogram executes the
instructions instructions
Fixed format instructions Var iable format instructions
Easier to decode as Difficult to decode as
instructions instructions
have fixed for mat have variable format
Multiple register sets are Single register set is used
used
RISC is highly pipelined CISC is not pipelined or less
pipelined
Load and store functions Load and store functions are
are found
separate instructions in a single instruction

Today, RISC and CISC architectures are becoming more alike. Many RISC chips
now support instructions of CISC chips also. Similarly, CISC chips are using
many techniques associated with RISC chips.
8.5 Summary
• Addressing modes provide different methods for specifying operand address in the instruction.
• Some of the commonly used addressing modes are direct addressing mode,
indirect addressing mode, register addressing mode, immediate addressing
mode, and index addressing mode.
• Data transfer instructions help to move the data from one location to another.
Data manipulation instructions perform arithmetic, logic, and shift
operations on data.
• Program control instructions specify the conditions for data processing operations.
• The Complex Instruction Set Computer (CISC) consists of many complex instruction sets.
• The Reduced Instruction Set Computer (RISC) consists of less instruction
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sets and executes the instructions at a greater speed.

8.6 Keywords
Accumulator: A processor register that stores intermediate arithmetic and logic results.
Flip-flops: An electronic circuit that is interconnected to form logic gates. It
changes its state when it receives the input pulse (trigger). Hence, it is also
known as bistable gate.
Microprogram: A computer program that has basic elemental commands
which control the operation of each components of a microprocessor.
Pipelining: In pipelining, while the processor is performing arithmetic operations,
the computer architecture allows the next instructions to be fetched, holding
them in a buffer close to the processor until each instruction operation can be
performed.

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Notes
8.7 Self Assessment
1. State whether the following statements are true or false:
(a) The number of address fields in the instruction format of a computer
varies according to the organization of the stack.
(b) In direct addressing mode, the register holds the operand.
(c) The store instruction transfers data from processor register to memory.
(d) Data transfer and manipulation instructions specify the conditions
that can alter the content of the program counter.
(e) Complex Instruction Set Computer (CISC) incorporates variable
length instruction format.
2. Fill in the blanks:
(a) The different methods/modes for specifying the operand address in
the instructions are known as .
(b) The push and pop instructions transfer data between a processor
register and
.
(c) In conditional branch instruction, when the condition is met, the
branch address is loaded in the .
(d) RISC has small set of instructions, which generally include operations.
3. Select a suitable choice for every question:
(a) In register addressing mode, the register holds the
(i) Operand
(ii) Opcode
(iii) Address
(iv) Register number
(b) A flip-flop is used to store the carry from operation.
(i) Addition
(ii) Subtraction
(iii) Comparison
(iv) Division
(c) The test instruction performs the logical operation on
two operands and updates the status bits.
(i) SUB
(ii) OR
(iii) XOR
(iv) AND
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pro
(d) The conditional branch instruction checks the conditions for ces
branching using the sor.
. ”
Pro
(i) Clock cycles vid
(ii) Registers e
the
(iii) Instruction codes
diff
(iv) Status bits ere
nce
Answers: Self Assessment
s.
1. (a) False
(b) False
(c) True
(d) False
(e) True
2. (a) Addressing modes
(b) Memory stack
(c) Program counter
(d) Register-to-register
3. (a) Operand
(b) Addition
(c) AND
(d) Status bits
8.8 Review Questions
1. “In direct addressing mode, the operand address is explicitly specified
in the instruction.” Explain with examples.
2. “Data manipulation instructions have computational capabilities.”
Comment.
3. “Data transfer and manipulation instructions specify the conditions for
data processing operations.” How?
4. “The conditional branch instruction checks the conditions for branching
using the status bits.” How?
5. “Complex Instruction Set Computer (CISC) comprises complex
instruction set.” Justify
6. “RISC instruction set includes simpler instructions.” Explain with an
example.
7. “There are some significant differences between RISC and CISC

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Notes

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Notes 8.9 Further Readings

Books Morris M. Computer System Architecture. Pearson Education.

A.P.Godse & D.A.Godse (2010). Computer Organization
And Architecture. Pune: Technical Publications.
Stallings. W (2009). Computer Organization and
Architecture: Designing for Performance. Prentice Hall.

Online links

www.mans.edu.eg/faceng/english/computers/PD
FS/PDF4/1.2.pdf
www.ehow.com/list_7332165_types-addressing-
modes-computers.html

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