Digital
Digital
ENGINEERING PROGRAM
In the modern world of electronics, the term Digital is generally associated with a computer
because the term Digital is derived from the way computers perform operation, by counting
digits. For many years, the application of digital electronics was only in the computer system.
But now-a-days, digital electronics is used in many other applications. Following are some of
the examples in which Digital electronics is heavily used.
Signal
Signal can be defined as a physical quantity, which contains some information. It is a
function of one or more than one independent variables. Signals are of two types.
• Analog Signal
• Digital Signal
Analog Signal
An analog signal is defined as the signal having continuous values. Analog signal can have
infinite number of different values. In real world scenario, most of the things observed in
nature are analog. Examples of the analog signals are following.
• Temperature
• Pressure
• Distance
• Sound
• Voltage
• Current
• Power
The circuits that process the analog signals are called as analog circuits or system. Examples
of the analog system are following.
• Filter
• Amplifiers
• Television receiver
• Motor speed controller
• Less accuracy
• Less versatility
• More noise effect
• More distortion
• More effect of weather
Digital Signal
A digital signal is defined as the signal which has only a finite number of distinct values.
Digital signals are not continuous signals. In the digital electronic calculator, the input is
given with the help of switches. This input is converted into electrical signal which have two
discrete values or levels. One of these may be called low level and another is called high
level. The signal will always be one of the two levels. This type of signal is called digital
signal. Examples of the digital signal are following.
• Binary Signal
• Octal Signal
• Hexadecimal Signal
The circuits that process the digital signals are called digital systems or digital circuits.
Examples of the digital systems are following.
• Registers
• Flip-flop
• Counters
• Microprocessors
• More accuracy
• More versatility
• Less distortion
• Easy communicate
• Possible storage of information
A digital system can understand positional number system only where there are a few
symbols called digits and these symbols represent different values depending on the position
they occupy in the number.
• The digit
• The position of the digit in the number
• The base of the number system (where base is defined as the total number of digits
available in the number system).
Each position represents a specific power of the base (10). For example, the decimal number
1234 consists of the digit 4 in the units position, 3 in the tens position, 2 in the hundreds
position, and 1 in the thousands position, and its value can be written as
Example
Example
Example −
2. Write all the remainder from bottom to top gives the binary equivalent number of
that given decimal number before decimal point.
3. For the conversion of fractional part of decimal number multiply it by 2 and write
the carry or if there is any digit goes beyond fractional point take out the carry and
multiply it until it reaches Zero or until sufficient accuracy is obtained.
4. Write all the carries generated from number of multiplication procedure from top to
bottom to get the binary equivalent of decimal fractional part.
2. Count the number of binary digit after the radix or binary point and put the weight of
each digit as-1,-2,-3....., from left hand side to right hand side. Let M is the number of
bits, last bit or digit has weight equal to 2-M.
3. Write the binary bit stream in generalized equation.
4. Finally add all the products, which give the number equivalent to the decimal
number system.
Example;
OR (10110.110)2 = (?)10
1 0 1 1 0 . 1 1 0
16 +0 +4 +2 +0 . 0.5 + 0.25 +0
22 . 75
2. Write the corresponding Hexadecimal number for each group gives the Hexadecimal
representation of binary digits.
3. Group the given digit or bit from LHS to RHS after of radix point 4 bits at a time.
If the last group is not equal to 4 bits postfix the required number of 0’s and the
value will not change.
4. Write the corresponding Hexadecimal equivalent number for each group gives the
Hexadecimal representation of binary digits.
For the Hexadecimal number representation in binary number use only four binary bits.
Example:
Hexadecimal 1 A B C . 2 F
Decimal 1 10 11 12 . 2 15
Binary 0001 1010 1011 1100 . 0010 1111
1101010111100 . 00101111
Hence result is
2. Write all the remainder from bottom to top gives the binary equivalent number of that
given decimal number before decimal point
3. For the conversion of fractional part of decimal number multiply it by ‘16’ and write
the carry or if there is any digit goes beyond fractional point take out the carry and
multiply
4. it until it reaches Zero or until sufficient accuracy is obtained.
5. Write all the carries generated from number of multiplication procedure from top to
bottom to get the Hexadecimal equivalent of decimal fractional part.
4. Finally add all the products terms, which gives the number equivalent to the decimal
number system.
Example;
A B C . C D
(ABC.CD) 16 = (2748.80)10
2. Write the corresponding octal number for each group gives the octal representation
of binary digits.
3. Group the given digit or bit from LHS to RHS after of radix point ‘3’ bits at a time.
If the last group is not equal to ‘3’ bits postfix the required number of 0’s and the
value will not change.
4. Write the corresponding octal equivalent number for each group gives the octal
representation of binary digits.
1 0 0 0 1 1 1
2 0 0 1 0 2 2
3 0 0 1 1` 3 3
4 0 1 0 0 4 4
5 0 1 0 1 5 5
6 0 1 1 0 6 6
7 0 1 1 1 7 7
8 1 0 0 0 10 8
9 1 0 0 1 11 9
10 1 0 1 0 12 A
11 1 0 1 1 13 B
12 1 1 0 0 14 C
13 1 1 0 1 15 D
14 1 1 1 0 16 E
15 1 1 1 1 17 F
• If we come across with a large binary number, that has to be converted to decimal,
we first convert number into Hexadecimal, then convert Hexadecimal to Decimal.
2’s complement of a given number can be found by adding ‘1’ to the least significant bit
of the 1’s complement of the given number.
• If carry is generated (End Around Carry) as a result of this addition processes (then
this addition process may not able to give the correct required result).
• To get the actual result carry generated must be added to the LSB of the remaining
result part.
Case-2:
• If carry not generated as a result of this addition processes (then this addition process
may not able to give the correct required result).
• To get the actual result we should take the complement vale of the result obtained with
Negative sign.
• Discard the carry and read the value if the remaining part of the result as the true
value of the result with positive sign.
Case-2:
Boolean Algebra
Boolean algebra is a system of mathematical logic developed by George Boole. The Laws
of Boolean algebra are used to simplify and evaluate logic expression. Operations like
addition (+), Subtraction (-), Multiplication (×) and Division (÷) are used to evaluate
arithmetic expression. Logical expressions have their own operations: i.e. AND (.), OR
Logic Gates
A logic gate is an Electronic circuit which makes Logical decisions The most commonly
used logic gates are NOT, OR, AND,NOR and NAND gates In addition to these EX-OR and
EX-NOR gates are other types. Which can be constructed using Basic gates NOT, OR and
AND.
Digital systems are said to be constructed by using logic gates. These gates are the AND, OR,
NOT, NAND, NOR, EXOR and EXNOR gates. The basic operations are described below
with the aid of truth tables.
AND gate
The AND gate is an electronic circuit that gives a high output (1) only if all its
inputs are high. A dot (.) is used to show the AND operation i.e. A.B. Bear in
mind that this dot is sometimes omitted i.e. AB
OR gate
The OR gate is an electronic circuit that gives a high output (1) if one or
more of its inputs are high. A plus (+) is used to show the OR operation.
NOT gate
The NOT gate is an electronic circuit that produces an inverted version of the input at
its output. It is also known as an inverter. If the input variable is A, the inverted
output is known as NOT A. This is also shown as A', or A with a bar over the top, as
shown at the outputs. The diagrams below show two ways that the NAND logic gate
can be configured to produce a NOT gate. It can also be done using NOR logic gates
in the same way.
NAND gate
NOR gate
EXOR gate
The 'Exclusive-OR' gate is a circuit which will give a high output if either,
but not both, of its two inputs are high. An encircled plus sign ( ) is used to
show the EOR operation.
EXNOR gate
The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a low output
if either, but not both, of its two inputs are high. The symbol is an EXOR gate with a small
circle on the output. The small circle represents inversion.
The NAND and NOR gates are called universal functions since with either one the AND and
OR functions and NOT can be generated.
Note:
A function in sum of products form can be implemented using NAND gates by replacing all
AND and OR gates by NAND gates.
A function in product of sums form can be implemented using NOR gates by replacing all
AND and OR gates by NOR gates.
Table 2 is a summary truth table of the input/output combinations for the NOT gate together
with all possible input/output combinations for the other gate functions. Also note that a truth
table with 'n' inputs has 2n rows. You can compare the outputs of different gates.
Combinational circuits
Logic gates are the fundamental building blocks of the combination logic circuit. When
logic gates are connected together to produce a specified output for certain specified
combinations of input variable, with no storage involved, the resulting network is called
“Combinational logic”.
In combinational circuit, the outputs at any instant of time depend upon the input present
at that instant of time.
“Half Adder”. The Half Adder accepts two binary digits at its input and produces two binary
digits at its output i.e., a “SUM” bit and a “CARRY” bit.
Full Adder:
Full Adder is a combination logic circuit which performs the addition of three binary bits. It
consists of three inputs and two outputs
An n-bit adder is a circuit which adds two n-bit numbers say A&B. In addition an n-bit
adder will have another single bit input which is added to the two numbers called the carry-
in (Cin). The output of the n-bit adder is an n-bit SUM (S) and a CARRY- OUT (Cout) bit.
The carry out bit of one stage of full adder is used as carry-in i.e. Input to the next stage.
In general, an n-bit binary parallel adder can be built out of ‘n’ full adder blocks (or with
‘n-1’ full adder block and one half adder block).
i)Parallel Binary Adder circuit using Half Adder and Full Adder Blocks.
Outputs
Inputs Combinational Circuit
The clock is required for synchronization. The delay depends on propagation delay of
circuit and clock frequency. The examples are flip-flops, registers, counters etc.
– Inputs are sampled at specific clock intervals & hence the state as well as
outputs change at these clock intervals
2. Asynchronous:
– Are not controlled by any clock pulses
– Output responds immediately to change in inputs
FLIPFLOPS
Latches and flip-flops are the basic elements for storing information. One latch or flip-flop
can store one bit of information. The main differences between latches and flip-flops are: For
latches, their outputs are constantly affected by their inputs as long as the enable signal is
asserted. In other words, when they are enabled, their output changes immediately when their
inputs change. Flip-flops, on the other hand, have their output change only either at the rising
or falling edge of the enable/clock signal. This enable signal is usually the controlling clock
signal. After the rising or falling edge of the clock, the flip-flop content remains constant
even if the input changes. There are basically four main types of latches and flip-flops: SR,
D, JK, and T. The major differences in these flip-flop types are the number of inputs they
have and how they change state. For each type, there are also different variations that
enhance their operations.
The simplest sequential circuit or storage element is a bistable element, which is constructed
with two inverters connected sequentially in a loop as shown in Figure 4.3. It has no inputs
and two outputs labeled Q and Q’. Since the circuit has no inputs, we cannot change the
values of Q and Q’. However, Q will take on whatever value it happens to be when the circuit
is first powered up.
Assume that Q = 0 when we switch on the power. Since Q is also the input to the bottom
inverter, Q’, therefore, is a ‘1’. A ‘1’ going to the input of the top inverter will produce a ‘0’
at the output Q, which is what we started off with. Similarly, if we start the circuit with Q =
1, we will get Q’ = 0, and again we get a stable situation. A bistable element has memory in
the sense that it can remember the content (or state) of the circuit indefinitely. Using the
signal Q as the state variable to describe the state of the circuit, we can say that the circuit has
two stable states: Q = 0, and Q = 1; hence the name “bistable.”
Note: When the output Q is in between State ‘0’ and state ‘1’, it is said to be in meta-stable
state.
Bistable Element
SR Flip-flop - (Set / Reset)
This type of flip-flop has two inputs: Set and Reset. Two outputs: Q and Q' (Q' being the
inverse of Q). The SR flip-flop can also have a clock input for a level driven circuit as
opposed to a pulse driven circuit
An SR latch
State S R Q Q Description
1 0 0 1 Set Q » 1
Set
1 1 0 1 no change
0 1 1 0 Reset Q » 0
Reset
1 1 1 0 no change
The operation of an SR flip-flop is as follows: The Set input will make Q goto 1 i.e. will 'set'
the output. The Reset input will make the output Q goto 0 i.e. reset the output.
The scenario of having both Set and Reset at logic 1 is not allowed as this is not a logical pair
of inputs. Knowing the above, we can layout the operating characteristics and the state
change table:
There are a few different ways SR flip-flops can be made. They can be pulse driven or clock
(and therefore level are used) driven. For the state change diagram above either a pulse or
level input can be implied. When using the state change table to describe pulses, a '1' implies
a pulse should be applied, where '0' implies that no pulse should exist at this state.
For either a pulse driven circuit or a clock driven circuit, the following applies: An 'X' means
a pulse / level may or may not be applied. The reason behind this is because no matter of the
input (0 or 1), the output will always goto the same value. It is because of this fact that this is
considered a 'don't care' input. Hence 's' and 'r' are 'don't care' sets of 'S' and 'R' respectivly ('s'
leads to the same output as 'S' and that is why 's' is a subset of 'S').
The T type flip-flop is a single input device: T (trigger). Two outputs: Q and Q' (where Q' is
the inverse of Q).
The operation of the T type flip-flop is as follows: A '0' input to 'T' will make the next state
the same as the present state (i.e. T = 0 present state = 0 therefore next state = 0). However a
'1' input to 'T' will change the next state to the inverse of the present state (i.e. T = 1 present
state = 0 therefore next state = 1).
Knowing the above, we can now formalise the operating characteristics and the state change
table:
The T type flip-flop is an edge driven device. Therefore you should not associate 1 and 0 with
levels, but instead 1 should be considered as a pulse, and 0 as no pulse.
Notice that if a clock signal was tied to T, the output Q would be a clock signal at
approximatly half the frequency of T. This property makes the T flip-flop a good candidate
for applications such as frequency division.
The D type flip-flop has one data input 'D' and a clock input. The circuit edge triggers on.the
clock input. The flip-flop also has two outputs Q and Q' (where Q' is the reverse of Q).
The operation of the D type flip-flop is as follows: Any input appearing (present state) at the
input D, will be produced at the output Q in time T+1 (next state). e.g. if in the present state
we have D = 0 and Q = 1, the next state will be D = anything and Q = 0.
Knowing the above, we can now generate the state change table and the operating
characteristics.
The operation of the D type delays any input by exactly one clock cycle (given an
instantanious response time i.e. a perfect flip-flop). Cascading several D type flip-flops
together can produce delaying circuits, possible applications could be for matching time
delays in digital television systems.
JK flip-flop
The JK type flip-flop consists of two data inputs: J and K, and one clock input. There are
again two outputs Q and Q' (where Q' is the reverse of Q).
The JK flip-flop operations are quite complicated to understand by text alone. So here we will
simply see the operating characteristics diagram and then discuss it.
A. When J=K=0, the current output will carry through to the next state. e.g. Current state
Q = Next state Q
B. When J=0 and K=1, the next state output will be put to 0. This happens regardless of
the present state output.
C. When J=1 and K=0, the next state output will be asserted (put to 1). This happens
regardless of the present state output.
D. When J=K=1, the next state output will be the inverse of the current state output. e.g.
Current state Q' = Next state Q.
Knowing the above we can now construct the state change table:
Lets discuss this state change table with respect to the operating characteristics diagram.
There actually exists two operating characteristics that satisfy every possible output
combination. This means there should be some 'don't care' terms with each output
combination (as our diagram shows). In the list below we shall see how each of the terms
i. Two conditions exist so that the next state is 0 while the present state is also 0. From
the operating characteristics diagram, we can see that condition A and B would both
satisfy this scenerio. The common term to make this scenerio true is J=0. We dont
care about K, as K=1 or K=0 while J=0 will work. Hence the 'don't care' term is K,
ii. Operating characteristics C and D both satisfy this scenerio. The common term is
again J, as the situation is solved by J=1 and either K=0 or K=1, therefore the 'don't
care' term is K as shown on the state change table.
iii. When the output goes from 1 to 0, there are two characteristics that will allow this to
happen; B and D. K=1 and J can be equal to 1 or 0. Therefore in this case, J is the
'don't care' term.
iv. When the JK flip-flop remains at logic, it means that either A or C of the four
operating characteristics have been applied. K must equal 0 in either case, but J could
have been equal to 1 (A) or 0 (C). Because of this, J is the 'don't care' term.
The JK flip-flop can actually be reconfigured so that it can perform the operation of some of
the other flip-flops that are discussed above. For example, if the two inputs J and K are tied
together, then the output characteristics are fixed to A and D. This precisely matches the
characteristics of a T type flip flop. Also to note, because the way a JK is made, you may
replace an SR flip-flop with a JK flip-flop without a change in operation. However you
cannot replace a JK flip-flop with an SR flip-flop as a S=1 R=1 condition is not allowed, but
a J=1 K=1 condition is permitted.
APPLICATIONS OF FLIP-FLOPS:- We have just seen that there are a variety of flip-flops.
In the subsections below, we illustrate a number of applications that use flip-flops as their
functional units. Switch Debouncing When mechanical switches are opened or closed, there
are brief current oscillations due to mechanical bouncing or electrical arcing. This
phenomenon is called switch bounce. As illustrated in Figure 6.16 , a single closing of a
switch can result in multiple voltage transitions that usually occur within a few milliseconds.
The sequential logic circuit shown in Figure 6.17 can provide an output that is free from
multiple transitions associated with switch bounce. As the switch breaks contact with B,
signal bounce occurs on the B line. There is a small delay as the switch moves from contact B
to A, and then signal bounce occurs on the A line as contact is established with A. However,
as a result of the feedback and logic, the output signal (Q) experiences only a single transition
from low to high (i.e., the output is bounce free). The circuit functions very much like a
flipflop
Like shift registers and other combinational circuits, there is another important element in
digital electronics which we use most. They are counters. Counters are used not only for
counting but also for measuring frequency and time ; increment memory addresses .Counters
remember the digital combinations of data. Counters are used everywhere and every time in
our day to day life. Example is the digital clock alarm that wakes you up in the early
morning.
Asynchronous Counters
Asynchronous counters are those whose output is free from the clock signal. Because the flip
flops in asynchronous counters are supplied with different clock signals, there may be delay
in producing output.
The counters which use clock signal to change their transition are called “Synchronous
counters”. This means the synchronous counters depends on their clock input to change state
values. In synchronous counters, all flip flops are connected to the same clock signal and all
flip flops will trigger at the same time.
The output of first JK flip flop (Q) is connected to the input of second flip flop. The AND
gates (which are connected externally) drives the inputs of other two flip flops . The inputs of
these AND gates , are supplied from previous stage lip flop outputs.
If inputs of FF2 are connected directly to the Q1 output of FF1 , the counter would not
function properly. This is because , the Q1 value is high at count of 210 , this means that the
FF2 flip flop will toggle for the 3rd clock pulse. This results in wrong counting operation,
gives the count as 710 instead of 410.
To prevent this problem AND gates are used at the input side of FF2 and FF3. The output of
the AND gate will be high only when the Q0, Q1 outputs are high. So for the next clock
pulse, the count will be 00012.
Similarly, the flip flop FF3 will toggle for the fourth clock pulse when Q0, Q1 and Q2 are
high. The Q3 output will not toggle till the 8th clock pulse and will again remain high until
16th clock pulse. After the 16th clock pulse, the q outputs of all flip flops will return to 0.
Operation
In the up counter the 4 bit binary sequence starts from 0000 and increments up to
1111.Before understanding the working of the above up counter circuit know about JK Flip
flop.
In the above circuit as the two inputs of the flip flop are wired together. So , there are only
two possible conditions that can occur, that is, either the two inputs are high or low.
If the two inputs are high then JK flip-flop toggles and if both are low JK flip flop remembers
i.e. it stays in the previous state.
Let us see the operation. Here clock pulse indicates edge triggered clock pulse .
1.) In the first clock pulse, the outputs of all the flip flops will be at 0000.
2.)In the second clock pulse, as inputs of J and k are connected to the logic high, output of JK
flip flop(FF0) change its state .Thus the output of the first flip-flop(FF0) changes its state for
every clock pulse .This can be observed in the above shown sequence .The LSB changes its
state alternatively. Thus producing -0001
3.) In the third clock pulse next flip flop (FF1) will receive its J K inputs i.e (logic high) and
it changes its state. At this state FF0 will change its state to 0. And thus input on the FF1 is
0.Hence output is -0010
4.) Similarly, in the fourth clock pulse FF1 will not change its state as its inputs are in low
state, it remains in its previous state. Though it produces the output to FF2, it will not change
its state due to the presence of AND gate. FF0 will again toggle its output to logic high state.
Thus Output is 0011.
5.) In the fifth clock pulse, FF2 receives the inputs and changes its state. While, FF0 will
have low logic on its output and FF1 will also be low state producing 0100.