1.
Combinational Logic
What: Output depends only on current inputs (no memory).
Block: Inputs → [ Combinational Logic ] → Outputs
Example: Sum-of-products function: F(A,B,C) = A·B + A'·C
Circuit: implemented with AND, OR, NOT gates.
Truth table (example for F):
A B C F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
2. Designing a logic circuit (procedure)
1. Write truth table. 2. Obtain Boolean expression (K-map or algebra). 3. Simplify. 4.
Draw gates. 5. Verify.
Block: Spec → Truth table → Simplify → Gate netlist → Test on all
inputs
3. Adders: Half & Full Adders
Half Adder
Purpose: Add two 1-bit numbers A and B → produce Sum and Carry.
Equations: Sum = A ⊕ B, Carry = A · B
Block: A,B → [ Half Adder ] → Sum, Carry
Truth table:
A B Sum Cout
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Circuit: XOR gate for sum, AND for carry.
Full Adder
Purpose: Add A + B + Cin → Sum, Cout.
Equations: Sum = A ⊕ B ⊕ Cin
Cout = A·B + B·Cin + A·Cin
Block: A,B,Cin → [ Full Adder ] → Sum, Cout
Truth table: (8 rows; example rows)
A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
1 1 1 1 1
...and so
on.
Circuit: Two half-adders + OR: HA(A,B) → S1,C1; HA(S1,Cin) → Sum,C2; Cout = C1 +
C2.
4. Subtractors: Half & Full Subtractors
Half Subtractor
Purpose: Subtract B from A (A − B) → Difference (D) and Borrow (Bo).
Equations: D = A ⊕ B, Bo = ¬A · B
Truth table:
A B D Bo
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Circuit: XOR for D, AND + NOT for Bo.
Full Subtractor
Purpose: A − B − Bin → D, Bout.
Equations: D = A ⊕ B ⊕ Bin
Bout = (¬A·B) + (B·Bin) + (¬A·Bin)
Implementation: Similar to full adder but borrow logic.
5. Design of Adder Circuits
Types: Ripple-carry adder (chain full adders), carry-lookahead adder (faster).
Block: cascade full adders:
A0,B0 → FA → S0,C1
A1,B1,C1 → FA → S1,C2 ...
Tradeoff: ripple is simple; lookahead reduces delay using propagate/generate signals.
6. Design of Subtractor Circuits
Approach 1: Implement using adders with 2’s complement: A + (−B) where −B = B' + 1.
Approach 2: Use chain of full subtractors (borrow ripple).
Block (2’s complement): B → NOT → +1 → add to A (use adder).
7. Lab: Half & Full Adder (practical)
What to do: Draw and build HA and FA on breadboard or simulator. Verify truth table for all
input combos. Measure propagation behavior (if possible).
8. Multiplexer (MUX)
Function: Select one of many inputs to pass to output using select lines.
2:1 MUX (one select S): Y = S'·I0 + S·I1
Block:
I0 ---\
>--[MUX S]--> Y
I1 ---/
Truth table (2:1):
S Y (if I0=0,I1=1 example)
0 I0
1 I1
Circuit: AND gates with selects, OR to combine, plus NOT for S'.
9. Implementation of a Boolean expression
using MUX
Idea: A MUX can implement any function of n variables using 2^n input lines or fewer by
using variables as select lines.
Example: Implement F(A,B) = A + B' using a 2:1 MUX with select = A: Y = A·1 +
A'·B' choose appropriate inputs: I1=1, I0=B'.
Block: A → select; inputs hardwired to constants or other expressions.
10. De-Multiplexer (DEMUX)
Function: Single input routed to one of many outputs based on select lines. Reverse of
MUX.
Block (1:2 DEMUX):
S
\
+--> Y0 = D·S'
D --+
+--> Y1 = D·S
Truth table (1→2):
S Y0 Y1
0 D 0
1 0 D
11. Encoder
Function: Map one-hot input (only one active input) to binary code.
4→2 Encoder example: Inputs I0..I3 produce outputs Y1 Y0:
I3 I2 I1 I0 Y1 Y0
0001 00
0010 01
0100 10
1000 11
Circuit: OR and logic to detect which input is active. Use priority encoder if multiple inputs
may be 1.
12. Decoder
Function: Map binary code to one-hot output.
2→4 Decoder (enable E): Outputs Y0..Y3, Yi = E·(binary == i)
Truth table:
A1 A0 Y3 Y2 Y1 Y0
00 0001
01 0010
10 0100
11 1000
Circuit: AND/NOT combinations to produce each output.
13. Lab: Half & Full Subtractor
Do this: implement HS and FS on simulator/breadboard; test all input combos; compare
with expected truth tables above.
14. Parity Generator
Purpose: Produce parity bit for data (even or odd parity).
Even parity for two bits A,B: P = A ⊕ B (so total 1s even).
Block: Data bits → [ XOR chain ] → Parity
Truth table (even parity for A,B):
A B P
0 0 0
0 1 1
1 0 1
1 1 0
15. Parity Checker
Purpose: Check if received data + parity bit satisfies selected parity.
Check for even parity (A,B,P): Check = A ⊕ B ⊕ P → if result = 0, parity OK; if =1,
error.
Circuit: XOR all bits; output indicates error or OK.
16. Checksum (simple)
Purpose: Lightweight error detection: sum data bytes/words and send truncated sum.
Receiver recomputes and compares.
Example (1-byte sum mod 256): Sender: CS = Σ bytes (mod 256); receiver: compute
Σ and check equality.
Circuit: Usually implemented with adder(s) and comparator.
17. Code Conversion
Examples: Binary ↔ BCD, Binary ↔ Gray.
Gray code from binary (n bits): G(n-1)=B(n-1), Gi = Bi+1 ⊕ Bi
Block: Binary input → [Logic network (XOR/AND/OR)] → Gray
Truth table (2-bit):
Binary Gray
00 00
01 01
10 11
11 10
18. Programmable Array Logic (PAL)
What: Fixed OR array, programmable AND array (or vice versa depending on device).
Useful for implementing sum-of-products cheaply.
Block: Inputs → [Programmable AND plane] → [Fixed OR plane] → Outputs
Use: Program product terms in AND plane; OR them to make outputs.
19. Programmable Logic Array (PLA)
What: Both AND and OR planes are programmable (more flexible than PAL).
Block: Inputs → [Programmable AND] → [Programmable OR] → Outputs
Use: Implement multiple outputs with shared product terms; good for custom
combinational logic.
20. Lab: Implementation of MUX (practical)
What to do: Build 2:1 and 4:1 MUX on breadboard or in Logisim. Test using switches for
selects and inputs; verify the Y = Σ S_i·I_i behavior. Also try implementing a Boolean
function using a MUX (from item 9).
