Tawfeeq Khan
§ GitHub | ï LinkedIn | # Email | +91 7975605521
SUMMARY
Electronics and Communication Engineering Graduate specializing in VLSI design with extensive experience in Standard Cell
Design Flow, ASIC Design Flow, and RTL to GDS implementation. Proficient in Verilog, and Python with a strong foundation in
digital design principles and EDA methodologies.
EDUCATION
Degree/Certificate Institute CGPA/Percentage Year
B.Tech PES University 7.5 2021-2025
Senior Secondary GRV PU College 90% 2019-2021
Secondary Kendriya Vidyalaya NAL Campus 86% 2009-2019
COURSEWORK
• Courses: Digital VLSI Design, VLSI Physical Design for ASIC, VLSI Designing: RTL to GDS, RISC V, Testing Of VLSI Circuits,
Power Management of Integrated Circuits, Analog Circuit Design
SKILLS
• Languages: Verilog (Intermediate), Python (Beginner), VHDl (Beginner), Matlab (Intermediate)
• Tools: Cadence Virtuoso (Advanced), Cadence Spectre (Advanced), genus (Advanced), Innovus (Advanced), Xcellium
(advanced), Xilinx Vivado (advanced), Xilinx Vitis (intermediate), Yosys (Intermediate), OpenLane (Intermediate), Matlab
Simulink (Intermediate)
EXPERIENCE/INTERESTS
• U R Rao Satellite Centre | Internship Feb-May 2025
→ Worked as a project Trainee on implementation of RapidIO Protocol on Xilinx/AMD SRAM FPFA for SpaceVPX Backplane
Architecture.
→ Gained knowledge in satellite High Data Rate communications protocol such as SpaceWire ,SpaceFibre and RapidIO and
learnt Skill and tool such as VHDL and Xilinx Vitis
• Teaching Assistant | Part-Time Jul - Dec 2024
→ conducted a 4 month course on Standard cell design for ASIC under CHIPS (Center for Heterogeneous and Intelligent
Processing Systems), learned the whole ASIC course online from CDAC Bangalore and transferred the knowledge to juniors.
60+ enrolled students.
PROJECTS
• Standard Cell Design Library | Verilog, Cadence Virtuoso, Xcellium Feb 2023 - Mar 2023
→ Designed standard cells which successfully passed DRC, LVS checks and ran post-synthesis simulation, AV Extraction and
Characterisation.
→ Developed Layout Designs following the standard cell design rules and libraries. Designed INV1X1, INV1X2, INV1X3 , INV1X4,
AND1X1,X2, NANDX1,X2, OR2X1,X2 and NOR2X1,X2 and DFF for gpdk 180nm..
• Subthreshold Standard Cell Library Design | Verilog, Cadence Virtuoso, Xcellium, Spectre , Calibre Feb 2023 - Jan 2025
→ Developed ultra-low power subthreshold standard cell library using SCL 180nm PDK .
→ Successfully Designed all the Basic gates, Flip flop, Half Adder using Cadence tool.
• VLSI Physical Design for ASIC | Verilog, Genus. Innovus, tempus, Xcellium Aug 2023- Dec 2024
→ Successfully Designed standard cell based ASIC designs of Full Adder , 32 Bit RCA , 4 Bit CLA etc) using SCL 180nm pdk in
Cadence tool.
→ Completed the RTL to GDSII flow for a 4-Bit Ring Counter as a project for the Course held by Kunal Ghosh, VSD squadron
using Skywater130nm PDK on OpenLane.
• RISC V Single Cycle Processor | Verilog, Xilinx Vivado Feb - May 2025
→ Designed and implemented a complete 32-bit RISC-V single-cycle processor supporting R-type, I-type, L-type, S-type, and
B-type instruction sets
→ Developed integrated datapath and control unit with ALU, register file, and memory interface for full instruction execution.
→ Synthesized and verified processor functionality using Xilinx Vivado with comprehensive testbench validation.
CERTIFICATIONS
• System Design Through Verilog Elite + Silver medal in NPTEL certification exam
• Certificate of Participation Participated in a 1 week workshop on Standard cell Design Conducted by CHIPS(Centre for
Heterogenous and Intelligent Processing Systems).
