Analog VLSI Circuit Design

Laboratory
Laboratory #1: Introduction to Cadence
Objectives
Learn how to login on a Linux workstation, perform basic Linux tasks, and use the Cadence design
system to simulate and layout simple circuits.
Introduction
This lab will introduce students to the computer system and software used throughout the lab
course. First, students will learn how to login and logout of a Linux workstation. Next, basic operating
system commands used to perform file management, printing, and various other tasks will be
illustrated. Finally, students will be given an overview of the Cadence Development System.
In class examples will demonstrate the creation of libraries, the construction of schematic symbols,
the drafting of schematics, and the layout of simple transistors. The student will apply this knowledge
to the creation of a CMOS inverter.

Logging-in/Logging-out
In order to use the Linux machines, you must first login to the system. As with the PC lab, enter
the login ID and password at the prompts. Login using the login ID and password obtained from the
department (center). This is your account and all files stored in this area will be retained by the system
after logging-out.

Using the Linux Operating System

Using the Linux operating system is similar to using other operating systems such as DOS. Linux
commands are issued to the system by typing them in a “shell” or “xterm”. Linux commands are case
sensitive so be careful when issuing a command, usually they are given in lower-case.

The following list summarizes some basic commands required to manage the data files you will be
creating in this lab course. All Linux commands are entered from the shell or xterm window. Do not
use Linux commands for modifying, deleting, or moving any Cadence data files.

Table 1-1: Common UNIX commands.

ls [-la] List files in the current directory. “l” list with properties and “a” also
lists hidden files (ones beginning with a “.”).
cd xx Change the current directory to xx.
cd .. Change the current directory to one level up (parent directory).
pwd Show the current location in relation to the whole file-system
cp xx yy Copy the file xx to yy.
mv xx yy Move the file xx to yy. Also used for renaming.
rm xx Delete the file xx (use /bin/rm to remove without prompt).
rmdir xx Remove directory xx
mkdir xx Create directory xx.
lp –d xx yy Print the textfile or postscript file yy to the printer named xx, where
xx can be either “ipszac” or “hpszac”.
gedit xx & Start the gedit (text editor program) and load file xx.
ps –u user List processes of user.
 top Check available processes and memory usage.
quota –v Check for disk space available
Kill –l -l Kill all my processes
tar –cvf xx.tar /home/test1 Create a new archive xx.tar from /home/test1
tar –xvf xx.tar test1.tar test1 Extract test1.tar archive into test1
Virtuoso & Execute cadence virtuoso
Note: The command “&” tells Linux to execute the command and return the prompt to the active shell

Cadence
The Cadence Development System consists of a bundle of software packages such as schematic
editors, simulators, and layout editors. This software manages the development process for analog,
digital, and mixed-mode circuits. In this course, we will strictly use the tools associated with analog
circuit design.
All the cadence design tools are managed by a software package called the Design Framework II.
This program supervises a common database which holds all circuit information including schematics,
layouts, and simulation data.
From the Design Framework II, also known as the “framework”, we can invoke a program called
the Library Manager, which governs the storage of circuit data. We can access libraries and the
components of the libraries called cells.
A program called “Virtuoso Layout Suite” is used for creating integrated circuit layouts. The layout
is used to create the masks, which are used in the integrated circuit fabrication process.
Finally, a circuit simulation is handled through an interface called Analog Design Environment
(ADE). This interface can be used to invoke various simulators including Hspice, Spectre, and Verilog.
We will be using the Spectre simulator in this course.

Starting Cadence Using Linux workstations

You can connect to lab workstations using secure shell (ssh) from another computer in the lab. If
the computer has Linux or Unix operating system, you can use the following command to connect to
lab workstations.
ssh –X hostname

If you are connecting from a computer that has Windows operating system, you need to have an
ssh client and an X-server installed. Make sure that the connections are tunneled within the settings
of ssh client you are using. Once you login, you can start Cadence using following command:
virtuoso &

Figure 1-1: The Cadence CIW

 This will load Cadence. The command Interpreter Window (CIS) will now load as shown in Figure
1-1.

Starting a Design
From the CIW, select Tools → Library Manager to load the Library manager (Figure 1-2). The Library
Manager stores all designs in a hierarchal manner. A library is a collection of cells. For example, if you
had a digital circuits library named Digital, it will have several cells included in it. These cells will be
inverters, nand gates, nor gates, multiplexers, and etc. Each cell has different views. These views will
in general be things such as symbols, schematics, or layout of each cell.

Figure 1-2: Cadence library manager

Figure 1-3: Create a library, and attach a tech library (file)

 The first thing you need to do to start a design is create a library to store the cells you will be
designing in this lab. Let’s call this library “AMSIC_LAB”. From the library manager, select File → New
→ Library. Name the library “AMSIC_LAB” (without quotes) and select OK. In the window, that appears
select “Attach to an existing tech file” (Figure 1-3) and select OK. In the next window make sure that
“tsmcN65” Technology library is selected and select OK.

Creating a Schematic
The first circuit we will design is a simple inverter. Select which library you want to put the cell into,
in this case “AMSIC_LAB”, and then File → New → Cell View. Name your cell “inverter”. The application
you want to use here is schematics L as seen in Figure 1-4.

Figure 1-4: Create a cellview.

After selecting OK, the schematic window opens. We wish to add two transistors so that we can
make an inverter. To do this, we need to add an instance. You can do this by either clicking Create →
Instance or by pressing “i” on the keyboard. A window titled “Component Browser” should pop up.
Hit the “Browse” button, and make sure that the library tsmcN65 is selected. Select “nch” and then
symbol. Go back to the schematic and select where you would like to add the NMOS transistor. Go
back to the component browser and select “pch” and then symbol. Add this transistor to your
schematic. Hit ESC to exit the add instance mode.
Connect components together using wires. You can select Add → Wire or use “w” hotkey. Pins
identify the inputs and outputs of the schematic. Click add → pin or use the “p” hotkey. Pin names
and directions must be consistent between the symbol, schematic, and layout. The name uniquely
identifies the pin while the direction indicates the usage of the pin. Using the inputOutput direction is
recommended for power supplies.
To change the properties of a device, use Edit → properties → Objects or use the “q” hotkey. In
order to compensate for lower mobility in the PMOS, try changing the width if the PMOS transistor
from 200n to 400n. Place the pins on the wires each net. Beware of the direction of pins. When finished,
your schematic should resemble Figure 1-5.

Important: Use all uppercase letters in the PDK when naming pins and/or nets.

Select Design → Check and Save, or press F8 to save your schematic and make sure that there are
no errors or warnings.

Figure 1-5: Inverter schematic.

Creating a Symbol
From the schematic window, select Create → Cellview → From Cellview, and click OK. In the next
window, arrange the pin specifications and click OK. The symbol editor will appear with the default
symbol. Using the editor, modify the symbol so that it will resemble the one shown in Figure 1-7.

Figure 1-6: Create a symbol from schematic.

 Figure 1-7: Final inverter symbol.

Creating a Layout
After the schematic and symbol have been designed, it is time to move onto the layout of the
circuit. From the schematic window, select Launch → Layout XL. Pop-up window will appear (Figure 1-
8), then click OK. Virtuoso Layout Suite should open as shown in Figure 1-9.

Figure 1-8: Create a layout cell view.

 Figure 1-9: Virtuoso Layout Suite.

In order to effectively place and route objects in the layout, you need to disable “Gravity On” in
Options → Editor. The layout consists of instances, paths, rectangles and pins. A transistor can be
inserted into the layout using Create → Instance, or press I and selecting nmos or pmos layout after
clicking on Browse button. Use “shift-f” hotkey to see the layers after inserting the instances.
Properties such as W and L of the transistors/metal wires can be modified from the properties window
(“q” hotkey after selection).

Alternatively, transistors can be created from scratch (not recommended) by drawing rectangles
for its gate, diffusion and metal regions. The gate region is created by drawing a rectangle with poly
(drw) or “r” on the keyboard. The diffusions for a transistor are created by drawing a rectangle with
the active (drw) layer. The intersection of poly and active regions defines the size (length and width)
of the transistors. In order to define whether a transistor is NMOS or PMOS, NP (drw) or PP(drw) needs
to surround the active area. The design rules describe minimum spacing and size requirements for
various rectangles. Some basic design rules for this technology are shown in Figure 1-10.

Substrate contacts and vias between layers of metal can also be inserted using Create → Via or
press “o”. Use OD_M1 via for both NP and PP(substrate connections). Enclose NP with NW, PP with BP.
To add a pin, select Create → Pin. “Terminal Name” should be the name of the pin in the schematic.
Make sure that the “Display Pin Name” option is checked in the Options → Display so that the pin
name will appear in the layout. Pin Layer should be the same as the metal layer that it is connecting to
but its purpose should be label.

Design Rule Check (DRC) needs to be performed during the placement of instances and throughout
the layout development. To avoid extra work later, DRC needs to be run as often as possible during the
completion of layout (see the next section). When finished, enclose the entire layout with GRLOGIC
layer. Moreover, you should obtain a layout of the inverter that resembles Figure 1-11.
 After the layout is done, several steps have to be followed to ensure that the layout is correct.
These steps involve performing the analysis in the following sections.

Figure 1-10: Basic design rules

Figure 1-11: Inverter layout.

 Table 1-1: Post-Layout Steps.
DRC Design Rule Check (DRC). Checks physical layout data against fabrication-
specific rules. Typical checks include spacing, enclosure and overlap.
LVS Layout Versus Schematic (LVS). Compares a physical layout design to the
schematic where it was designed.
Parasitic extraction Device parameters and connectivity are extracted from the layout in order
to perform ERC, Short Locator, LVS and post-layout simulation and analysis.

DRC
To run DRC for the layout, select Calibre → Run DRC. Then, Calibre Interactive window will show
up. For the DRC setting, find the DRC rule file inside the relevant location and then click on Run DRC.
The total number of errors will show up in the RVE window as seen in Figure 1-12. DRC check should
be performed not only after the layout is completed, but also during the layout work as mentioned
earlier. Figure 1-12 shows a rule setting and RVE report window.

Figure 1-12: Calibre DRC settings & DRC report.

The error will usually show up in the layout with highlights. To have Cadence address what and
where the error is, double click the error and number, respectively. And, Cadence will explain what
design rules are broken. Adjust the layout to fix these errors and then rerun DRC until you have no
design rule errors except density violations that can be waivered until design rule of the layout is
evaluated at the full chip level.

LVS
To run LVS, click Calibre → Run LVS. The LVS settings window will show just like the DRC settings in
Figure 1-12. Make sure that rule file is referenced into proper location such as
“./PDK/Calibre/lvs/calibre.lvs”. Furthermore in the Inputs option, select Netlist tab then click on
“Export from schematic viewer” to generate your netlists from the schematic as a reference
comparison to your layout. Click Run LVS, then LVS report should pop up once LVS has completed saying
that the job succeeded. Click OK, and Calibre RVE window will popped up with smile emoticon if your
schematic and layout are matched each other. If they do not match, go back to the LVS window and
select Error Display to find out what your errors are. Adjust the layout to match, rerun DRC, and LVS
until the netlist match. Figure 1-13 shows Calibre Interactive LVS settings and Calibre RVE windows.

Figure 1-13: Calibre LVS settings & LVS report.

Parasitic Extraction
Once DRC and LVS are successful, you can now extract the layout for post-layout simulation. To run
Extraction, click Calibre → Run PEX. The PEX settings window will show up in the screen, then you
need several settings to proceed. Ensure that the rule file is referenced into the proper location such
as “./PDK/Calibre/rcx/calibre.rcx” and the generated netlist file from LVS is set into your netlist input
option. Then, go to Output options, in the Netlist tab, select CALIBRE VIEW as format and use name
from SCHEMATIC. Then, Calibre Views setup window will pop up, then select the calview.cellmap file
that is located in the same folder as your rule files. Figure 1-14 shows the PEX window settings and
Calibre Views setup window.

Figure 1-14: Calibre PEX settings for Parasitic Extraction.

Schematic Simulation
To test the inverter, we need to create a new schematic cell view called “TB_Inverter” in order to
build a test bench. To simulate the design, add the inverter symbol, signal sources, power supplies,
and loads as illustrated in Figure 1-15. For parameters, we can use VDD=1.8 V, and signal sources with
vin V.

Figure 1-15: inverter test-bench schematic.

Start the simulator environment by selecting Launch → ADE L. The simulator should appear in a
few moments. Select Setup → Simulator/Directory/Host and verify that spectre is the simulator. Then,
we need to configure the environment to run our first simulation. In the ADE window, select Analyses
→ Choose. Select “dc”, check “design variable”, click on “select design variable” and choose “vin”.
We can choose any desired voltage for the sweep by putting the numbers in “start” and “stop”. In this
case, we want to sweep the input voltage from ground to VDD. Thus, we input 0 to “start” and 1.8 to
“stop” and click OK. Then, to set the output plot, click Outputs → Setup. A new window will show up,
then select “From Schematic”, then click on the output node and input node of the circuit. ADE L
settings example depicted in Fig. 1-16.
 Figure 1-16: ADE-L settings.

The simulator should now be configured to run the simulation. Select Simulation → Netlist and
Run. Once the simulation is complete, the pop up window will show up according to the “Outputs”
setting that we configured earlier. Alternatively, we can plot waveforms using the calculator. To access
the calculator, select Tools → Calculator in the analog environment. Since our analysis was done for
dc sweep, click the “vs” button (The “v” is for voltage and the “s” is for DC sweep). Next, click on the
output node in the schematic. You can now plot the output as a function of the swept variable, which
in this case is the inverter input (vin) by selecting Tools → Plot. Your output waveform should resemble
Fig 1-17.

Figure 1-17: Inverter input & output plot.

Simulating the Extracted Layout
For post-layout simulation to account for various parasitics, you must prioritize calibre in the view
list over sechematic and/or veriloga in the spectre environment before running simulations.
In the Analog Design Environment (ADE), select Setup → Environment. In the field labeled “Switch
View List”, add “calibre” before “schematic” as shown in figure 1-18. All other steps in simulation of
the extracted view will now be the same as they were for simulating the schematic.

Figure 1-18: Add extracted view to switch view list.

Prelab
No prelab lab report is required this week other than the printouts listed in the Prelab section.

Lab Report
Turn in print outs of the following as a lab report:
1. Inverter schematic
2. Inverter symbol
3. DC sweep output graph showing the inverter was simulated
4. Inverter layout
5. Copy of the LVS output file showing that the netlists match
6. Post-layout simulation: DC sweep output graph with comparison to Pre-layout simulation
7. Post-layout simulation: Transient with 1pF loading capacitor with comparison to Pre-layout
simulation
8. Discussion