Understanding Delta-Sigma Data Converters
Richard Schreier
Analog Devices, Inc.
Gabor C. Temes
Oregon State University
OlEEE
IEEE Press
iWILEYINTERSCIENCE
A JOHN WILEY & SONS, INC., PUBLICATION
Contents
Foreword
References xii
xi
CHAPTER 1
Introduction
1.1 The Need for Oversampling Converters 1 1.2 Delta and Delta-Sigma Modulation 4 1.3 Higher-Order Single-Stage Noise-Shaping Modulators 1.4 Multi-Stage (Cascade, MASH) Modulators 10 1.5 Bandpass AZ Modulators 13 1.6 AZ Modulators with Multi-Bit Quantizers 15 1.7 Delta-Sigma Digital-to-Analog Converters 16 1.8 History; Performance and Architecture Trends 17
CHAPTER 2
The First-Order Delta Sigma Modulator
2.1 Quantizers and Quantization Noise
2.].] Binary Quantization 28
21
21
Contents
2.2 MODI as an ADC 29 2.3 MODI as a DAC 34 2.4 MODI Linear Model 36 2.5 Simulation of MODI 38 2.6 MODI under DC Excitation 41 2.6.1 Idle Tone Generation 42 2.6 2 Graphical Visualization 45 2.7 Stability of MODI 49 2.8 The Effects of Finite Op-Amp Gain 50 2.8.1 Linear Systems Perspective- Degraded Noise Shaping 50 2.8.2 Nonlinear Systems Perspective- Dead Zones 51 2.9 Decimation Filters for MOD 1 54 2.9.1 The Sine Filter [9] 55 2.9.2 The Sine2 Filter 58 2.10 Conclusions 60
CHAPTER 3
The Second-Order Delta-Sigma Modulator
3.1 The Second-Order Modulator: MOD2 63 3.2 Simulation of MOD2 67 3.3 Nonlinear Effects in MOD2 71 3.3 1 Signal-dependent quantizer gain 71 3.3.2 Stability ofMOD2 74 3.3.3 Dead-band behavior 77 3.4 Alternative Second-Order Modulator Structures 79 3.4.1 The Boser- Wooley Modulator 79 3.4.2 The Silva-Steensgaard Structure 80 3.4.3 The Error-Feedback Structure 81 3.4.4 Generalized Second-Order Structures 82 3.4.5 Optimal Second-Order Modulator 84 3.5 Decimation Filtering for Second-Order A Modulators 3.6 Conclusions 89
63
86
CHAPTER 4
Higher-Order Delta-Sigma Modulation
91
4.1 High-Order Single-Quantizer Modulators 91 4.2 Stability Considerations in High-Order Modulators 97
VI
Contents
4.2.1 Single-Bit Modulators 98 4.2.2 Multi-Bit Modulators [12] 104 A3 Optimization of the NTF Zeros and Poles 107 4.3.1 NTF Zero Optimization 107 4.3.2 NTF Pole Optimization HI 4.4 Loop Filter Architectures 115 4.4.1 Loop Filters with Distributed Feedback and Input Coupling- The CIFB and CRFB Structures 115 4.4.2 Loop Filters with Distributed Feedforward and Input Coupling- The CIFF and CRFF Structures 121 4.5 Multi-Stage Modulators 122 4.5.1 The Leslie-Singh (L-0 Cascade) Structure [16] 123 4.5.2 Cascade (MASH) Modulators 127 4.5.3 Noise Leakage in Cascade Modulators 132 4.6 Conclusions 136
CHAPTER 5
Bandpass and Quadrature Delta-Sigma Modulation 139
5.1 The Need for Bandpass and Quadrature Modulation 139 5.2 Bandpass NTF Selection 145 5.2.1 Pseudo N-path transformation 149 5.3 Architectures for Bandpass Delta-Sigma Modulators 151 5.3.1 Topology Choices 151 5.3.2 Resonator Implementations 154 5.4 Bandpass Modulator Example 161 5.5 Quadrature Signals 166 5.6 Quadrature Modulation 172 5.7 Conclusions 176
CHAPTER 6
Implementation Considerations For AE ADCs
6.1 Modulators with Multi-Bit Internal Quantizers 179 6.2 Dual-Quantizer Modulators 182 6.2.1 Dual-Quantization MASH Structure 182 6.2.2 Dual-Quantization Single-Stage Structure 183 6.3 Dynamic Element Randomization 184
179
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Contents
6.4 Mismatch Error Shaping
6.4.1 6.4.2 6.4.3 6.4.4
186
Element Rotation or Data-Weighted Averaging 189 Individual Level Averaging 191 Vector-Based Mismatch Shaping 192 Element Selection Using a Tree Structure 196
6.5 Digital Correction of DAC Nonlinearity 199 6.5.1 Digitally-Corrected Multi-Bit AS Modulator with Power-Up Calibration 200 6.5.2 Digitally-Corrected Multi-Bit AS ADC with Background Calibration 202 6.6 Continuous-Time Implementations 205 6.6.7 A Continuous-Time Implementation ofMOD2 207 6.6.2 Inherent Anti-Aliasing in CT AS ADCs 212 6.6.3 Design Issues for Continuous-Time Modulators 213 6.7 Conclusions 216
CHAPTER 7
Delta-Sigma DACs 219
7.1 System Architectures for AS DACs 220 7.2 Loop configurations for AE DACs 222
7.2.1 Single-Stage Delta-Sigma Loops 223 7.2.2 The Error Feedback Structure 224 7.2.3 Cascade (MASH) Structures 226 7.3 AL DACs Using Multi-Bit Internal DACs 229 7.3.1 Dual-Truncation DAC Structures 230 7.3.2 Multi-bit Delta-Sigma DACs with Mismatch Error Shaping 7.3.3 Digital Correction of Multi-Bit Delta-Sigma DACs 236 7.3.4 Comparison of Single-Bit and Multi-Bit AS DACs 238 7.4 Interpolation Filtering for AZ DACs 239 7.5 Analog Post-Filters for AS DACs 243 7.5.1 Analog Post-Filtering in Single-Bit AS DACs 244 7.5.2 Analog Post-Filtering in Multi-Bit AS DACs 251 7.6 Conclusions 253
232
CHAPTER 8
High-Level Design and Simulation
8.1 NTF Synthesis 257 8.1.1 How synthesizeNTF works 260
257
V11I
Contents
8.1.2 Limitations o/synthesizeNTF 262 8.2 NTF Simulation, SQNR Calculation and Spectral Estimation 8.3 NTF Realization and Dynamic Range Scaling 266 8 3.1 The ABCD Matrix 2 71 8.4 Creating a SPICE-Simulatable Schematic 273 8.4.1 Voltage Scaling 273 8.4.2 Tuning 274 8.4.3 kT/C Noise 280 8.5 Conclusions 281
263
CHAPTER 9
Example Modulator Systems
283
9.1 SCMOD2: General-Purpose Second-Order Switched-Capacitor ADC 283 9.1.1 System Design 284 9.1.2 Timing 286 9.1.3 Scaling 288 9.1.4 Verification 289 9.1.5 Capacitor Sizing 292 9.1.6 Circuit Design 294 9.2 SCMOD5: A Fifth-Order Single-Bit Noise-Shaping Loop 298 9.2.1 NTF and Architecture Selection 298 9.2.2 Implementation 302 9.2.3 Instability and Reset 311 9.3 A Wideband 2-0 Cascade System 311 9.3.1 Architecture 312 9.3 2 Implementation 315 9.4 A Micropower Continuous-Time ADC 317 9.4.1 High-Level Design 318 9.4.2 Circuit Design 322 9.5 A Continuous-Time Bandpass ADC 326 9.5.1 Architecture/Analysis 328 9.5.2 Subcircuits 333 9.6 Audio DAC 337 9.6.1 Modulator Design 338 9.6.2 Interpolation Filter Design 344 9.6.3 DAC and Reconstruction Filter Design 355 9.7 Conclusions 357 9.7.1 The ADC State-of-the-Art 357
IX
Contents
9.7.2 FOM Justification
359
9.7.2 References
362
APPENDIX A
Spectral Estimation
365
A. 1 Windowing 366 A.2 Scaling and Noise Bandwidth 373 A.3 Averaging 377 A.4 An Example 379 A.5 Mathematical Background 383
APPENDIX B
The Delta-Sigma Toolbox 389
Demonstrations and Examples 390 Summary of Key Functions 391
synthesizeNTF 393 predictSNR 395 simulateDSM 396 simulateSNR 398 realizeNTF 400 stuffABCD, mapABCD scaleABCD 402 calculateTF 403 simulateESL 404 designHBF 405 simulateHBF 408 findPIS 409
401
Modulator Model Details 410 APPENDIX C
Noise in Switched-Capacitor Delta-Sigma Data Converters 417
C.I Noise Effects in CMOS Op Amps 419 C.2 Sampled Thermal Noise 423 C.3 Noise Effects in an SC Integrator 425 C.4 Integrator Noise Analysis Example 433 C.5 Noise Effects in Delta-Sigma ADC Loops
435
