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Silicon N Channel MOS FET High Speed Power Switching: Features

The document provides specifications for the 2SK3069 Silicon N Channel MOS FET, highlighting its low on-resistance and low drive current capabilities. It includes absolute maximum ratings, electrical characteristics, and detailed graphs illustrating performance under various conditions. Additionally, it contains information on package dimensions and ordering details.

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Valcu Marius
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0% found this document useful (0 votes)
4 views8 pages

Silicon N Channel MOS FET High Speed Power Switching: Features

The document provides specifications for the 2SK3069 Silicon N Channel MOS FET, highlighting its low on-resistance and low drive current capabilities. It includes absolute maximum ratings, electrical characteristics, and detailed graphs illustrating performance under various conditions. Additionally, it contains information on package dimensions and ordering details.

Uploaded by

Valcu Marius
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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2SK3069

Silicon N Channel MOS FET


High Speed Power Switching
REJ03G1062-1100
(Previous: ADE-208-694I)
Rev.11.00
Sep 07, 2005

Features
• Low on-resistance
RDS(on) = 6 mΩ typ.
• Low drive current
• 4 V gate drive device can be driven from 5 V source

Outline

RENESAS Package code: PRSS0004AC-A


(Package name: TO-220AB)
D

1. Gate
2. Drain
(Flange)
G 3. Source

1
2
3
S

Rev.11.00 Sep 07, 2005 page 1 of 7


2SK3069

Absolute Maximum Ratings


(Ta = 25°C)
Item Symbol Ratings Unit
Drain to source voltage VDSS 60 V
Gate to source voltage VGSS ±20 V
Drain current ID 75 A
Drain peak current ID(pulse) Note 1 300 A
Body-drain diode reverse drain current IDR 75 A
Avalanche current IAP Note 3 50 A
Avalanche energy EAR Note 3 214 mJ
Channel dissipation Pch Note 2 100 W
Channel temperature Tch 150 °C
Storage temperature Tstg –55 to +150 °C
Notes: 1. PW ≤ 10µs, duty cycle ≤ 1 %
2. Value at Tc = 25°C
3. Value at Tch = 25°C, Rg ≥ 50 Ω

Electrical Characteristics
(Ta = 25°C)
Item Symbol Min Typ Max Unit Test Conditions
Drain to source breakdown voltage V(BR)DSS 60 — — V ID = 10 mA, VGS = 0
Gate to source leak current IGSS — — ±0.1 µA VGS = ±20 V, VDS = 0
Zero gate voltage drain current IDSS — — 10 µA VDS = 60 V, VGS = 0
Gate to source cutoff voltage VGS(off) 1.0 — 2.5 V ID = 1 mA, VDS = 10 V Note 4
Static drain to source on state RDS(on) — 6.0 7.5 mΩ ID = 40 A, VGS = 10 V Note 4
resistance — 8.0 12 mΩ ID = 40 A, VGS = 4 V Note 4
Forward transfer admittance |yfs| 50 80 — S ID = 40 A, VDS = 10 V Note 4
Input capacitance Ciss — 7100 — pF VDS = 10 V, VGS = 0,
Output capacitance Coss — 1000 — pF f = 1 MHz
Reverse transfer capacitance Crss — 280 — pF
Total gate charge Qg — 125 — nC VDD = 25 V, VGS = 10 V,
Gate to source charge Qgs — 25 — nC ID = 75 A
Gate to drain charge Qgd — 25 — nC
Turn-on delay time td(on) — 60 — ns VGS = 10 V, ID = 40 A,
Rise time tr — 300 — ns RL = 0.75 Ω
Turn-off delay time td(off) — 520 — ns
Fall time tf — 330 — ns
Body–drain diode forward voltage VDF — 1.05 — V IF = 75A, VGS = 0
Body–drain diode reverse recovery trr — 90 — ns IF = 75A, VGS = 0
time diF/ dt = 50 A/ µs
Note: 4. Pulse test

Rev.11.00 Sep 07, 2005 page 2 of 7


2SK3069

Main Characteristics

Power vs. Temperature Derating Maximum Safe Operation Area


200 1000
Channel Dissipation Pch (W)

300 10
10 µ
0µ s

Drain Current ID (A)


150 100 PW 1 s
= m
10 s
30 DC m
Op s(
e 1
sh
100 10 (T rati ot
c = on )
Operation in 25
°C
3 this area is )
limited by RDS(on)
50 1

0.3
0.1 Ta = 25°C
0 50 100 150 200 0.1 0.3 1 3 10 30 100

Case Temperature TC (°C) Drain to Source Voltage VDS (V)

Typical Output Characteristics Typical Transfer Characteristics

100 100
VGS = 10 V Pulse Test
VDS = 10 V
5V
80 4V 80 Pulse Test
3.5 V
Drain Current ID (A)

Drain Current ID (A)

60 60

40 40
3V
25°C
20 20
75°C
2.5 V Tc = –25°C
0 2 4 6 8 10 0 1 2 3 4 5

Drain to Source Voltage VDS (V) Gate to Source Voltage VGS (V)

Drain to Source Saturation Voltage Static Drain to Source on State


vs. Gate to Source Voltage Resistance vs. Drain Current
RDS (on) (mΩ)
Static Drain to Source on State Resistance

2.0 100
VDS (on) (V)
Drain to Source Saturation Voltage

Pulse Test Pulse Test


50
1.6

20
1.2
10 VGS = 4 V
0.8
5 10 V

0.4 ID = 50 A
2
20 A
10 A
1
0 4 8 12 16 20 1 2 5 10 20 50 100 200

Gate to Source Voltage VGS (V) Drain Current ID (A)

Rev.11.00 Sep 07, 2005 page 3 of 7


2SK3069

Static Drain to Source on State Forward Transfer Admittance


Resistance vs. Temperature vs. Drain Current

RDS (on) (mΩ)


Static Drain to Source on State Resistance

Forward Transfer Admittance yfs (S)


20 500
Pulse Test VDS = 10 V
200 Pulse Test
16 100
20 A
ID = 50 A 50 Tc = –25°C
12 10 A
20
4V 10
8 25°C
10, 20, 50 A 5
75°C
4 VGS = 10 V 2
1
0 0.5
–50 0 50 100 150 200 0.1 0.3 1 3 10 30 100

Case Temperature TC (°C) Drain Current ID (A)

Body to Drain Diode Reverse Typical Capacitance


Recovery Time vs. Drain to Source Voltage

1000 30000
VGS = 0
Reverse Recovery Time trr (ns)

500 f = 1 MHz
10000 Ciss
Capacitance C (pF)

200
3000
100
1000 Coss
50

300 Crss
20 di / dt = 50 A / µs
VGS = 0, Ta = 25°C
10 100
0.1 0.3 1 3 10 30 100 0 10 20 30 40 50

Reverse Drain Current IDR (A) Drain to Source Voltage VDS (V)

Dynamic Input Characteristics Switching Characteristics

100 20 1000
Drain to Source Voltage VDS (V)

Gate to Source Voltage VGS (V)

ID = 75 A td(off)
VGS 500
Switching Time t (ns)

80 16
tf
VDD = 50 V 200
60 V 25 V 12
DS tr
10 V 100
td(on)
40 8
50

20 VDD = 50 V 4 20
25 V VGS = 10 V, VDD = 30 V
10 V PW = 5 µs, duty < 1 %
0 10
0 80 160 240 320 400 0.1 0.2 0.5 1 2 5 10 20 50 100

Gate Charge Qg (nc) Drain Current ID (A)

Rev.11.00 Sep 07, 2005 page 4 of 7


2SK3069

Reverse Drain Current vs. Maximum Avalanche Energy vs.


Source to Drain Voltage Channel Temperature Derating

Repetitive Avalanche Energy EAR (mJ)


100 250
(A)

IAP = 50 A
10 V
VDD = 25 V
Reverse Drain Current IDR

80 200
5V duty < 0.1 %
Rg > 50 Ω
60 150

VGS = 0, –5 V
40 100

20 50

Pulse Test
0
0 0.4 0.8 1.2 1.6 2.0 25 50 75 100 125 150

Source to Drain Voltage VSD (V) Channel Temperature Tch (°C)

Normalized Transient Thermal Impedance vs. Pulse Width


Normalized Transient Thermal Impedance γs (t)

Tc = 25°C
1
D=1

0.5
0.3

0.2
θ ch – c(t) = γ s (t) • θ ch – c
0.1 0.1 θ ch – c = 1.25°C/W, Tc = 25°C
0.05
PDM PW
D=
0.02 T
0.03 1 lse
0.0 t pu PW
h o
1s T

0.01
10 µ 100 µ 1m 10 m 100 m 1 10

Pulse Width PW (S)

Avalanche Test Circuit Avalanche Waveform


VDSS
L 1
VDS EAR = • L • IAP2 •
2 VDSS – VDD
Monitor
IAP V(BR)DSS
Monitor
IAP
Rg D. U. T VDD VDS
ID
Vin 50 Ω
15 V
VDD
0

Rev.11.00 Sep 07, 2005 page 5 of 7


2SK3069

Switching Time Test Circuit Switching Time Waveforms

Vin Monitor Vout 90%


Monitor
D.U.T.
Vin 10%
RL
Vout 10% 10%
Vin VDD
50 Ω = 30 V
10 V
90% 90%

td(on) tr td(off) tf

Rev.11.00 Sep 07, 2005 page 6 of 7


2SK3069

Package Dimensions
JEITA Package Code RENESAS Code Package Name MASS[Typ.]
Unit: mm
SC-46 PRSS0004AC-A TO-220AB / TO-220ABV 1.8g

11.5 Max

2.79 ± 0.2
10.16 ± 0.2 4.44 ± 0.2
9.5 +0.1
φ 3.6 –0.08 1.26 ± 0.15
8.0

–0.1
+0.2
6.4

15.0 ± 0.3
1.27
18.5 ± 0.5

2.7 Max

1.5 Max

14.0 ± 0.5
7.8 ± 0.5

0.76 ± 0.1

2.54 ± 0.5 2.54 ± 0.5 0.5 ± 0.1

Ordering Information
Part Name Quantity Shipping Container
2SK3069-E 500 pcs Box (Sack)
Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of
production before ordering the product.

Rev.11.00 Sep 07, 2005 page 7 of 7


Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

Keep safety first in your circuit designs!


1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.

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© 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.


Colophon .3.0

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