IAE
CMOS Basics
MOS Transistor Behavior
Saturation Region: an imperfect switch n-Channel saturation current IDS(sat) =( n/2)(VGS-Vtn)2 p-Channel saturation current IDS(sat) =-( p/2)(VGS-Vtp)2
n and p = n and p channel transistor gain VGS = gate-to-source voltage Vtn and Vtp = n- and p-channel transistor threshold
n-channel transistor turns on with positive gate voltage p-channel transistor turns on with negative gate voltage n-channel transistor passes strong 0 but weak 1 p-channel transistor passes strong 1 but weak 0
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VDD A Mp Mn
Basic CMOS Inverter
Let: VDD = logic 1 0V = logic 0 A 1 0 F 0 1 VDD
F=A
VSS = 0V Switch Model A=0 VDD A=1
F = 1
F = 0
VSS
VSS
IAE
Institute of Advanced Microelectronics University of New Mexico
CMOS Inverter Layout
VDD VDD
Gate Polysilicon p+
N well
Metal
F=A
Metal n+ Gate
VSS
VSS
Metal Contacts
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Static CMOS NAND Gate
VDD B A B Output is 0 only when both N-transistors are on, i.e., when A=B=1 A F=(A and B) A 0 0 1 1 B F 0 1 0 1 1 1 1 0
A B
NAND Gate: Symbolic Layout
VDD
VDD Contact Metal
B A B F
A p-diffusion poly-Si F n-diffusion A B
A B
VSS Metal
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Static CMOS 2-input NOR Gate
VDD A B A F=(A or B) B A 0 0 1 1 B F 0 1 0 1 1 0 0 0
A B Output is 0 when either of the N-transistors is on.
NOR Gate: Symbolic Layout
VDD A B A F B B A F
VDD
A B
VSS
Characteristics of Static CMOS Logic
Restoring logic: can cascade gates indefinitely without loss of signal level.
Facilitates composition; construct complex systems from simple components Key to logic synthesis and silicon compilation
Static power dissipation essentially zero.
Power consumed only when switching.
As a load, looks like a capacitor.
High fan-out.
Fan-in limited by series transistors in NAND and NOR tree. A safe logic family, but not the fastest or most dense.
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MOS Transistor
Scalable CMOS
L = channel length W = channel width Metal
VDD L W
Poly-Si Gate
Saturation drain current: ID = k'W 2 (VGS VTH ) 2 L
p+ or n+ diffusion
VSS
Metal
ID=drain current VGS=drain-to-source voltage VTH=threshold voltage k=process dependent parameter
W and L are key performance parameters Scalable design rules = 2 x minimum feature size (critical dimension) Layout features scale proportionally 1970: = 100 m 1990: = 1 m 2000: = 0.18 m
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Layout Design Rules Minimum widths & spacing for layout elements.
Ensures device can be fabricated and will work as intended. Specific to process. Obtain from process vendor.
2 2 2 2 N+ or P+ 1 Poly 2 2 2 2
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3 Units =
Why do we need Layout Design Rules?
1. Ensure adequate separation and electrical isolation between structures on the chip. 2. Ensure adequate overlap to achieve correct alignment. Lithographic fabrication processes have limits: Optical limits of resolution Limits of alignment precision Diffusion profiles, continued diffusion Errors in coverage, edge failure, e.g. metal plugs in vias Design rules act as a contract between designer and fabrication house: If the design rules are obeyed, the fab guarantees the chip will function correctly on the test signals provided.
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Some Factors Affecting Inverter Performance
VDD
Channel R&C Contact resistance
Gate Resistance
In
Gate Capacitance Channel R&C
Load Capacitance
Contact resistance
VSS
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Inverter Switching Characteristics
VDD In In Out
VDD
0
VDD
time
Out
0
Propagation Delay
Temporal:
Channel resistance and parasitic capacitance produce RC delay
VDD
Vin
Input/Output characteristic:
Balance n- and p-channel gains to switch states at VDD/2 VDD
VDD/2
Vout
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Cell Layout Performance Issues
Resistance of a conductor (metal, poly) is proportional to aspect ratio (L/W: ohms/square). Capacitance of a conductor is proportional to area. To increase speed and drive power of a transistor, increase the channel width. Also increases power consumption. Use plenty of contacts to VDD and VSS to reduce power supply and ground bounce (noise). Transistor sizing p-channel resistance > n-channel resistance Hole mobility < electron mobility For symmetric switching, make p-channel wider than n-channel.
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Circuit Performance Estimation
Actual performance measures must consider layout. Pre-Layout, Post-Synthesis Simple circuit models, ignore interconnects e.g. use fan-in and fan-out to estimate delays Post-Layout Use SPICE to accurately model performance Use Spice Parameter Extraction to get parasitic parameters from: 1. Layout files 2. Process description
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Simple Memory Circuit: D Latch
D
0 1 S
Critical Parameters to Guarantee Valid Data is Latched tSU = Setup Time Time before clock when input must be stable tH = Hold Time Time after clock when input must be stable
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Clock Clock
tSU tH
D Q
Positive Edge Triggered D Flop-Flop
Input and output separated in time. D
0 1 S
QM
0 1 S
Q
D Q
Clock Master Clock QM Q
Clock Slave
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Synchronous Sequential Logic
Inputs Next State Logic Control Signals D Outputs Q State Register State Output Logic
Clock
Next state = f(current state, inputs) Controls signals stabilize on low clock period New state latched in falling clock edge
Clock State Vector State n Next-State Logic
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State n+1
State n+2
State n+3
Standard Logic Cells
Hand layout of a complex chip is tedious and expensive.
Optimal performance requires careful consideration of topology, fan in and fan out. Transistors must be sized for each case.
Instead, divide design into standard set of logic cells.
Custom design, layout and optimize each cell. Design cells so they can be tiled to produce complex designs. May be parameterized by drive strength (fanout) Physically designed to same height, so they can be abutted.
Some typical standard logic cells
D Q
AND-OR-Invert Flip-Flop 0 1 S Mux Buffer
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CMOS Summary
Silicon CMOS is the preferred logic family today. Complementary property gives balanced switching, low power. Excellent noise immunity. Restoring logic allows gates to be cascaded indefinitely.
Increasingly, digital CMOS is available as standard cells. CMOS Standard cells enable automatic circuit synthesis and semi-custom design. Full custom designers optimize the cells at layout level.
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