SUBMITTED BY:

SULOCHNANA GAUTAM MNNIT,ALLAHABAD

Semiconductor Technologies
VEDANT
VLSI DESIGN EDUCATION AND TRAINING LUCKNOW CENTRE

To Whom It May Concern This is to certify that SULOCHANA GAUTAM have successfully completed their project on:

VHDL code for VMC in VHDL

CERTIFIED BY:

MR. AMIT CHANDRA

Mr.Sachin Kr. Kanodia

(Project Guide)

(Head)

ACKNOWLEDGEMENT
No academic endeavor can be single handedly accomplished. This work is no exception. At the outset, we would like to record our gratitude to Mr. Sachin Kr. Kanodia for initiating us into this training. We sincerely acknowledge our thanks to our project guide Ms. Anupam Maurya, Mr. Amit Chandra, Mr.Satish Chandra & Mr. Anil Kumar for their valuable suggestions and time to time consultation. Last, but not the least, we would like to thank all the staff of VLSI Design Department, Semiconductor Laboratory (SCL), Vedant, Lucknow especially Ms. Charu Agarwal for their kind cooperation and assistance during our training period.

PREFACE
The evolution of Very large scale integration (VLSI) technology has developed to the point where millions of transistors can be integrated on a single die or chip where integrated circuits once filled the role of subsystem component partitioned at analog-digital boundaries. They now integrate complete systems on a chip by combining both analog-digital functions. Complementary metal oxide semiconductors technology has been the mainstay in mixed signal implementations because it provides density and power savings on the digital side, and a good mix of components for analog design. Due in part to the regularity and granularity of digital circuit computer aided design (CAD) methodologies have been very successful in automating the design of digital systems given a behavioral description of the function desired. Such is not the case for analog circuit design. Analog design still requires a hands on design approach in general. Moreover many of the design techniques used for discrete circuits are not applicable to the design of analog /mixed signal VLSI circuits. It is necessary to examine closely the design
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process of analog circuit and to identify those principles that will increase design productivity and the designers chances for success.

CONTENT

Page no.

SEMICONDUCTOR TECHNOLOGIES VEDANT INTRODUCTION TO VLSI INTRODUCTION TO VHDL IEEE LIBRARIES INTRODUCTION TO VMC VHDL CODE AND RTL SCHEMATIC WAVEFORM BIBLIOGRAPHY

06 08 09 12 14 15 18 41 42

SEMICONDUCTOR TECHNOLOGIESVEDANT
AN ISO 9001:2000 CERTIFIED INSTITUTION

Semiconductor Technologies has always been in sync with the future. It has understood and appreciated the needs of India, its people and its ever-growing industry. Over the last six 20 years tell the saga of VEDANT contribution in leading the national effort in the vital areas of microelectronics.

M/s Semiconductor Technologies-VEDANT is Indias premier VLSI Design & Embedded System Design organization since 2002. While VEDANT is Indias pioneer in the field of VLSI Design & Embedded System Design and Testing. VEDANT is providing Education & Training on VLSI Design & Embedded System Design through state-of-the-art lab facilities, equipped with the Industry Standard tools. VLSI
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Design / Embedded Systems Design Engineer design such Silicon chipsmaking a career in VLSI Design / ESD is highly respected & rewarding one. Furthermore we would like to bring in your notice that VEDANT is a member of Indian Semiconductor Association as well. SemiconductoR Technologies-VEDANT (Now an ISO 9001: 2000 Certified Institution) is center for the training crafted in VLSI/ESD education module followed with VLSI Design software along with the FPGA programming & 8051 Microcontroller kit.

VEDANT
VEDANT (VLSI design and training) is one of the prestigious projects of SCL, a pioneer with vertically integrated facility in the country. SCL VEDANT program covers the complete spectrum of VLSI design inclusive of front end, back end and provides of exposure to the IC fabrication process. Industry standard CAD tools are used for the purpose of training backed up by project work under the guidance of experts. VEDANT (LUCKNOW CENTER) is the institute, which provides training in VLSI design to students. The working environment is concentrated on front-end design process. It runs two programs PG diploma in VLSI designing of four months and certificate course of two months. It also provides Summer & Winter Training in VLSI Design or Embedded System. It has an advanced lab which is equipped with latest industry standard Electronic Design Automation (EDA) and FPGA tools and 8051 Development Kits inclusive of Model Sim 6.0a Xilinx tools FPGA Kit 8051 Development Kit
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Keil Software Flash Magic (Rom burning)

INTRODUCTION TO VLSI
For any given design, if the architecture of the fixed LSI and VLSI blocks suit the application then the design time is considerably shortened. When a one-chip microprocessor is not quite suitable, micro programmable architectures can often provide sufficient customization. Micro programmable architectures, such as bit-slice, allow a closer control over the architecture but not total control. The basic building blocks are still designed by the chip manufacturer for generic applications. Bit-slice architectures include interruptible sequencers and 32-bit ALUs. The customization of the bit-slice modules to an application is done through customer-designed module interconnection, the implemented commands and their sequences. The commands or instruction set is called the micro-program for the design. ASIC (VLSI, VHLSI) The 1980s saw the acceptance of ASICs ( Application Specific Integrated Circuits), VLSI devices large enough to allow designers to implement architectures that were suited to solving the design problem rather than forcing one architecture to solve everything. It was the natural extension to the bit-slice architectures, where some control of architecture was possible through microprogramming but where the basic building blocks were fixed designs. Not far behind the ASIC and ASIC developments, multimedia and design integration saw a need to incorporate analog functions into digital systems. For years the trend had been away from analog design as a chosen career and now there was a shortage of design engineers. First came massive re-training of internal staff as companies struggled to cope.
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Then came the creation of Electrically Programmable Analog Circuit (EPAC) and related devices. Application- specific solutions also includes the standard product mix where the market for a device is so large that product are developed specific to a mass application. PCI controllers is an example where one interface controller is targeted to handle the interface for many devices and device types, the control problem tailored to the device via programming. The application-specific customization of the design solution allows the designer to have the creative power of a gate-level breadboard design while keeping the production advantages of VLSI. Over the years, there has been an evolution of the universal building blocks used by logic circuit designers. In the mid-1960s, there were SSI gates; NAND, NOR, EXOR, and NOT or INVERT. In the early 1970s, MSI blocks, registers, decoders, multiplexers, and other blocks made their appearances. In the late 1970s, ALUs (arithmetic logic units) with on-board scratchpad registers, interrupt controllers, micro program sequencers, ROMs/PROMs, and other LSI devices up to and including a complete one-chip microprocessor (control, ALU and registers) became readily available. (And from this the PC was born.) SSI (small scale integration) is defined here to include chips containing approximately 2-10 gates. MSI (medium scale integration) is used for chips containing 20-100 gates. LSI (large scale integration) ships contain 200-1000 gates, with the upper limit continually extending as VLSI (very large scale integration) became a reality. In the mid-1980s, ASIC (application-specific integrated circuits) ranged from 1000 gates to 20,000 gates (bipolar technology) or 200,000 (CMOS technology).

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INTRODUCTION TO VHDL
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Excel VHDL is a user friendly windows based package which encapsulates the powerful Simily VHDL engine. A typical VHDL source file contains zero or more design units. Examples of design units are entity, architecture, package, etc. When a VHDL source file is compiled, the results of successful compilation are stored in a library .So, in effect; the design units contained within the VHDL source file are placed in a library. A design unit that has been compiled into one library can reference other designs units in any other library through the use of clauses and library statements. In VHDL, the current working library is always called work. When using a VHDL compiler or simulator, there is always a concept of a current working library. If no particular library is specified as a current working library, the current working library is assumed to be work. You can associate the work library with any other library. There are two kinds of design units: Primary and Secondary design units. The design units of type entity, package and configuration are primary design units. Design units or type architecture and package body are secondary design units. Secondary design units are always associated with a primary design unit. Secondary units typically contain the implementation of their primary units.

SIMPLE RULES TO REMEMBER

All primary units in a given library must have unique names. Note: VHDL language actually allows the entity to have the same name, as one of its configurations but VHDL Similar requires that all primary units have unique names in a given library. All secondary units for a given primary unit must also be named uniquely. A primary design and its associated design unit must both reside in the same library.

IEEE LIBRARIES
There is a VHDL standard library with a special name std. This library and its contents (the packages standard and textio) are built
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into the tools and cant be controlled. This also means that you cant have user defined library called std. The other IEEE libraries are stored I lib folder of the installation directory. The source code is present in IEEE folder and the compiled code is present in the IEEE.SYM folder. You may view the source code folder to see the definitions for use in your code.

Introduction to VMC
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A vending machine provides various snacks, beverages, and other products to consumers. The idea is to vend products without a cashier. Items sold via vending machines vary by country and region. Patrons may also buy nonfood items like newspapers or DVDs. One company selling the latter is Red box in the United States. In some countries, merchants may sell alcoholic beverages such as beer through vending machines, while other countries do not allow this practice (usually because of dram shop laws). Cigarettes were commonly sold in the United States through these machines, but this practice is increasingly rare due to concerns about underage buyers. Sometimes a pass has to be inserted in the machine to prove one's age. In some countries like Germany and Japan, by contrast, cigarette machines are still common. Vending machines were used at airports from the 1950s well into the 1970s to sell life insurance policies covering death in the event that the buyer's flight crashed. Such policies were quite profitable, because the risk of any given flight crashing was (and remains) very low, but this practice gradually disappeared due to the tendency of American courts to strictly construe such policies against their sellers, such as Mutual Omaha.

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The VMC i.e. the Vending Machine Controller is a basic machines which we used to see in our daily life at many places e.g. at malls, shops, etc. These machines are basically installed to dispense the commodity i.e. used regularly. It is for anything like ATM machines (whose basic work to dispense money after verification of the authorized person), may be for cold drinks where the person does not have to wait for the shopkeeper to open the shop and then only get the required things. So, the basic idea behind this project to supply a particular kind of things as per the request of the customer, here we are implementing a simple basic idea to develop the vending machine. But it doesnt mean that the idea stops here it just give us a brief about the approach and we can further enhance the idea upto any level. The vending machine is totally based on different states, which we engineers used to call the state machine or FSM. This project is based on this and it is for a cold drink i.e. it dispense the cold drink only after the customer puts money into this.

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Assumptions: The circuit reads signals from a coin input unit and sends outputs to a change dispensing unit and a drink dispensing unit. Here are the design parameters: This project assumes that only one kind of soft drink is dispensed. This is a clocked design with CLK and RESET input signals. The price of the drink is 10 rupees.

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CODE for VMC

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity vmc_mc_xtrnal is Port ( clk,rst : in STD_LOGIC; cancel :in bit; coin:in integer:=0; ocoin1,ocoin2,ocoin5,ocoin10 : out integer; fdisp : out STD_LOGIC); end vmc_mc_xtrnal; architecture Behavioral of vmc_mc_xtrnal is signal change :integer; signal disp:std_logic; signal emp: bit; component controller is Port ( clk,rst : in STD_LOGIC ; emp,cancel:in bit:='0'; coin:in integer:=0; disp : out STD_LOGIC:='0'; change :out integer:=0); end component; component money_changer is Port ( clk,rst : in STD_LOGIC; coin : in integer:=0; change : in integer:=0; ocoin1,ocoin2,ocoin5,ocoin10 : out integer:=0); end component; component cold_storage is Port ( clk,rst : in STD_LOGIC; disp: in STD_LOGIC; fdisp : out STD_LOGIC; emp : out bit:='0'); end component; begin A1: controller port map(clk,rst,emp,cancel,coin,disp,change); A2:money_changer port map(clk,rst,coin,change,ocoin1,ocoin2,ocoin5,ocoin10); A3:cold_storage port map(clk,rst,disp,fdisp,emp); end Behavioral; CONTROLLER 19

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity controller is Port ( clk,rst : in STD_LOGIC ; emp,cancel:in bit:='0'; coin:in integer:=0; disp : out STD_LOGIC:='0'; change :out integer:=0); end controller; architecture Behavioral of controller is type state is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9); signal st:state; signal chan:integer:=0; begin process(st,clk,cancel,coin,rst,emp) begin if rst='1' then chan<=0; st<=s0; change<=0; disp<='0'; elsif clk'event and clk='1' then if cancel='1' then st<=s0; change<=chan; disp<='0'; chan<=0; elsif emp='1' and coin=0 then change<= chan; disp<='0'; chan<=0; elsif emp='1' and coin/=0 then change<= chan+coin; disp<='0'; chan<=0; elsif cancel='1' and coin=0 then 20

change<= 0; disp<='0'; else if coin=1 then case st is when s0=>st<=s1; chan<=1; disp<='0'; change<=0; when s1=>st<=s2; chan<=chan+1; disp<='0'; change<=0; when s2=>st<=s3; chan<=chan+1; disp<='0'; change<=0; when s3=>st<=s4; chan<=chan+1; disp<='0'; change<=0; when s4=>st<=s5; chan<=chan+1; disp<='0'; change<=0; when s5=>st<=s6; chan<=chan+1; disp<='0'; change<=0; when s6=>st<=s7; chan<=chan+1; disp<='0'; change<=0; when s7=>st<=s8; chan<=chan+1; 21

disp<='0'; change<=0; when s8=>st<=s9; chan<=chan+1; disp<='0'; change<=0; when s9=>st<=s0; disp<='1'; chan<=10,0 after 10ps; change<=0; end case; elsif coin=2 then case st is when s0=>st<=s2; chan<=chan+2; disp<='0'; when s1=>st<=s3; chan<=chan+2; disp<='0'; change<=0; when s2=>st<=s4; disp<='0'; chan<=chan+2; change<=0; when s3=>st<=s5; disp<='0'; chan<=chan+2; change<=0; when s4=>st<=s6; disp<='0'; chan<=chan+2; change<=0; when s5=>st<=s7; chan<=chan+2; disp<='0'; change<=0; when s6=>st<=s8; disp<='0'; chan<=chan+2; change<=0; when s7=>st<=s9; disp<='0'; chan<=chan+2; change<=0; when s8=>st<=s0; 22

disp<='1'; change<=0; chan<=10,0 after 10ps; when s9=>st<=s0; disp<='1'; change<=1; chan<=10,0 after 10ps; end case; elsif coin=5 then case st is when s0=>st<=s5; chan<=chan+5; disp<='0'; change<=0; when s1=>st<=s6; chan<=chan+5; disp<='0'; change<= 0; when s2=>st<=s7; chan<=chan+5; disp<='0'; when s3=>st<=s8; chan<=chan+5; disp<='0'; change<=0; when s4=>st<=s9; chan<=chan+5; disp<='0'; change<=0; when s5=>st<=s0; disp<='1'; chan<=10,0 after 10ps; change<=0; when s6=>st<=s0; disp<='1'; chan<=10,0 after 10ps; change<=1; when s7=>st<=s0; disp<='1'; chan<=10,0 after 10ps; change<=2; when s8=>st<=s0; disp<='1'; 23

chan<=10,0 after 10ps; change<=3; when s9=>st<=s0; disp<='1'; chan<=10,0 after 10ps; change<=4; end case; elsif coin=10 then case st is when s0=>st<=s0; disp<='1'; chan<=10,0 after 10ps; change<=0; when s1=>st<=s0; disp<='1'; chan<=10,0 after 10ps; change<=1; when s2=>st<=s0; disp<='1'; chan<=10,0 after 10ps; change<=2; when s3=>st<=s0; disp<='1'; chan<=10,0 after 10ps; change<=3; when s4=>st<=s0; disp<='1'; chan<=10,0 after 10ps; change<=4; when s5=>st<=s0; disp<='1'; chan<=10,0 after 10ps; when s6=>st<=s0; disp<='1'; chan<=10,0 after 10ps; change<=6; when s7=>st<=s0; disp<='1'; chan<=10,0 after 10ps; change<=7; when s8=>st<=s0; 24

disp<='1'; chan<=10,0 after 10ps; change<=8; when s9=>st<=s0; disp<='1'; chan<=10,0 after 10ps; change<=9; end case; else disp<='0'; change<=chan; end if; end if; end if; end process; end Behavioral; MONEY CHANGER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity money_changer is Port ( clk,rst : in STD_LOGIC; coin : in integer:=0; change : in integer:=0; ocoin1,ocoin2,ocoin5,ocoin10 : out integer:=0); end money_changer; architecture Behavioral of money_changer is signal coin1,coin2,coin5,coin10:integer:=0; begin process(clk,rst,change,coin) begin if rst='1' then coin1<=50; 25

coin2<=50; coin5<=50; coin10<=50; ocoin1<=0; ocoin2<=0; ocoin5<=0; ocoin10<=0; elsif clk'event and clk='1' then case change is when 0=>case coin is when 1=>coin1<=coin1+1; when 2=>coin2<=coin2+1; when 5=>coin5<=coin5+1; when 10=>coin10<=coin10+1; when others=>null; end case; ocoin1<=0; ocoin2<=0; ocoin5<=0; ocoin10<=0; when 1=> if coin1>0 then ocoin2<=0; ocoin1<=1; coin1<=coin1-1 after 25 ps; ocoin5<=0; ocoin10<=0; else report "coin1 over"; end if; when 2=>if coin2>0 then ocoin1<=0; ocoin2<=1; coin2<=coin2-1; ocoin5<=0; ocoin10<=0; elsif coin1>=2 then ocoin1<=2; coin1<=coin1-2; ocoin2<=0; ocoin5<=0; ocoin10<=0; else report "coin1 and coin2 over"; end if; when 3=> 26

if coin2>0 and coin1>0 then ocoin2<=1; coin2<=coin2-1; ocoin1<=1; coin1<=coin1-1; ocoin5<=0; ocoin10<=0; elsif coin1>=3 then ocoin1<=3; coin1<=coin1-3; ocoin2<=0; ocoin5<=0; ocoin10<=0; else report "coin1 and coin2"; end if; when 4=> if coin2>=2 then ocoin1<=0; ocoin2<=2; coin2<=coin2-2; ocoin5<=0; ocoin10<=0; elsif coin2>=1 and coin1>=2 then ocoin2<=1; coin2<=coin2-1; ocoin1<=2; coin1<=coin1-2; ocoin5<=0; ocoin10<=0; elsif coin1>=4 then ocoin1<=4; coin1<=coin1-4; ocoin2<=0; ocoin5<=0; ocoin10<=0; else report "coin2 and coin1 over"; end if; when 5=> if coin5>=1 then ocoin1<=0; ocoin2<=0; ocoin5<=1; coin5<=coin5-1; 27

ocoin10<=0; elsif coin2>=2 and coin1>=1 then ocoin2<=2; coin2<=coin2-2; ocoin1<=1; coin1<=coin1-1; ocoin5<=0; ocoin10<=0; elsif coin1>=1 then ocoin1<=5; coin1<=coin1-5; ocoin2<=0; ocoin5<=0; ocoin10<=0; else report "coin5,coin2,coin5 over"; end if; when 6=> if coin5>=1 and coin1>=1 then ocoin5<=1; coin5<=coin5-1; ocoin1<=1; coin1<=coin1-1; ocoin2<=0; ocoin10<=0; elsif coin2>=3 then ocoin2<=3; coin2<=coin2-3; ocoin1<=0; ocoin5<=0; ocoin10<=0; elsif coin2>=2 and coin1>=2 then ocoin2<=2; coin2<=coin2-2; ocoin1<=2; coin1<=coin-2; ocoin5<=0; ocoin10<=0; elsif coin2>=1 and coin1>=4 then ocoin2<=1; coin2<=coin2-1; ocoin1<=4; coin1<=coin1-4; ocoin5<=0; 28

ocoin10<=0; elsif coin1>=6 then ocoin1<=6; coin1<=coin1-6; ocoin2<=0; ocoin5<=0; ocoin10<=0; else report "coin5,coin2,coin1 over"; end if; when 7=>if coin5>=1 and coin2>=1 then ocoin5<=1; coin5<=coin5-1; ocoin2<=1; coin2<=coin2-1; ocoin1<=0; ocoin10<=0; elsif coin2>=3 and coin1>=1 then ocoin2<=3; coin2<=coin2-3; ocoin1<=1; coin1<=coin1-1; ocoin5<=0; ocoin10<=0; elsif coin2>=2 and coin1>=3 then ocoin2<=2; coin2<=coin2-2; ocoin1<=3; coin1<=coin1-3; ocoin5<=0; ocoin10<=0; elsif coin1>=7 then ocoin2<=0; ocoin1<=7; coin1<=coin1-7; ocoin5<=0; ocoin10<=0; end if; when 8=>if coin5>=1 and coin2>=1 and coin1>=1 then ocoin5<=1; coin5<=coin5-1; ocoin1<=1; coin1<=coin1-1; ocoin2<=1; coin2<=coin2-1; 29

ocoin10<=0; elsif coin2>=4 then ocoin2<=4; coin2<=coin2-4; ocoin1<=0; ocoin5<=0; ocoin10<=0; elsif coin2>=3 and coin1>=2 then ocoin2<=3; coin2<=coin2-3; ocoin1<=2; coin1<=coin1-2; ocoin5<=0; ocoin10<=0; elsif coin2>=2 and coin1>=4 then ocoin2<=2; coin2<=coin2-2; ocoin1<=4; coin1<=coin1-4; ocoin5<=0; ocoin10<=0; elsif coin2>=1 and coin1>=6 then ocoin2<=1; coin2<=coin2-1; ocoin1<=6; coin1<=coin1-6; ocoin5<=0; ocoin10<=0; elsif coin1>=8 then ocoin2<=0; ocoin1<=7; coin1<=coin1-7; ocoin5<=0; ocoin10<=0; end if; when 9=>if coin5>=1 and coin2>=2 then ocoin5<=1; coin5<=coin5-1; ocoin1<=0; ocoin2<=2; coin2<=coin2-2; ocoin10<=0; elsif coin5>=1 and coin2>=1 and coin1>=2 then 30

ocoin5<=1; coin5<=coin5-1; ocoin1<=2; coin1<=coin1-2; ocoin2<=1; coin2<=coin2-1; ocoin10<=0; elsif coin5>=1 and coin1>=4 then ocoin5<=1; coin5<=coin5-1; ocoin1<=4; coin1<=coin1-4; ocoin2<=0; ocoin10<=0; elsif coin2>=4 and coin1>=1 then ocoin2<=4; coin2<=coin2-4; ocoin1<=1; coin1<=coin1-1; ocoin5<=0; ocoin10<=0; elsif coin2>=3 and coin1>=3 then ocoin2<=3; coin2<=coin2-3; ocoin1<=3; coin1<=coin1-3; ocoin5<=0; ocoin10<=0; elsif coin2>=2 and coin1>=5 then ocoin2<=2; coin2<=coin2-2; ocoin1<=5; coin1<=coin1-5; ocoin5<=0; ocoin10<=0; elsif coin2>=1 and coin1>=7 then ocoin2<=1; coin2<=coin2-1; ocoin1<=7; coin1<=coin1-7; ocoin5<=0; ocoin10<=0; elsif coin1>=9 then ocoin2<=0; ocoin1<=9; 31

coin1<=coin1-9; ocoin5<=0; ocoin10<=0; end if; when 10=>ocoin10<=1; coin10<=coin10-1; ocoin2<=0; ocoin1<=0; ocoin5<=0; when others=>ocoin1<=0; ocoin2<=0; ocoin5<=0; ocoin10<=0; end case; end if; end process; end Behavioral;

COLD STORAGE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity cold_storage is Port ( clk,rst : in STD_LOGIC; disp: in STD_LOGIC; fdisp : out STD_LOGIC; emp : out bit:='0'); end cold_storage; architecture Behavioral of cold_storage is signal cd:integer:=10; begin process(rst,clk,disp) 32

begin if rst='1' then fdisp<='0'; cd<=10; emp<='0'; elsif clk'event and clk='1' then if disp='1' then if cd>0 then cd<=cd-1; fdisp<='1'; else fdisp<='0'; emp<='1'; end if; else fdisp<='0'; cd<=cd; end if; end if; end process; end Behavioral;

Block diagram of vmc

Internal Schematic diagram of VMC

RTL for controller of VMC

internal of controller
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RTL for money changer of VMC

Internal of money changer

RTL for cold storage of VMC

Internal of cold storage

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WAVEFORM OF VMC

BIBLIOGRAPHY
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Following is the list of books from which help has been taken for the completion of this project. 1 2 3 VHDL-PRIMER MODERN DIGITAL ELECTRONICS DIGITAL DESIGN J.Bhasker R.P.Jain MorisMano

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