18th Telecommunications forum TELFOR 2010 Serbia, Belgrade, November 23-25, 2010.

Abstract This paper presents an improved first

generation current conveyor. The proposed circuit is based
on a CMOS translinear loop and self-cascode current
mirrors. The structure of the circuit is analyzed and
compared with a classical CCI structure. PSpice simulation
results for the proposed circuit in 0.35m CMOS technology
are given to verify the theoretical analysis.
Keywords current conveyor, self-cascode mirror,
CMOS.
I. INTRODUCTION
INCE Sedra published first generation current
conveyor (CCI) (1968), current conveyor based
circuits have received lots of attention in analog signal
processing applications, such as filter [1] function
generator [2], impedance function synthesis [3], etc. [4].
CCs are unity-gain amplifiers widely used by analog
designers, in particular because they offer a number of
advantages, such as better linearity, wider bandwidth, and
design flexibility over conventional voltage-mode active
devices.
Several types of CC exist covering first, second (CCII)
and third generation (CCIII). Whilst CCII is considered
the most versatile and used CC, the first generation CCI is
well known for its simplicity.

Z
X
Y
Z
X
Y
V
I
V
I
V
I
0 1 0
0 0 1
0 1 0
(1)

=
= =
Y x
x z Y
V V
I I I
(2)
The definition matrix (1) along with input-output
equations (2) and nodes impedance level (Table 1)
presents the main characteristics of the ideal CCI (CCI+
and CCI-).
TABLE 1: CCI IMPEDANCE LEVELS
Node (CCI) Impedance Level
X 0
Y
Z
The CCI symbol and CMOS structure are given in Fig.
1 and Fig. 2.
A good CCI structure must provide several features:
Beniamin Drgoi is with the Faculty of Electronics and
Telecommunications, University Politehnica of Timisoara, Bul. V.
Parvan nr. 2, 300223, Timioara, Romania, (phone: +40745459956; e
mail: beniamin.dragoi@etc.upt.ro).
very low X input impedance, very high Y and Z
impedances, unity voltage and current gains between
ports, large dynamic input and output current and voltage
ranges.
Fig. 1. CCI symbol
Fig. 2. Typical CMOS CCI+ structure
II. IMPROVEDSELF-CASCODE CCI
A. Simple current mirror based CCI structure
The typical CMOS structure (Fig.2) is a class AB
current conveyor that offers the advantages of high
dynamic range, wide bandwidth and non-slew rate limited
performance. Due to the low quality of the simple current
mirror (CM) this CCI structure assures moderate
performances in respect of input/output impedance.
Equations for input and output resistances for CCI in
Fig.2 are given in (3), (4) and (5).
|
|
.
|

\
| +
+
+
|
|
.
|

\
| +
+
+
~
8 6
8 6
6 5
7 5
2 1
3 1
4 2
4 2
||
||
m m
ds ds
m m
ds ds
m m
ds ds
m m
ds ds
X
g g
g g
g g
g g
g g
g g
g g
g g
R
(3)
7 3
||
o o Y
r r R ~ (4)
oP oN Z
r r R || ~ (5)
To decrease the input resistance on port X, R
X
, and
increase input resistance on port Y, R
Y
, and output
resistance on port Z, R
Z
, the designer must increase the
CMs output resistance. An efficiently improvement cannot
Improved first generation current conveyor
based on self-cascode current mirror
Beniamin Drgoi, Member, IEEE
S
799
be obtained due to CMs structure. This limitation imposes
to replace simple CM with better current mirrors.
B. Cascode mirror based CCI structure
Several papers present AB class current conveyors
using improved current mirrors: cascode mirror [5], high-
swing mirror [6], low voltage self-cascode [7], etc. Fig. 3
shows a CCI based on cascode current mirror (CCM).
Fig. 3. Cascode mirror based CCI structure
This current mirror structure provides much greater
output resistance (6) and thus CCI input and output
resistances are improved.
) (
3 3 3 o m A o o
r g r r = (6)
CCM requires minimum input (7) and output voltage
(8) larger than CM to keep all transistors in saturation.
DSsat th output
V V V * 2
3 min ,
+ = (7)
) ( * 2
3 3 min , A DSsat A th input
V V V + = (8)
Using CCMs instead of CMs in CCI dramatically
reduce input and output voltage dynamic ranges. This is a
disadvantage than cannot be accepted for circuits that use
low voltage power supply.
Replacing CCM with high-swing current mirror is out
of purpose of this paper because requires additional bias
circuitry that increases CCI complexity.
C. Self cascode mirror based CCI structure
The purpose of this paper is to propose and analyze a
new AB class CCI structure based on self-cascode mirrors
(SCCM). The proposed circuit is given in Fig. 4 and based
on 6 SCCMs [8]. This structure maintains CCI circuit
complexity as low as possible but provides good
performance in terms of input and output resistances and
voltage dynamic range.
Fig. 4. New self-cascode CCI+
A well-designed SCCM must assure that all transistors
work in saturation. Reference [8] shows a condition (9) to
keep transistors T3A and T4A in saturation. This is easy to
fulfill in a multi-threshold CMOS process.
4 4 4 DSsat th A th
V V V > (9)
In a standard CMOS technology this condition can be
accomplish using SCE (short-channel effect) and (10) [9].
2
4 4
4 4
4
4
1
|
|
.
|

\
|

s
A th A GS
th A th A
V V
V V
n
n

(10)
n slope factor (about 1.3), =CoxW/L.
Reference [10] presents a methodology based on SCE
and RSCE (reverse short-channel effect) [11] useful to
design both pMOS and nMOS SCCMs.
This kind of current mirror shows an output resistance
similar to that of the cascode mirror but input and output
voltage close to the simple CM. Table 2 gives a
comparative view for output impedance, input and output
voltage for the three current mirrors previous presented. It
is obvious that SCCM is better than CM and equal with
CCM regarding output resistance. SCCM demands a
minimum input voltage similar with CM but much less
than CCM. Minimum output voltage required by SCCM is
less that similar voltage for CCM and very close to CM
once. This SCCM shows improved output resistance
without affecting voltage dynamic ranges.
Input and output resistances for CCI in Fig. 4:
|
|
.
|

\
| +
+
+
|
|
.
|

\
| +
+
+
~
A m m m
A ds ds m ds
m m m
A ds ds m ds
m m m
A ds ds m ds
A m m m
A ds ds m ds
X
g g g
g g g g
g g g
g g g g
g g g
g g g g
g g g
g g g g
R
8 8 6
8 8 8 6
7 6 5
7 7 7 5
3 2 1
3 3 3 1
4 4 2
4 4 4 2
||
||
(11)
800
TABLE 2: CM, CCM AND SCCM MAINLY CHARACTERISTICS
Current mirror CM Cascode current mirror CCM Self cascade current mirror SCCM
Output resistance
3 o o
r r = ) (
3 3 3 o m A o o
r g r r = ) (
3 3 3 o m A o o
r g r r =
Minimum output voltage
A DSsat
V
3 DSsat th
V V * 2
3
+
DSsat A th th
V V V +
3 3
Minimum input voltage
3 3 DSsat th
V V + ) ( * 2
3 3 A DSsat A th
V V +
A DSsat A th
V V
4 4
+
A ds ds
m
A ds ds
m
Y
g g
g
g g
g
R
7 7
7
3 3
3
|| ~ (12)
oPA oP mP oNA oN mN Z
r r g r r g R || ~ (13)
Equations (11), (12) and (13) show that new CCI
structure achieves greater resistances on ports Y and Z and
smaller resistance on port X.
Fig. 5 shows CCI- structure based on self cascade
current mirror.
Fig. 5. Self-cascode CCI-
III. DESIGNCIRCUITS
Both circuits from Fig. 2 and Fig. 4 were designed in a
standard 0.35m CMOS technology. All the transistors in
Fig. 4 were designed to work in saturation mode using
(10) and SCE for sizing nMOS and RSCE for sizing
pMOS [10]. Table 3 and Table 4 show W and L sizes for
transistors in Fig. 2 and Fig. 4.
TABLE 3: W AND L SIZES FOR SELF-CASCODE CCI+
CCI+ new W[m] L[m]
T
1
, T
2
26 3.3
T
3
, T
4
, T
N
68.4 1
T
3A
, T
4A
, T
NA
3.8 0.65
T
5
, T
6
10.2 2.8
T
7
, T
8
, T
P
96 0.55
T
7A
, T
8A
, T
PA
32 3.4
TABLE 4: W AND L SIZES FOR TYPICAL CCI+
CCI+ typical W[m] L[m]
all nMOS 15 2.5
all pMOS 55.5 2.5
IV. SIMULATIONRESULTS
The circuit was simulated using PSpice. Using power
supplies of 2.5V and the sizes in Table 3 and Table 4
self-bias currents are 110A for Fig. 2 and 55A for Fig.4.
Table 5 shows the input and output impedances, voltage
and current gains, bias currents and active areas for the
proposed CCI+ and for a typical CCI+. For almost the
same active area the new CCI provides the same input
resistance on port X but the bias current is halved. There
are good improvements in respect of input impedance on
port Y 13.5 times and output impedance on port Z 8
times. Current gains and errors are reduced from 0.7%
to 0.11%. Voltage gain is reduced from 0.72% to 0.38%.
TABLE 5: NEW CCI+ VERSUS TYPICAL CCI+ PERFORMANCES
CCI+ new CCI+ Typical
Technology CMOS 0.35m, 2.5V
Active area 926 881 m
2
Bias current 55 110 A
Rx 20.02 19.12
Ry 6.86 0.507 M
Rz 10.89 1.36 M
V
X
/V
Y
() 0.9962 0.9928
I
Z
/I
X
() 1.0011 1.007
I
Y
/I
X
() 0.9989 0.993
Cy 105 130 fF
Cz 85 55 fF
Fig. 6 shows input and output impedances for both the
new CCI+ and a typical CCI+.
Fig. 6. Input/output impedances for new and typical CCI+
Fig. 7 presents the voltage tracking error between Y
and X ports. It can be seen that the input voltage range is
almost the same for the new CCI based on SCCM as for
the typical CCI based on CM.
801
Fig. 7. Input voltage tracking error between ports Y and X
To demonstrate the usefulness of the improved
features for the CCI next are presented two applications
for this circuit negative impedance convertor (NIC) and
negative admittance/impedance convertor (NAIC). Fig. 8
and Fig. 9 show these circuits.
v
i
v
i
Fig. 8. NIC based on CCI+
i
Y
i
X
i
Z
=i
X
=i
Y
R2
R1
Z
i2
CCI-
Y
X
Z-
Z2
i
i
Fig. 9. NAIC based on CCI-
NIC input impedance is given by (14) and NAIC input
impedance is given by (15)
1 1
Z
i
v
i
v
Z
Y
i
X
i
i
= = = (14)
2 1 2 2 1
2
2
1
R R Y R R
Z i
v
Z
i
i
i
= = =
(15)
Both circuits were simulated with typical CCI and new
CCI. Fig. 10 shows simulation results. Z
1
and Z
2
are
capacitors with value 10pF and resistors have equal
values, R
1
=R
2
=100k. For circuits designed using CCI
based on SCCM input impedances have extended
frequency ranges where close approximate an ideal
behavior. Frequency ranges are extended with more than
1.5 decades towards lower frequency. This improvement
is consequence of higher input and output resistance on
ports Y and Z for new first generation current conveyor.
Fig. 10. a) NAIC input impedance and b) NIC input
impedance for both new and typical CCI
V. CONCLUSION
This paper has presented a novel CCI structure based on
self-cascode current mirror. The results show that the
proposed circuit improves performances in respect of
input/output impedances and voltage/current gains
maintaining large dynamic voltage ranges.
REFERENCES
[1] Yamacli S., Ozcan S. and Kuntman H., Resistorless tunable KHN-
filter in current mode with CCCIIs and grounded capacitors
Proceedings of the 15th IEEE International Conference on
Electronics, Circuits and Systems, ICECS 2008, pp. 324-327, Aug.
- Sept. 2008, St. Julien's.
[2] Minhaj N. Multioutput current-controlled current conveyor-based
function generator Proceedings of the Conference ACT '09. pp.
424 427, Dec. 2009, Trivandrum, Kerala.
[3] Yuce E., Negative impedance converter with reduced nonideal
gain and parasitic impedance effects, IEEE Transactions on
Circuits and Systems I: Regular Papers. Vol. 55, Issue1, pp.276-
283.
[4] Di Carlo C., De Marcellis A., Stornelli V., Ferri, G. and Tiberio D.,
A novel LV LP CMOS internal topology of CCII+ and its
application in current-mode integrated circuits Proceedings of
Research in Microelectronics and Electronics, PRIME 2009. Ph.D.
pp.132 135, July 2009, Cork.
[5] Minaei S., A new high performance CMOS third generation
current conveyor (CCIII) and its application Electrical
Engineering 85. Pp.147153, Springer-Verlag.
[6] Calvo B., Celma S., Martinez P.A. and Sanz M.T., High-Speed
High-Precision CMOS Current Conveyor, Analog Integrated
Circuits and Signal Processing, pp.235238, Kluwer Academic
Publishers.
[7] Kaur J., Prakash N. and Rajput S.S., Low voltage high
performance self cascode CCII Proceeding of the IEEE
International Multitopic Conference, 2008. INMIC 2008. pp.7-11,
Dec, Karachi.
[8] Fujimori I., Low Voltage Self Cascode Current Mirror U.S.
Patent 5,966,005, Oct. 12.
[9] Zeki A. and Kuntman H., High-linearity Low-Voltage self-cascode
class AB CMOS current output stage Proceeding of the IEEE
International Symposium on Circuits and Systems, ISCAS 2000,
pp. 257-260 vol.4, May 2000, Geneva.
[10] Dragoi B., Researches concerning the design of CMOS integrated
sinusoidal oscillators Editura Politehnica, pp. 94-104, Timisoara,
Romania.
[11] Lu C.-Y. and Sung J.M., Reverse short-channel effects on
threshold voltage in submicrometer salicide devices, Electron
Device Letters, IEEE , Oct 1989, Vol. 10 Issue 10, pages 446 448.
802