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Aim of The Project: Features

This document discusses verifying an SPI Master Core using OVM methodology. It contains an introduction and abstract about SPI interfaces. Key features of the SPI Master Core include full duplex data transfer up to 128 bits, variable transfer word lengths, and independent Rx and Tx edges. Tests are written using the OVM methodology with a master and slave OVC, sequencer, driver, monitor, and scoreboard. Transactions randomize inputs like character length and direction. Coverage models all input parameter scenarios affecting data transmission like character length and edge polarity. Verification results and conclusions are presented.

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Yeshoda Mallikarjuna
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80 views4 pages

Aim of The Project: Features

This document discusses verifying an SPI Master Core using OVM methodology. It contains an introduction and abstract about SPI interfaces. Key features of the SPI Master Core include full duplex data transfer up to 128 bits, variable transfer word lengths, and independent Rx and Tx edges. Tests are written using the OVM methodology with a master and slave OVC, sequencer, driver, monitor, and scoreboard. Transactions randomize inputs like character length and direction. Coverage models all input parameter scenarios affecting data transmission like character length and edge polarity. Verification results and conclusions are presented.

Uploaded by

Yeshoda Mallikarjuna
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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INTRODUCTION

AIM OF THE PROJECT To verify SPI (Serial Peripheral Interface) Master Core by using OVM Methodology.

ABSTRACT Synchronous serial interfaces are widely used to provide economical board level interfaces between different devices such as microcontrollers, DACs, ADCs and other. Although there is no single standard for a synchronous serial bus, there are industry-wide accepted guidelines based on two most popular implementations: SPI Microwire

Many IC manufacturers produce components that are compatible with SPI and Microwire. The SPI Master core is compatible with both above mentioned protocols as master with some additional functionality. At the hosts side, the core acts like WISHBONE complaint slave devices.

Features
Full Duplex synchronous serial data transfer.

Variable length of transfer word up to 128 bits MSB or LSB first data transfer Rx and Tx on both rising and falling edge of serial clock independently 8 slave select lines Fully static synchronous design with one clock domain.

BLOCKDIAGRAM
TESTS

BLOCK DIAGRAM
TB Coverage

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Scoreboard

Master OVC Sequencer

Slave OVC Sequen cer Driver

Driver

Monitor r

Monito

Interface

DUT

TRANSACTION DETAILS
In the transactions, we randomize the Rx_neg, Tx_neg, char_length, DIVIDER, wb_data_i.

I/P and O/P OVC DETAILS


The input and output OVCs are Master and Slave OVCs. In the Master OVC, it is having the Sequencer, Agent, Sequence, Driver, and Monitor. The Slave OVC is also having Sequencer, Agent, Sequences, Driver and Monitor. The Master OVC part of verification deals with the configuration of several registers which are used in data transmission. Firstly, Slave select register is configured to select slave registers of receiver. Secondly, divider register is configured to generate serial clk from wb_clk_in of wishbone interface. Thirdly, control register of SPI core is configured to transmit data depending on character length, LSB, Tx_neg etc parameters affecting data transmission. For data transmission, the 8th bit of control register Go_busy is to set '1' after register configuration. Two events are triggered one after ss configuration and one after data transmission. The Slave OVC part of verification deals with driving of MISO depending on different events. The scoreboard part of verification deals with comparision of master data and slave data

VIRTUAL SEQUENCER AND VIRTUAL SEQUENCES Virtual Sequencer is used to control the existing physical sequence. Virtual Sequences is also used to control the existing physical sequences. we can control the tests in the TB using the virtual sequences. COVERAGE MODEL The coverage model of SPI design consists of several cover points and cross cover points which checks all the possible scenarios of input parameter which are affecting data transmission. The cover points are Tx_neg, Rx_neg, character length also above cover points are crossed together to get maximum coverage report.

RESULTS

CONCLUSION Thus verification is done for the SPI master core using OVM methodology.

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